1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import chisel3.util.experimental.decode._ 7import utils.XSError 8import xiangshan.backend.fu.FuConfig 9import xiangshan.backend.fu.vector.{Mgu, VecPipedFuncUnit} 10import xiangshan.ExceptionNO 11import yunsuan.VfpuType 12import yunsuan.vector.VectorConvert.VectorCvt 13import yunsuan.util._ 14 15 16class VCVT(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) { 17 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfcvt OpType not supported") 18 19 // params alias 20 private val dataWidth = cfg.dataBits 21 private val dataWidthOfDataModule = 64 22 private val numVecModule = dataWidth / dataWidthOfDataModule 23 24 // io alias 25 private val opcode = fuOpType(7, 0) 26 private val sew = vsew 27 28 private val isRtz = opcode(2) & opcode(1) 29 private val isRod = opcode(2) & !opcode(1) & opcode(0) 30 private val isFrm = !isRtz && !isRod 31 private val rm = Mux1H( 32 Seq(isRtz, isRod, isFrm), 33 Seq(1.U, 6.U, frm) 34 ) 35 36 private val lmul = vlmul // -3->3 => 1/8 ->8 37 38 val widen = opcode(4, 3) // 0->single 1->widen 2->norrow => width of result 39 val isSingleCvt = !widen(1) & !widen(0) 40 val isWidenCvt = !widen(1) & widen(0) 41 val isNarrowCvt = widen(1) & !widen(0) 42 val fire = io.in.valid 43 val fireReg = GatedValidRegNext(fire) 44 45 // output width 8， 16， 32， 64 46 val output1H = Wire(UInt(4.W)) 47 output1H := chisel3.util.experimental.decode.decoder( 48 widen ## sew, 49 TruthTable( 50 Seq( 51 BitPat("b00_01") -> BitPat("b0010"), // 16 52 BitPat("b00_10") -> BitPat("b0100"), // 32 53 BitPat("b00_11") -> BitPat("b1000"), // 64 54 55 BitPat("b01_00") -> BitPat("b0010"), // 16 56 BitPat("b01_01") -> BitPat("b0100"), // 32 57 BitPat("b01_10") -> BitPat("b1000"), // 64 58 59 BitPat("b10_00") -> BitPat("b0001"), // 8 60 BitPat("b10_01") -> BitPat("b0010"), // 16 61 BitPat("b10_10") -> BitPat("b0100"), // 32 62 ), 63 BitPat.N(4) 64 ) 65 ) 66 if(backendParams.debugEn) { 67 dontTouch(output1H) 68 } 69 val outputWidth1H = output1H 70 71 val outEew = RegEnable(RegEnable(Mux1H(output1H, Seq(0,1,2,3).map(i => i.U)), fire), fireReg) 72 private val needNoMask = outVecCtrl.fpu.isFpToVecInst 73 val maskToMgu = Mux(needNoMask, allMaskTrue, outSrcMask) 74 75 // modules 76 private val vfcvt = Module(new VectorCvtTop(dataWidth, dataWidthOfDataModule)) 77 private val mgu = Module(new Mgu(dataWidth)) 78 79 val vs2Vec = Wire(Vec(numVecModule, UInt(dataWidthOfDataModule.W))) 80 vs2Vec := vs2.asTypeOf(vs2Vec) 81 82 /** 83 * [[vfcvt]]'s in connection 84 */ 85 vfcvt.uopIdx := vuopIdx(0) 86 vfcvt.src := vs2Vec 87 vfcvt.opType := opcode 88 vfcvt.sew := sew 89 vfcvt.rm := rm 90 vfcvt.outputWidth1H := outputWidth1H 91 vfcvt.isWiden := isWidenCvt 92 vfcvt.isNarrow := isNarrowCvt 93 vfcvt.fire := fire 94 val vfcvtResult = vfcvt.io.result 95 val vfcvtFflags = vfcvt.io.fflags 96 97 /** fflags: 98 */ 99 val eNum1H = chisel3.util.experimental.decode.decoder(sew ## (isWidenCvt || isNarrowCvt), 100 TruthTable( 101 Seq( // 8, 4, 2, 1 102 BitPat("b001") -> BitPat("b1000"), //8 103 BitPat("b010") -> BitPat("b1000"), //8 104 BitPat("b011") -> BitPat("b0100"), //4 105 BitPat("b100") -> BitPat("b0100"), //4 106 BitPat("b101") -> BitPat("b0010"), //2 107 BitPat("b110") -> BitPat("b0010"), //2 108 ), 109 BitPat.N(4) 110 ) 111 ) 112 val eNumMax1H = Mux(lmul.head(1).asBool, eNum1H >> ((~lmul.tail(1)).asUInt +1.U), eNum1H << lmul.tail(1)).asUInt(6, 0) 113 val eNumMax = Mux1H(eNumMax1H, Seq(1,2,4,8,16,32,64).map(i => i.U)) //only for cvt intr, don't exist 128 in cvt 114 val eNumEffectIdx = Mux(vl > eNumMax, eNumMax, vl) 115 116 val eNum = Mux1H(eNum1H, Seq(1, 2, 4, 8).map(num =>num.U)) 117 val eStart = vuopIdx * eNum 118 val maskPart = srcMask >> eStart 119 val mask = Mux1H(eNum1H, Seq(1, 2, 4, 8).map(num => maskPart(num-1, 0))) 120 val fflagsEn = Wire(Vec(4 * numVecModule, Bool())) 121 122 fflagsEn := mask.asBools.zipWithIndex.map{case(mask, i) => mask & (eNumEffectIdx > eStart + i.U) } 123 124 val fflagsEnCycle2 = RegEnable(RegEnable(fflagsEn, fire), fireReg) 125 val fflagsAll = Wire(Vec(8, UInt(5.W))) 126 fflagsAll := vfcvtFflags.asTypeOf(fflagsAll) 127 val fflags = fflagsEnCycle2.zip(fflagsAll).map{case(en, fflag) => Mux(en, fflag, 0.U(5.W))}.reduce(_ | _) 128 io.out.bits.res.fflags.get := fflags 129 130 131 /** 132 * [[mgu]]'s in connection 133 */ 134 val resultDataUInt = Wire(UInt(dataWidth.W)) 135 resultDataUInt := vfcvtResult 136 137 private val narrow = RegEnable(RegEnable(isNarrowCvt, fire), fireReg) 138 private val narrowNeedCat = outVecCtrl.vuopIdx(0).asBool && narrow 139 private val outNarrowVd = Mux(narrowNeedCat, Cat(resultDataUInt(dataWidth / 2 - 1, 0), outOldVd(dataWidth / 2 - 1, 0)), resultDataUInt) 140 141 mgu.io.in.vd := resultDataUInt 142 mgu.io.in.vd := Mux(narrow, outNarrowVd, resultDataUInt) 143 mgu.io.in.oldVd := outOldVd 144 mgu.io.in.mask := maskToMgu 145 mgu.io.in.info.ta := outVecCtrl.vta 146 mgu.io.in.info.ma := outVecCtrl.vma 147 mgu.io.in.info.vl := Mux(outVecCtrl.fpu.isFpToVecInst, 1.U, outVl) 148 mgu.io.in.info.vlmul := outVecCtrl.vlmul 149 mgu.io.in.info.valid := io.out.valid 150 mgu.io.in.info.vstart := Mux(outVecCtrl.fpu.isFpToVecInst, 0.U, outVecCtrl.vstart) 151 mgu.io.in.info.eew := outEew 152 mgu.io.in.info.vsew := outVecCtrl.vsew 153 mgu.io.in.info.vdIdx := outVecCtrl.vuopIdx 154 mgu.io.in.info.narrow := narrow 155 mgu.io.in.info.dstMask := outVecCtrl.isDstMask 156 mgu.io.in.isIndexedVls := false.B 157 158 io.out.bits.res.data := mgu.io.out.vd 159 io.out.bits.ctrl.exceptionVec.get(ExceptionNO.illegalInstr) := mgu.io.out.illegal 160} 161 162class VectorCvtTopIO(vlen: Int, xlen: Int) extends Bundle{ 163 val fire = Input(Bool()) 164 val uopIdx = Input(Bool()) 165 val src = Input(Vec(vlen / xlen, UInt(xlen.W))) 166 val opType = Input(UInt(8.W)) 167 val sew = Input(UInt(2.W)) 168 val rm = Input(UInt(3.W)) 169 val outputWidth1H = Input(UInt(4.W)) 170 val isWiden = Input(Bool()) 171 val isNarrow = Input(Bool()) 172 173 val result = Output(UInt(vlen.W)) 174 val fflags = Output(UInt((vlen/16*5).W)) 175} 176 177 178 179//according to uopindex, 1: high64 0:low64 180class VectorCvtTop(vlen: Int, xlen: Int) extends Module{ 181 val io = IO(new VectorCvtTopIO(vlen, xlen)) 182 183 val (fire, uopIdx, src, opType, sew, rm, outputWidth1H, isWiden, isNarrow) = ( 184 io.fire, io.uopIdx, io.src, io.opType, io.sew, io.rm, io.outputWidth1H, io.isWiden, io.isNarrow 185 ) 186 val fireReg = GatedValidRegNext(fire) 187 188 val in0 = Mux(isWiden, 189 Mux(uopIdx, src(1).tail(32), src(0).tail(32)), 190 src(0) 191 ) 192 193 val in1 = Mux(isWiden, 194 Mux(uopIdx, src(1).head(32), src(0).head(32)), 195 src(1) 196 ) 197 198 val vectorCvt0 = Module(new VectorCvt(xlen)) 199 vectorCvt0.fire := fire 200 vectorCvt0.src := in0 201 vectorCvt0.opType := opType 202 vectorCvt0.sew := sew 203 vectorCvt0.rm := rm 204 205 val vectorCvt1 = Module(new VectorCvt(xlen)) 206 vectorCvt1.fire := fire 207 vectorCvt1.src := in1 208 vectorCvt1.opType := opType 209 vectorCvt1.sew := sew 210 vectorCvt1.rm := rm 211 212 val isNarrowCycle2 = RegEnable(RegEnable(isNarrow, fire), fireReg) 213 val outputWidth1HCycle2 = RegEnable(RegEnable(outputWidth1H, fire), fireReg) 214 215 //cycle2 216 io.result := Mux(isNarrowCycle2, 217 vectorCvt1.io.result.tail(32) ## vectorCvt0.io.result.tail(32), 218 vectorCvt1.io.result ## vectorCvt0.io.result) 219 220 io.fflags := Mux1H(outputWidth1HCycle2, Seq( 221 vectorCvt1.io.fflags ## vectorCvt0.io.fflags, 222 Mux(isNarrowCycle2, vectorCvt1.io.fflags.tail(10) ## vectorCvt0.io.fflags.tail(10), vectorCvt1.io.fflags ## vectorCvt0.io.fflags), 223 Mux(isNarrowCycle2, vectorCvt1.io.fflags(4,0) ## vectorCvt0.io.fflags(4,0), vectorCvt1.io.fflags.tail(10) ## vectorCvt0.io.fflags.tail(10)), 224 vectorCvt1.io.fflags(4,0) ## vectorCvt0.io.fflags(4,0) 225 )) 226} 227 228 229