1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.ZeroExt 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput} 10import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 11import xiangshan.backend.datapath.DataConfig.{IntData, VecData} 12import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 13import xiangshan.backend.datapath.WbConfig._ 14import xiangshan.backend.datapath._ 15import xiangshan.backend.dispatch.CoreDispatchTopDownIO 16import xiangshan.backend.exu.ExuBlock 17import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 18import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, PerfCounterIO} 19import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerImpBase} 20import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO} 21import xiangshan.frontend.{FtqPtr, FtqRead} 22import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 23 24class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 25 with HasXSParameter { 26 27 /* Only update the idx in mem-scheduler here 28 * Idx in other schedulers can be updated the same way if needed 29 * 30 * Also note that we filter out the 'stData issue-queues' when counting 31 */ 32 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 33 ibp.updateIdx(idx) 34 } 35 36 println(params.iqWakeUpParams) 37 38 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 39 schdCfg.bindBackendParam(params) 40 } 41 42 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 43 iqCfg.bindBackendParam(params) 44 } 45 46 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 47 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 48 exuCfg.updateExuIdx(i) 49 exuCfg.bindBackendParam(params) 50 } 51 52 println("[Backend] ExuConfigs:") 53 for (exuCfg <- params.allExuParams) { 54 val fuConfigs = exuCfg.fuConfigs 55 val wbPortConfigs = exuCfg.wbPortConfigs 56 val immType = exuCfg.immType 57 58 println("[Backend] " + 59 s"${exuCfg.name}: " + 60 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 61 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 62 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 63 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " 64 ) 65 require( 66 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 67 fuConfigs.map(_.writeIntRf).reduce(_ || _), 68 "int wb port has no priority" 69 ) 70 require( 71 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 72 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 73 "vec wb port has no priority" 74 ) 75 } 76 77 println(s"[Backend] all fu configs") 78 for (cfg <- FuConfig.allConfigs) { 79 println(s"[Backend] $cfg") 80 } 81 82 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 83 for ((port, seq) <- params.getRdPortParams(IntData())) { 84 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 85 } 86 87 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 88 for ((port, seq) <- params.getWbPortParams(IntData())) { 89 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 90 } 91 92 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 93 for ((port, seq) <- params.getRdPortParams(VecData())) { 94 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 95 } 96 97 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 98 for ((port, seq) <- params.getWbPortParams(VecData())) { 99 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 100 } 101 102 val ctrlBlock = LazyModule(new CtrlBlock(params)) 103 val pcTargetMem = LazyModule(new PcTargetMem(params)) 104 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 105 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 106 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 107 val cancelNetwork = LazyModule(new CancelNetwork(params)) 108 val dataPath = LazyModule(new DataPath(params)) 109 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 110 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 111 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 112 113 lazy val module = new BackendImp(this) 114} 115 116class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 117 with HasXSParameter { 118 implicit private val params = wrapper.params 119 120 val io = IO(new BackendIO()(p, wrapper.params)) 121 122 private val ctrlBlock = wrapper.ctrlBlock.module 123 private val pcTargetMem = wrapper.pcTargetMem.module 124 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 125 private val vfScheduler = wrapper.vfScheduler.get.module 126 private val memScheduler = wrapper.memScheduler.get.module 127 private val cancelNetwork = wrapper.cancelNetwork.module 128 private val dataPath = wrapper.dataPath.module 129 private val intExuBlock = wrapper.intExuBlock.get.module 130 private val vfExuBlock = wrapper.vfExuBlock.get.module 131 private val bypassNetwork = Module(new BypassNetwork) 132 private val wbDataPath = Module(new WbDataPath(params)) 133 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 134 135 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 136 intScheduler.io.toSchedulers.wakeupVec ++ 137 vfScheduler.io.toSchedulers.wakeupVec ++ 138 memScheduler.io.toSchedulers.wakeupVec 139 ).map(x => (x.bits.exuIdx, x)).toMap 140 141 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 142 143 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 144 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 145 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 146 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 147 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 148 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 149 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 150 151 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 152 153 private val vconfig = dataPath.io.vconfigReadPort.data 154 private val og1CancelVec: Vec[Bool] = dataPath.io.og1CancelVec 155 private val og0CancelVecFromDataPath: Vec[Bool] = dataPath.io.og0CancelVec 156 private val og0CancelVecFromCancelNet: Vec[Bool] = cancelNetwork.io.out.og0CancelVec 157 private val og0CancelVecFromFinalIssue: Vec[Bool] = Wire(chiselTypeOf(dataPath.io.og0CancelVec)) 158 private val og0CancelVec: Seq[Bool] = og0CancelVecFromDataPath.zip(og0CancelVecFromCancelNet).zip(og0CancelVecFromFinalIssue).map(x => x._1._1 | x._1._2 | x._2) 159 private val cancelToBusyTable = dataPath.io.cancelToBusyTable 160 161 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 162 ctrlBlock.io.frontend <> io.frontend 163 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 164 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 165 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 166 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 167 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 168 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 169 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 170 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 171 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 172 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 173 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 174 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 175 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 176 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 177 ctrlBlock.perfinfo := DontCare // TODO: Implement backend hpm 178 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 179 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 180 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 181 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 182 183 184 intScheduler.io.fromTop.hartId := io.fromTop.hartId 185 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 186 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 187 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 188 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 189 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 190 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 191 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 192 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 193 intScheduler.io.fromDataPath.og0Cancel := og0CancelVec 194 intScheduler.io.fromDataPath.og1Cancel := og1CancelVec 195 intScheduler.io.ldCancel := io.mem.ldCancel 196 intScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 197 198 memScheduler.io.fromTop.hartId := io.fromTop.hartId 199 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 200 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 201 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 202 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 203 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 204 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 205 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 206 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 207 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 208 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 209 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 210 sink.valid := source.valid 211 sink.bits := source.bits.robIdx 212 } 213 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 214 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 215 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 216 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 217 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 218 memScheduler.io.fromDataPath.og0Cancel := og0CancelVec 219 memScheduler.io.fromDataPath.og1Cancel := og1CancelVec 220 memScheduler.io.ldCancel := io.mem.ldCancel 221 memScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 222 223 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 224 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 225 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 226 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 227 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 228 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 229 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 230 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 231 vfScheduler.io.fromDataPath.og0Cancel := og0CancelVec 232 vfScheduler.io.fromDataPath.og1Cancel := og1CancelVec 233 vfScheduler.io.ldCancel := io.mem.ldCancel 234 vfScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 235 236 cancelNetwork.io.in.int <> intScheduler.io.toDataPath 237 cancelNetwork.io.in.vf <> vfScheduler.io.toDataPath 238 cancelNetwork.io.in.mem <> memScheduler.io.toDataPath 239 cancelNetwork.io.in.og0CancelVec := og0CancelVecFromDataPath.zip(og0CancelVecFromFinalIssue).map(x => x._1 || x._2) 240 cancelNetwork.io.in.og1CancelVec := og1CancelVec 241 intScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.int 242 vfScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.vf 243 memScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.mem 244 245 dataPath.io.hartId := io.fromTop.hartId 246 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 247 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 248 249 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 250 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 251 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 252 253 dataPath.io.ldCancel := io.mem.ldCancel 254 255 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 256 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 257 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 258 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 259 dataPath.io.debugIntRat .foreach(_ := ctrlBlock.io.debug_int_rat.get) 260 dataPath.io.debugFpRat .foreach(_ := ctrlBlock.io.debug_fp_rat.get) 261 dataPath.io.debugVecRat .foreach(_ := ctrlBlock.io.debug_vec_rat.get) 262 dataPath.io.debugVconfigRat.foreach(_ := ctrlBlock.io.debug_vconfig_rat.get) 263 264 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 265 bypassNetwork.io.fromDataPath.vf <> dataPath.io.toFpExu 266 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 267 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 268 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 269 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 270 sink.valid := source.valid 271 sink.bits.pdest := source.bits.uop.pdest 272 sink.bits.data := source.bits.data 273 } 274 275 276 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 277 for (i <- 0 until intExuBlock.io.in.length) { 278 for (j <- 0 until intExuBlock.io.in(i).length) { 279 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 280 NewPipelineConnect( 281 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 282 Mux( 283 bypassNetwork.io.toExus.int(i)(j).fire, 284 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 285 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 286 ) 287 ) 288 } 289 } 290 291 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 292 pcTargetMem.io.fromDataPathFtq := bypassNetwork.io.toExus.int.flatten.filter(_.bits.params.hasPredecode).map(_.bits.ftqIdx.get).toSeq 293 intExuBlock.io.in.flatten.filter(_.bits.params.hasPredecode).map(_.bits.predictInfo.get.target).zipWithIndex.foreach { 294 case (sink, i) => 295 sink := pcTargetMem.io.toExus(i) 296 } 297 298 private val csrio = intExuBlock.io.csrio.get 299 csrio.hartId := io.fromTop.hartId 300 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 301 csrio.fpu.isIllegal := false.B // Todo: remove it 302 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 303 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 304 305 val debugVconfig = dataPath.io.debugVconfig.get.asTypeOf(new VConfig) 306 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 307 val debugVl = debugVconfig.vl 308 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 309 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 310 csrio.vpu.set_vstart.bits := 0.U 311 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 312 //Todo here need change design 313 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 314 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 315 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 316 csrio.exception := ctrlBlock.io.robio.exception 317 csrio.memExceptionVAddr := io.mem.exceptionVAddr 318 csrio.externalInterrupt := io.fromTop.externalInterrupt 319 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 320 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 321 csrio.perf <> io.perf 322 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 323 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 324 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 325 private val fenceio = intExuBlock.io.fenceio.get 326 io.fenceio <> fenceio 327 fenceio.disableSfence := csrio.disableSfence 328 329 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 330 for (i <- 0 until vfExuBlock.io.in.size) { 331 for (j <- 0 until vfExuBlock.io.in(i).size) { 332 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 333 NewPipelineConnect( 334 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 335 Mux( 336 bypassNetwork.io.toExus.vf(i)(j).fire, 337 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 338 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 339 ) 340 ) 341 342 vfExuBlock.io.in(i)(j).bits.vpu.foreach(_.vstart := csrio.vpu.vstart) 343 } 344 } 345 346 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 347 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 348 349 wbDataPath.io.flush := ctrlBlock.io.redirect 350 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 351 wbDataPath.io.fromIntExu <> intExuBlock.io.out 352 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 353 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 354 sink.valid := source.valid 355 source.ready := sink.ready 356 sink.bits.data := source.bits.data 357 sink.bits.pdest := source.bits.uop.pdest 358 sink.bits.robIdx := source.bits.uop.robIdx 359 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 360 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 361 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 362 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 363 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 364 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 365 sink.bits.debug := source.bits.debug 366 sink.bits.debugInfo := source.bits.uop.debugInfo 367 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 368 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 369 } 370 371 // to mem 372 private val memIssueParams = params.memSchdParams.get.issueBlockParams 373 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(_.fuConfigs.contains(FuConfig.LduCfg))) 374 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 375 for (i <- toMem.indices) { 376 for (j <- toMem(i).indices) { 377 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 378 val issueTimeout = 379 if (memExuBlocksHasLDU(i)(j)) 380 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 381 else 382 false.B 383 384 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty) { 385 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 386 memScheduler.io.loadFinalIssueResp(i)(j).bits.dataInvalidSqIdx := DontCare 387 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 388 memScheduler.io.loadFinalIssueResp(i)(j).bits.respType := RSFeedbackType.fuBusy 389 memScheduler.io.loadFinalIssueResp(i)(j).bits.rfWen := toMem(i)(j).bits.rfWen.getOrElse(false.B) 390 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 391 } 392 393 NewPipelineConnect( 394 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 395 Mux( 396 bypassNetwork.io.toExus.mem(i)(j).fire, 397 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 398 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 399 ) 400 ) 401 } 402 } 403 404 io.mem.redirect := ctrlBlock.io.redirect 405 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 406 sink.valid := source.valid 407 source.ready := sink.ready 408 sink.bits.iqIdx := source.bits.iqIdx 409 sink.bits.isFirstIssue := source.bits.isFirstIssue 410 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 411 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 412 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 413 sink.bits.deqPortIdx := source.bits.deqPortIdx.getOrElse(0.U) 414 sink.bits.uop.fuType := source.bits.fuType 415 sink.bits.uop.fuOpType := source.bits.fuOpType 416 sink.bits.uop.imm := source.bits.imm 417 sink.bits.uop.robIdx := source.bits.robIdx 418 sink.bits.uop.pdest := source.bits.pdest 419 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 420 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 421 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 422 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 423 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 424 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 425 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 426 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 427 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 428 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 429 } 430 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 431 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 432 io.mem.tlbCsr := csrio.tlb 433 io.mem.csrCtrl := csrio.customCtrl 434 io.mem.sfence := fenceio.sfence 435 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 436 require(io.mem.loadPcRead.size == params.LduCnt) 437 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 438 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 439 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueUops(i).bits.uop.ftqPtr 440 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueUops(i).bits.uop.ftqOffset 441 require(toMem.head(i).bits.ftqIdx.isDefined && toMem.head(i).bits.ftqOffset.isDefined) 442 } 443 444 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 445 storePcRead := ctrlBlock.io.memStPcRead(i).data 446 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueUops(i + params.LduCnt).bits.uop.ftqPtr 447 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueUops(i + params.LduCnt).bits.uop.ftqOffset 448 require(toMem(1)(i).bits.ftqIdx.isDefined && toMem(1)(i).bits.ftqOffset.isDefined) 449 } 450 451 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 452 453 // mem io 454 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 455 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 456 457 private val intFinalIssueBlock = intExuBlock.io.in.flatten.map(_ => false.B) 458 private val vfFinalIssueBlock = vfExuBlock.io.in.flatten.map(_ => false.B) 459 private val memFinalIssueBlock = io.mem.issueUops zip memExuBlocksHasLDU.flatten map { 460 case (out, isLdu) => 461 if (isLdu) RegNext(out.valid && !out.ready, false.B) 462 else false.B 463 } 464 og0CancelVecFromFinalIssue := (intFinalIssueBlock ++ vfFinalIssueBlock ++ memFinalIssueBlock).toSeq 465 466 io.frontendSfence := fenceio.sfence 467 io.frontendTlbCsr := csrio.tlb 468 io.frontendCsrCtrl := csrio.customCtrl 469 470 io.tlb <> csrio.tlb 471 472 io.csrCustomCtrl := csrio.customCtrl 473 474 io.toTop.cpuHalted := false.B // TODO: implement cpu halt 475 476 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 477 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 478 479 io.debugRolling := ctrlBlock.io.debugRolling 480 481 dontTouch(memScheduler.io) 482 dontTouch(dataPath.io.toMemExu) 483 dontTouch(wbDataPath.io.fromMemExu) 484} 485 486class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 487 // params alias 488 private val LoadQueueSize = VirtualLoadQueueSize 489 // In/Out // Todo: split it into one-direction bundle 490 val lsqEnqIO = Flipped(new LsqEnqIO) 491 val robLsqIO = new RobLsqIO 492 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 493 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 494 val ldCancel = Vec(params.LduCnt, Flipped(new LoadCancelIO)) 495 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 496 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 497 498 // Input 499 val writeBack = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(Flipped(DecoupledIO(new MemExuOutput()))) ++ Seq.fill(params.VlduCnt)(Flipped(DecoupledIO(new MemExuOutput(true))))) 500 501 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 502 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 503 val memoryViolation = Flipped(ValidIO(new Redirect)) 504 val exceptionVAddr = Input(UInt(VAddrBits.W)) 505 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 506 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 507 508 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 509 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 510 511 val lqCanAccept = Input(Bool()) 512 val sqCanAccept = Input(Bool()) 513 514 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 515 val stIssuePtr = Input(new SqPtr()) 516 517 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 518 519 val debugLS = Flipped(Output(new DebugLSIO)) 520 521 val lsTopdownInfo = Vec(params.LduCnt, Flipped(Output(new LsTopdownInfo))) 522 // Output 523 val redirect = ValidIO(new Redirect) // rob flush MemBlock 524 val issueUops = MixedVec(Seq.fill(params.LduCnt + params.StaCnt + params.StdCnt)(DecoupledIO(new MemExuInput())) ++ Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 525 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 526 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 527 528 val tlbCsr = Output(new TlbCsrBundle) 529 val csrCtrl = Output(new CustomCSRCtrlIO) 530 val sfence = Output(new SfenceBundle) 531 val isStoreException = Output(Bool()) 532} 533 534class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 535 val fromTop = new Bundle { 536 val hartId = Input(UInt(8.W)) 537 val externalInterrupt = new ExternalInterruptIO 538 } 539 540 val toTop = new Bundle { 541 val cpuHalted = Output(Bool()) 542 } 543 544 val fenceio = new FenceIO 545 // Todo: merge these bundles into BackendFrontendIO 546 val frontend = Flipped(new FrontendToCtrlIO) 547 val frontendSfence = Output(new SfenceBundle) 548 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 549 val frontendTlbCsr = Output(new TlbCsrBundle) 550 // distributed csr write 551 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 552 553 val mem = new BackendMemIO 554 555 val perf = Input(new PerfCounterIO) 556 557 val tlb = Output(new TlbCsrBundle) 558 559 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 560 561 val debugTopDown = new Bundle { 562 val fromRob = new RobCoreTopDownIO 563 val fromCore = new CoreDispatchTopDownIO 564 } 565 val debugRolling = new RobDebugRollingIO 566} 567