1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 14import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode 15 16class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 17{ 18 val csrIn = io.csrio.get 19 val csrOut = io.csrio.get 20 val csrToDecode = io.csrToDecode.get 21 22 val setFsDirty = csrIn.fpu.dirty_fs 23 val setFflags = csrIn.fpu.fflags 24 25 val setVsDirty = csrIn.vpu.dirty_vs 26 val setVstart = csrIn.vpu.set_vstart 27 val setVtype = csrIn.vpu.set_vtype 28 val setVxsat = csrIn.vpu.set_vxsat 29 val vlFromPreg = csrIn.vpu.vl 30 31 val flushPipe = Wire(Bool()) 32 val flush = io.flush.valid 33 34 val (valid, src1, src2, func) = ( 35 io.in.valid, 36 io.in.bits.data.src(0), 37 io.in.bits.data.imm, 38 io.in.bits.ctrl.fuOpType 39 ) 40 41 // split imm from IMM_Z 42 val addr = src2(11, 0) 43 val csri = ZeroExt(src2(16, 12), XLEN) 44 45 import CSRConst._ 46 47 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 48 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 49 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 50 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 51 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 52 private val isWfi = CSROpType.isWfi(func) 53 private val isCSRAcc = CSROpType.isCsrAccess(func) 54 55 val csrMod = Module(new NewCSR) 56 57 private val privState = csrMod.io.status.privState 58 // The real reg value in CSR, with no read mask 59 private val regOut = csrMod.io.out.bits.regOut 60 private val src = Mux(CSROpType.needImm(func), csri, src1) 61 private val wdata = LookupTree(func, Seq( 62 CSROpType.wrt -> src1, 63 CSROpType.set -> (regOut | src1), 64 CSROpType.clr -> (regOut & (~src1).asUInt), 65 CSROpType.wrti -> csri, 66 CSROpType.seti -> (regOut | csri), 67 CSROpType.clri -> (regOut & (~csri).asUInt), 68 )) 69 70 private val csrAccess = valid && CSROpType.isCsrAccess(func) 71 private val csrWen = valid && CSROpType.notReadOnly(func) 72 73 csrMod.io.in match { 74 case in => 75 in.valid := valid 76 in.bits.wen := csrWen 77 in.bits.ren := csrAccess 78 in.bits.op := CSROpType.getCSROp(func) 79 in.bits.addr := addr 80 in.bits.src := src 81 in.bits.wdata := wdata 82 in.bits.mret := isMret 83 in.bits.sret := isSret 84 in.bits.dret := isDret 85 } 86 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 87 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 88 89 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 90 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 91 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 92 // Todo: shrink the width of trap vector. 93 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 94 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 95 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 96 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 97 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 98 csrMod.io.fromRob.trap.bits.triggerCf := csrIn.exception.bits.trigger 99 csrMod.io.fromRob.trap.bits.isHls := csrIn.exception.bits.isHls 100 101 csrMod.io.fromRob.commit.fflags := setFflags 102 csrMod.io.fromRob.commit.fsDirty := setFsDirty 103 csrMod.io.fromRob.commit.vxsat.valid := setVxsat.valid 104 csrMod.io.fromRob.commit.vxsat.bits := setVxsat.bits 105 csrMod.io.fromRob.commit.vsDirty := setVsDirty 106 csrMod.io.fromRob.commit.vstart := setVstart 107 csrMod.io.fromRob.commit.vl := vlFromPreg 108 // Todo: correct vtype 109 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid 110 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1) 111 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 112 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 113 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 114 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 115 116 csrMod.io.fromRob.commit.instNum.valid := true.B // Todo: valid control signal 117 csrMod.io.fromRob.commit.instNum.bits := csrIn.perf.retiredInstr 118 119 csrMod.io.perf := csrIn.perf 120 121 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 122 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 123 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 124 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 125 csrMod.platformIRP.STIP := false.B 126 csrMod.platformIRP.VSEIP := false.B // Todo 127 csrMod.platformIRP.VSTIP := false.B // Todo 128 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 129 130 csrMod.io.fromTop.hartId := io.csrin.get.hartId 131 csrMod.io.fromTop.clintTime := io.csrin.get.clintTime 132 private val csrModOutValid = csrMod.io.out.valid 133 private val csrModOut = csrMod.io.out.bits 134 135 private val imsic = Module(new IMSIC(NumVSIRFiles = 5, NumHart = 1, XLEN = 64, NumIRSrc = 256)) 136 imsic.i.hartId := io.csrin.get.hartId 137 imsic.i.msiInfo := io.csrin.get.msiInfo 138 imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid 139 imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr 140 imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt 141 imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt 142 imsic.i.csr.vgein := csrMod.toAIA.vgein 143 imsic.i.csr.mClaim := csrMod.toAIA.mClaim 144 imsic.i.csr.sClaim := csrMod.toAIA.sClaim 145 imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim 146 imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid 147 imsic.i.csr.wdata.bits.op := csrMod.toAIA.wdata.bits.op 148 imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data 149 150 csrMod.fromAIA.rdata.valid := imsic.o.csr.rdata.valid 151 csrMod.fromAIA.rdata.bits.data := imsic.o.csr.rdata.bits.rdata 152 csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal 153 csrMod.fromAIA.meip := imsic.o.meip 154 csrMod.fromAIA.seip := imsic.o.seip 155 csrMod.fromAIA.vseip := imsic.o.vseip 156 csrMod.fromAIA.mtopei := imsic.o.mtopei 157 csrMod.fromAIA.stopei := imsic.o.stopei 158 csrMod.fromAIA.vstopei := imsic.o.vstopei 159 160 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 161 import ExceptionNO._ 162 exceptionVec(EX_BP ) := isEbreak 163 exceptionVec(EX_MCALL ) := isEcall && privState.isModeM 164 exceptionVec(EX_HSCALL) := isEcall && privState.isModeHS 165 exceptionVec(EX_VSCALL) := isEcall && privState.isModeVS 166 exceptionVec(EX_UCALL ) := isEcall && privState.isModeHUorVU 167 exceptionVec(EX_II ) := csrMod.io.out.bits.EX_II 168 exceptionVec(EX_VI ) := csrMod.io.out.bits.EX_VI 169 170 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 171 172 // ctrl block will use theses later for flush // Todo: optimize isXRetFlag's DelayN 173 val isXRetFlag = RegInit(false.B) 174 isXRetFlag := Mux1H(Seq( 175 DelayN(flush, 5) -> false.B, 176 isXRet -> true.B, 177 )) 178 179 flushPipe := csrMod.io.out.bits.flushPipe 180 181 // tlb 182 val tlb = Wire(new TlbCsrBundle) 183 tlb.satp.changed := csrMod.io.tlb.satpASIDChanged 184 tlb.satp.mode := csrMod.io.tlb.satp.MODE.asUInt 185 tlb.satp.asid := csrMod.io.tlb.satp.ASID.asUInt 186 tlb.satp.ppn := csrMod.io.tlb.satp.PPN.asUInt 187 tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged 188 tlb.vsatp.mode := csrMod.io.tlb.vsatp.MODE.asUInt 189 tlb.vsatp.asid := csrMod.io.tlb.vsatp.ASID.asUInt 190 tlb.vsatp.ppn := csrMod.io.tlb.vsatp.PPN.asUInt 191 tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged 192 tlb.hgatp.mode := csrMod.io.tlb.hgatp.MODE.asUInt 193 tlb.hgatp.asid := csrMod.io.tlb.hgatp.VMID.asUInt 194 tlb.hgatp.ppn := csrMod.io.tlb.hgatp.PPN.asUInt 195 196 // expose several csr bits for tlb 197 tlb.priv.mxr := csrMod.io.tlb.mxr 198 tlb.priv.sum := csrMod.io.tlb.sum 199 tlb.priv.vmxr := csrMod.io.tlb.vmxr 200 tlb.priv.vsum := csrMod.io.tlb.vsum 201 tlb.priv.spvp := csrMod.io.tlb.spvp 202 tlb.priv.virt := csrMod.io.tlb.dvirt 203 tlb.priv.imode := csrMod.io.tlb.imode 204 tlb.priv.dmode := csrMod.io.tlb.dmode 205 206 io.in.ready := true.B // Todo: Async read imsic may block CSR 207 io.out.valid := csrModOutValid 208 io.out.bits.ctrl.exceptionVec.get := exceptionVec 209 io.out.bits.ctrl.flushPipe.get := flushPipe 210 io.out.bits.res.data := csrMod.io.out.bits.rData 211 212 io.out.bits.res.redirect.get.valid := isXRet 213 val redirect = io.out.bits.res.redirect.get.bits 214 redirect := 0.U.asTypeOf(redirect) 215 redirect.level := RedirectLevel.flushAfter 216 redirect.robIdx := io.in.bits.ctrl.robIdx 217 redirect.ftqIdx := io.in.bits.ctrl.ftqIdx.get 218 redirect.ftqOffset := io.in.bits.ctrl.ftqOffset.get 219 redirect.cfiUpdate.predTaken := true.B 220 redirect.cfiUpdate.taken := true.B 221 redirect.cfiUpdate.target := csrMod.io.out.bits.targetPc 222 // Only mispred will send redirect to frontend 223 redirect.cfiUpdate.isMisPred := true.B 224 225 connect0LatencyCtrlSingal 226 227 // Todo: summerize all difftest skip condition 228 csrOut.isPerfCnt := csrMod.io.out.bits.isPerfCnt && csrModOutValid && func =/= CSROpType.jmp 229 csrOut.fpu.frm := csrMod.io.status.fpState.frm.asUInt 230 csrOut.vpu.vstart := csrMod.io.status.vecState.vstart.asUInt 231 csrOut.vpu.vxrm := csrMod.io.status.vecState.vxrm.asUInt 232 233 csrOut.isXRet := isXRetFlag 234 235 csrOut.trapTarget := csrMod.io.out.bits.targetPc 236 csrOut.interrupt := csrMod.io.status.interrupt 237 csrOut.wfi_event := csrMod.io.status.wfiEvent 238 239 csrOut.tlb := tlb 240 241 csrOut.debugMode := csrMod.io.status.debugMode 242 243 csrOut.customCtrl match { 244 case custom => 245 custom.l1I_pf_enable := csrMod.io.status.custom.l1I_pf_enable 246 custom.l2_pf_enable := csrMod.io.status.custom.l2_pf_enable 247 custom.l1D_pf_enable := csrMod.io.status.custom.l1D_pf_enable 248 custom.l1D_pf_train_on_hit := csrMod.io.status.custom.l1D_pf_train_on_hit 249 custom.l1D_pf_enable_agt := csrMod.io.status.custom.l1D_pf_enable_agt 250 custom.l1D_pf_enable_pht := csrMod.io.status.custom.l1D_pf_enable_pht 251 custom.l1D_pf_active_threshold := csrMod.io.status.custom.l1D_pf_active_threshold 252 custom.l1D_pf_active_stride := csrMod.io.status.custom.l1D_pf_active_stride 253 custom.l1D_pf_enable_stride := csrMod.io.status.custom.l1D_pf_enable_stride 254 custom.l2_pf_store_only := csrMod.io.status.custom.l2_pf_store_only 255 // ICache 256 custom.icache_parity_enable := csrMod.io.status.custom.icache_parity_enable 257 // Load violation predictor 258 custom.lvpred_disable := csrMod.io.status.custom.lvpred_disable 259 custom.no_spec_load := csrMod.io.status.custom.no_spec_load 260 custom.storeset_wait_store := csrMod.io.status.custom.storeset_wait_store 261 custom.storeset_no_fast_wakeup := csrMod.io.status.custom.storeset_no_fast_wakeup 262 custom.lvpred_timeout := csrMod.io.status.custom.lvpred_timeout 263 // Branch predictor 264 custom.bp_ctrl := csrMod.io.status.custom.bp_ctrl 265 // Memory Block 266 custom.sbuffer_threshold := csrMod.io.status.custom.sbuffer_threshold 267 custom.ldld_vio_check_enable := csrMod.io.status.custom.ldld_vio_check_enable 268 custom.soft_prefetch_enable := csrMod.io.status.custom.soft_prefetch_enable 269 custom.cache_error_enable := csrMod.io.status.custom.cache_error_enable 270 custom.uncache_write_outstanding_enable := csrMod.io.status.custom.uncache_write_outstanding_enable 271 // Rename 272 custom.fusion_enable := csrMod.io.status.custom.fusion_enable 273 custom.wfi_enable := csrMod.io.status.custom.wfi_enable 274 // distribute csr write signal 275 // write to frontend and memory 276 custom.distribute_csr.w.valid := csrWen 277 custom.distribute_csr.w.bits.addr := addr 278 custom.distribute_csr.w.bits.data := wdata 279 // rename single step 280 custom.singlestep := csrMod.io.status.singleStepFlag 281 // trigger 282 custom.frontend_trigger := csrMod.io.status.frontendTrigger 283 custom.mem_trigger := csrMod.io.status.memTrigger 284 // virtual mode 285 custom.virtMode := csrMod.io.status.privState.V.asBool 286 } 287 288 csrToDecode := csrMod.io.toDecode 289} 290 291class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{ 292 val hartId = Input(UInt(8.W)) 293 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 294 val clintTime = Input(ValidIO(UInt(64.W))) 295} 296 297class CSRToDecode(implicit p: Parameters) extends XSBundle { 298 val illegalInst = new Bundle { 299 /** 300 * illegal sfence.vma, sinval.vma 301 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 302 */ 303 val sfenceVMA = Bool() 304 305 /** 306 * illegal sfence.w.inval sfence.inval.ir 307 * raise EX_II when isModeHU 308 */ 309 val sfencePart = Bool() 310 311 /** 312 * illegal hfence.gvma, hinval.gvma 313 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 314 * the condition is the same as sfenceVMA 315 */ 316 val hfenceGVMA = Bool() 317 318 /** 319 * illegal hfence.vvma, hinval.vvma 320 * raise EX_II when isModeHU 321 */ 322 val hfenceVVMA = Bool() 323 324 /** 325 * illegal hlv, hlvx, and hsv 326 * raise EX_II when isModeHU && hstatus.HU=0 327 */ 328 val hlsv = Bool() 329 330 /** 331 * decode all fp inst or all vecfp inst 332 * raise EX_II when FS=Off 333 */ 334 val fsIsOff = Bool() 335 336 /** 337 * decode all vec inst 338 * raise EX_II when VS=Off 339 */ 340 val vsIsOff = Bool() 341 342 /** 343 * illegal wfi 344 * raise EX_II when isModeHU || !isModeM && mstatus.TW=1 345 */ 346 val wfi = Bool() 347 } 348 val virtualInst = new Bundle { 349 /** 350 * illegal sfence.vma, svinval.vma 351 * raise EX_VI when isModeVS && hstatus.VTVM=1 || isModeVU 352 */ 353 val sfenceVMA = Bool() 354 355 /** 356 * illegal sfence.w.inval sfence.inval.ir 357 * raise EX_VI when isModeVU 358 */ 359 val sfencePart = Bool() 360 361 /** 362 * illegal hfence.gvma, hinval.gvma, hfence.vvma, hinval.vvma 363 * raise EX_VI when isModeVS || isModeVU 364 */ 365 val hfence = Bool() 366 367 /** 368 * illegal hlv, hlvx, and hsv 369 * raise EX_VI when isModeVS || isModeVU 370 */ 371 val hlsv = Bool() 372 373 /** 374 * illegal wfi 375 * raise EX_VI when isModeVU && mstatus.TW=0 || isModeVS && mstatus.TW=0 && hstatus.VTW=1 376 */ 377 val wfi = Bool() 378 } 379}