xref: /XiangShan/src/test/scala/top/SimTop.scala (revision d57bda64dd69dbc246bd52257ef7392f220149aa) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chipsalliance.rocketchip.config.{Config, Parameters}
20import chisel3.stage.ChiselGeneratorAnnotation
21import chisel3._
22import device.AXI4RAMWrapper
23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
24import utils.GTimer
25import xiangshan.{DebugOptions, DebugOptionsKey}
26import difftest._
27
28class SimTop(implicit p: Parameters) extends Module {
29  val debugOpts = p(DebugOptionsKey)
30  val useDRAMSim = debugOpts.UseDRAMSim
31
32  val l_soc = LazyModule(new XSTopWithoutDMA())
33  val soc = Module(l_soc.module)
34
35  val l_simMMIO = LazyModule(new SimMMIO(l_soc.peripheralNode.in.head._2))
36  val simMMIO = Module(l_simMMIO.module)
37  l_simMMIO.connectToSoC(l_soc)
38
39  if(!useDRAMSim){
40    val l_simAXIMem = LazyModule(new AXI4RAMWrapper(
41      l_soc.memAXI4SlaveNode, 8L * 1024 * 1024 * 1024, useBlackBox = true
42    ))
43    val simAXIMem = Module(l_simAXIMem.module)
44    l_simAXIMem.connectToSoC(l_soc)
45  }
46
47  soc.io.clock := clock.asBool()
48  soc.io.reset := reset.asBool()
49  soc.io.extIntrs := simMMIO.io.interrupt.intrVec
50
51  val io = IO(new Bundle(){
52    val logCtrl = new LogCtrlIO
53    val perfInfo = new PerfInfoIO
54    val uart = new UARTIO
55    val memAXI = if(useDRAMSim) l_soc.memory.cloneType else null
56  })
57
58  simMMIO.io.uart <> io.uart
59
60  if(useDRAMSim){
61    io.memAXI <> l_soc.memory
62  }
63
64  if (debugOpts.EnableDebug || debugOpts.EnablePerfDebug) {
65    val timer = GTimer()
66    val logEnable = (timer >= io.logCtrl.log_begin) && (timer < io.logCtrl.log_end)
67    ExcitingUtils.addSource(logEnable, "DISPLAY_LOG_ENABLE")
68    ExcitingUtils.addSource(timer, "logTimestamp")
69  }
70
71  if (debugOpts.EnablePerfDebug) {
72    val clean = io.perfInfo.clean
73    val dump = io.perfInfo.dump
74    ExcitingUtils.addSource(clean, "XSPERF_CLEAN")
75    ExcitingUtils.addSource(dump, "XSPERF_DUMP")
76  }
77
78  // Check and dispaly all source and sink connections
79  ExcitingUtils.fixConnections()
80  ExcitingUtils.checkAndDisplay()
81}
82
83object SimTop extends App {
84
85  override def main(args: Array[String]): Unit = {
86    val (config, firrtlOpts) = ArgParser.parse(args, fpga = false)
87    // generate verilog
88    XiangShanStage.execute(
89      firrtlOpts,
90      Seq(
91        ChiselGeneratorAnnotation(() => new SimTop()(config))
92      )
93    )
94  }
95}
96