1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.VSew 9import xiangshan.backend.fu.vector.utils.VecDataSplitModule 10import xiangshan.backend.fu.vector.{Mgu, Utils, VecPipedFuncUnit, VecSrcTypeModule} 11import xiangshan.SrcType 12import yunsuan.encoding.Opcode.VimacOpcode 13import yunsuan.encoding.{VdType, Vs1IntType, Vs2IntType} 14import yunsuan.{OpType, VpermType} 15import yunsuan.vector.perm.Permutation 16 17class VPermSrcTypeModule extends VecSrcTypeModule { 18 private val srcVdType = Wire(new Bundle{ 19 val srcType2 = UInt(4.W) 20 val srcType1 = UInt(4.W) 21 val vdType = UInt(4.W) 22 }) 23 srcVdType := VpermType.getSrcVdType(fuOpType, vsew) 24 25 io.out.vs2Type := srcVdType.srcType2 26 io.out.vs1Type := srcVdType.srcType1 27 io.out.vdType := srcVdType.vdType 28} 29 30class VPPU(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) { 31 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VpermType.dummy, "VpermType OpType not supported") 32 33 // params alias 34 private val dataWidth = cfg.dataBits 35 private val dataWidthOfDataModule = 64 36 private val numVecModule = dataWidth / dataWidthOfDataModule 37 private val vppuNeedClearMask = (VpermType.vcompress === io.in.bits.ctrl.fuOpType) && (vuopIdx(log2Up(MaxUopSize)-1,1) === 0.U) 38 private val mask = Mux(vppuNeedClearMask, 0.U, srcMask) 39 40 // io alias 41 private val opcode = VpermType.getOpcode(fuOpType) 42 43 // modules 44 private val typeMod = Module(new VIMacSrcTypeModule) 45 private val vperms = Module(new Permutation) 46 47 /** 48 * [[typeMod]]'s in connection 49 */ 50 typeMod.io.in.fuOpType := fuOpType 51 typeMod.io.in.vsew := vsew 52 typeMod.io.in.isReverse := isReverse 53 typeMod.io.in.isExt := isExt 54 typeMod.io.in.isDstMask := vecCtrl.isDstMask 55 typeMod.io.in.isMove := isMove 56 57 /** 58 * [[vperms]]'s in connection 59 */ 60 vperms.io match { 61 case subIO => 62 subIO.in.valid := io.in.valid 63 subIO.in.bits.opcode.op := opcode 64 subIO.in.bits.info.vm := vm 65 subIO.in.bits.info.ma := vma 66 subIO.in.bits.info.ta := vta 67 subIO.in.bits.info.vlmul := vlmul 68 subIO.in.bits.info.vl := srcVConfig.vl 69 subIO.in.bits.info.vstart := vstart 70 subIO.in.bits.info.uopIdx := vuopIdx 71 subIO.in.bits.info.vxrm := vxrm 72 subIO.in.bits.srcType(0) := typeMod.io.out.vs2Type 73 subIO.in.bits.srcType(1) := typeMod.io.out.vs1Type 74 subIO.in.bits.vdType := typeMod.io.out.vdType 75 subIO.in.bits.vs1 := Mux(vecCtrl.permImmTruncate, vs1(4,0), vs1) 76 subIO.in.bits.vs2 := vs2 77 subIO.in.bits.old_vd := oldVd 78 subIO.in.bits.mask := mask 79 } 80 81 io.out.bits.res.data := vperms.io.out.vd 82 io.out.bits.res.vxsat.foreach(_ := vperms.io.out.vxsat) 83} 84