1package xiangshan.backend.exu 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan.backend.fu.{CSRFileIO, FenceIO} 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.issue.SchdBlockParams 10import xiangshan.{HasXSParameter, Redirect, XSBundle} 11 12class ExuBlock(params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 13 val exus: Seq[ExeUnit] = params.issueBlockParams.flatMap(_.exuBlockParams.map(x => LazyModule(x.genExuModule))) 14 15 lazy val module = new ExuBlockImp(this)(p, params) 16} 17 18class ExuBlockImp( 19 override val wrapper: ExuBlock 20)(implicit 21 p: Parameters, 22 params: SchdBlockParams 23) extends LazyModuleImp(wrapper) { 24 val io = IO(new ExuBlockIO) 25 26 private val exus = wrapper.exus.map(_.module) 27 28 private val ins: IndexedSeq[DecoupledIO[ExuInput]] = io.in.flatten 29 private val outs: IndexedSeq[DecoupledIO[ExuOutput]] = io.out.flatten 30 31 (ins zip exus zip outs).foreach { case ((input, exu), output) => 32 exu.io.flush <> io.flush 33 exu.io.csrio.foreach(exuio => io.csrio.get <> exuio) 34 exu.io.fenceio.foreach(exuio => io.fenceio.get <> exuio) 35 exu.io.frm.foreach(exuio => io.frm.get <> exuio) 36 exu.io.in <> input 37 output <> exu.io.out 38 } 39} 40 41class ExuBlockIO(implicit p: Parameters, params: SchdBlockParams) extends XSBundle { 42 val flush = Flipped(ValidIO(new Redirect)) 43 // in(i)(j): issueblock(i), exu(j) 44 val in: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = Flipped(params.genExuInputBundle) 45 // out(i)(j): issueblock(i), exu(j). 46 val out: MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = params.genExuOutputDecoupledBundle 47 48 val csrio = if (params.hasCSR) Some(new CSRFileIO) else None 49 val fenceio = if (params.hasFence) Some(new FenceIO) else None 50 val frm = if (params.needSrcFrm) Some(Input(UInt(3.W))) else None 51}