1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility._ 23import utils._ 24import xiangshan._ 25import xiangshan.backend.decode.{FusionDecodeInfo, Imm_I, Imm_LUI_LOAD, Imm_U} 26import xiangshan.backend.fu.FuType 27import xiangshan.backend.rename.freelist._ 28import xiangshan.backend.rob.RobPtr 29import xiangshan.backend.rename.freelist._ 30import xiangshan.mem.mdp._ 31import xiangshan.backend.Bundles.{DecodedInst, DynInst} 32 33class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents { 34 private val numRegSrc = backendParams.numRegSrc 35 private val vecOldVdIdx = 2 36 37 println(s"[Rename] numRegSrc: $numRegSrc") 38 39 val io = IO(new Bundle() { 40 val redirect = Flipped(ValidIO(new Redirect)) 41 val robCommits = Input(new RobCommitIO) 42 // from decode 43 val in = Vec(RenameWidth, Flipped(DecoupledIO(new DecodedInst))) 44 val fusionInfo = Vec(DecodeWidth - 1, Flipped(new FusionDecodeInfo)) 45 // ssit read result 46 val ssit = Flipped(Vec(RenameWidth, Output(new SSITEntry))) 47 // waittable read result 48 val waittable = Flipped(Vec(RenameWidth, Output(Bool()))) 49 // to rename table 50 val intReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 51 val fpReadPorts = Vec(RenameWidth, Vec(4, Input(UInt(PhyRegIdxWidth.W)))) 52 val vecReadPorts = Vec(RenameWidth, Vec(5, Input(UInt(PhyRegIdxWidth.W)))) 53 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 54 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 55 val vecRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 56 // to dispatch1 57 val out = Vec(RenameWidth, DecoupledIO(new DynInst)) 58 // debug arch ports 59 val debug_int_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 60 val debug_vconfig_rat = Input(UInt(PhyRegIdxWidth.W)) 61 val debug_fp_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 62 val debug_vec_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 63 }) 64 65 // create free list and rat 66 val intFreeList = Module(new MEFreeList(NRPhyRegs)) 67 val intRefCounter = Module(new RefCounter(NRPhyRegs)) 68 val fpFreeList = Module(new StdFreeList(NRPhyRegs - FpLogicRegs - VecLogicRegs)) 69 70 intRefCounter.io.commit <> io.robCommits 71 intRefCounter.io.redirect := io.redirect.valid 72 intRefCounter.io.debug_int_rat <> io.debug_int_rat 73 intFreeList.io.commit <> io.robCommits 74 intFreeList.io.debug_rat <> io.debug_int_rat 75 fpFreeList.io.commit <> io.robCommits 76 fpFreeList.io.debug_rat <> io.debug_fp_rat 77 78 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 79 // fp and vec share `fpFreeList` 80 def needDestReg[T <: DecodedInst](reg_t: RegType, x: T): Bool = reg_t match { 81 case Reg_I => x.rfWen && x.ldest =/= 0.U 82 case Reg_F => x.fpWen 83 case Reg_V => x.vecWen 84 } 85 def needDestRegCommit[T <: RobCommitInfo](reg_t: RegType, x: T): Bool = { 86 reg_t match { 87 case Reg_I => x.rfWen 88 case Reg_F => x.fpWen 89 case Reg_V => x.vecWen 90 } 91 } 92 def needDestRegWalk[T <: RobCommitInfo](reg_t: RegType, x: T): Bool = { 93 reg_t match { 94 case Reg_I => x.rfWen && x.ldest =/= 0.U 95 case Reg_F => x.fpWen 96 case Reg_V => x.vecWen 97 } 98 } 99 100 // connect [redirect + walk] ports for __float point__ & __integer__ free list 101 Seq(fpFreeList, intFreeList).foreach { case fl => 102 fl.io.redirect := io.redirect.valid 103 fl.io.walk := io.robCommits.isWalk 104 } 105 // only when both fp and int free list and dispatch1 has enough space can we do allocation 106 // when isWalk, freelist can definitely allocate 107 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 108 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 109 110 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ not walk 111 val canOut = io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk 112 113 114 // speculatively assign the instruction with an robIdx 115 val validCount = PopCount(io.in.map(in => in.valid && in.bits.lastUop)) // number of instructions waiting to enter rob (from decode) 116 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 117 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 118 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 119 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 120 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 121 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 122 robIdxHead := robIdxHeadNext 123 124 /** 125 * Rename: allocate free physical register and update rename table 126 */ 127 val uops = Wire(Vec(RenameWidth, new DynInst)) 128 uops.foreach( uop => { 129 uop.srcState := DontCare 130 uop.robIdx := DontCare 131 uop.debugInfo := DontCare 132 uop.lqIdx := DontCare 133 uop.sqIdx := DontCare 134 uop.waitForRobIdx := DontCare 135 uop.singleStep := DontCare 136 }) 137 138 require(RenameWidth >= CommitWidth) 139 val needVecDest = Wire(Vec(RenameWidth, Bool())) 140 val needFpDest = Wire(Vec(RenameWidth, Bool())) 141 val needIntDest = Wire(Vec(RenameWidth, Bool())) 142 val hasValid = Cat(io.in.map(_.valid)).orR 143 144 val isMove = io.in.map(_.bits.isMove) 145 146 val walkNeedIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 147 val walkNeedFpDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 148 val walkNeedVecDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 149 val walkIsMove = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 150 151 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 152 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 153 val vecSpecWen = Wire(Vec(RenameWidth, Bool())) 154 155 val walkIntSpecWen = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 156 157 val walkPdest = Wire(Vec(RenameWidth, UInt(PhyRegIdxWidth.W))) 158 159 // uop calculation 160 for (i <- 0 until RenameWidth) { 161 for ((name, data) <- uops(i).elements) { 162 if (io.in(i).bits.elements.contains(name)) { 163 data := io.in(i).bits.elements(name) 164 } 165 } 166 167 // update cf according to ssit result 168 uops(i).storeSetHit := io.ssit(i).valid 169 uops(i).loadWaitStrict := io.ssit(i).strict && io.ssit(i).valid 170 uops(i).ssid := io.ssit(i).ssid 171 172 // update cf according to waittable result 173 uops(i).loadWaitBit := io.waittable(i) 174 175 uops(i).replayInst := false.B // set by IQ or MemQ 176 // alloc a new phy reg, fp and vec share the `fpFreeList` 177 needVecDest (i) := io.in(i).valid && needDestReg(Reg_V, io.in(i).bits) 178 needFpDest (i) := io.in(i).valid && needDestReg(Reg_F, io.in(i).bits) 179 needIntDest (i) := io.in(i).valid && needDestReg(Reg_I, io.in(i).bits) 180 if (i < CommitWidth) { 181 walkNeedIntDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(Reg_I, io.robCommits.info(i)) 182 walkNeedFpDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(Reg_F, io.robCommits.info(i)) 183 walkNeedVecDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(Reg_V, io.robCommits.info(i)) 184 walkIsMove(i) := io.robCommits.info(i).isMove 185 } 186 fpFreeList.io.allocateReq(i) := Mux(io.robCommits.isWalk, walkNeedFpDest(i) || walkNeedVecDest(i), needFpDest(i) || needVecDest(i)) 187 intFreeList.io.allocateReq(i) := Mux(io.robCommits.isWalk, walkNeedIntDest(i) && !walkIsMove(i), needIntDest(i) && !isMove(i)) 188 189 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 190 io.in(i).ready := !hasValid || canOut 191 192 uops(i).robIdx := robIdxHead + PopCount(io.in.take(i).map(in => in.valid && in.bits.lastUop)) 193 194 uops(i).psrc(0) := Mux1H(uops(i).srcType(0), Seq(io.intReadPorts(i)(0), io.fpReadPorts(i)(0), io.vecReadPorts(i)(0))) 195 uops(i).psrc(1) := Mux1H(uops(i).srcType(1), Seq(io.intReadPorts(i)(1), io.fpReadPorts(i)(1), io.vecReadPorts(i)(1))) 196 uops(i).psrc(2) := Mux1H(uops(i).srcType(2)(2, 1), Seq(io.fpReadPorts(i)(2), io.vecReadPorts(i)(2))) 197 uops(i).psrc(3) := io.vecReadPorts(i)(3) 198 uops(i).psrc(4) := io.vecReadPorts(i)(4) // Todo: vl read port 199 200 // int psrc2 should be bypassed from next instruction if it is fused 201 if (i < RenameWidth - 1) { 202 when (io.fusionInfo(i).rs2FromRs2 || io.fusionInfo(i).rs2FromRs1) { 203 uops(i).psrc(1) := Mux(io.fusionInfo(i).rs2FromRs2, io.intReadPorts(i + 1)(1), io.intReadPorts(i + 1)(0)) 204 }.elsewhen(io.fusionInfo(i).rs2FromZero) { 205 uops(i).psrc(1) := 0.U 206 } 207 } 208 uops(i).oldPdest := Mux1H(Seq( 209 uops(i).rfWen -> io.intReadPorts(i).last, 210 uops(i).fpWen -> io.fpReadPorts (i).last, 211 uops(i).vecWen -> io.vecReadPorts(i)(vecOldVdIdx), 212 )) 213 uops(i).eliminatedMove := isMove(i) 214 215 // update pdest 216 uops(i).pdest := MuxCase(0.U, Seq( 217 needIntDest(i) -> intFreeList.io.allocatePhyReg(i), 218 (needFpDest(i) || needVecDest(i)) -> fpFreeList.io.allocatePhyReg(i), 219 )) 220 221 // Assign performance counters 222 uops(i).debugInfo.renameTime := GTimer() 223 224 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !io.robCommits.isWalk 225 io.out(i).bits := uops(i) 226 // Todo: move these shit in decode stage 227 // dirty code for fence. The lsrc is passed by imm. 228 when (io.out(i).bits.fuType === FuType.fence.U) { 229 io.out(i).bits.imm := Cat(io.in(i).bits.lsrc(1), io.in(i).bits.lsrc(0)) 230 } 231 232 // dirty code for SoftPrefetch (prefetch.r/prefetch.w) 233// when (io.in(i).bits.isSoftPrefetch) { 234// io.out(i).bits.fuType := FuType.ldu.U 235// io.out(i).bits.fuOpType := Mux(io.in(i).bits.lsrc(1) === 1.U, LSUOpType.prefetch_r, LSUOpType.prefetch_w) 236// io.out(i).bits.selImm := SelImm.IMM_S 237// io.out(i).bits.imm := Cat(io.in(i).bits.imm(io.in(i).bits.imm.getWidth - 1, 5), 0.U(5.W)) 238// } 239 240 // write speculative rename table 241 // we update rat later inside commit code 242 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 243 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 244 vecSpecWen(i) := needVecDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 245 246 if (i < CommitWidth) { 247 walkIntSpecWen(i) := walkNeedIntDest(i) && !io.redirect.valid 248 walkPdest(i) := io.robCommits.info(i).pdest 249 } else { 250 walkPdest(i) := io.out(i).bits.pdest 251 } 252 253 intRefCounter.io.allocate(i).valid := Mux(io.robCommits.isWalk, walkIntSpecWen(i), intSpecWen(i)) 254 intRefCounter.io.allocate(i).bits := Mux(io.robCommits.isWalk, walkPdest(i), io.out(i).bits.pdest) 255 } 256 257 /** 258 * How to set psrc: 259 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 260 * - default: psrc from RAT 261 * How to set pdest: 262 * - Mux(isMove, psrc, pdest_from_freelist). 263 * 264 * The critical path of rename lies here: 265 * When move elimination is enabled, we need to update the rat with psrc. 266 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 267 * 268 * If we expand these logic for pdest(N): 269 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 270 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 271 * Mux(bypass(N, N - 2), pdest(N - 2), 272 * ... 273 * Mux(bypass(N, 0), pdest(0), 274 * rat_out(N))...)), 275 * freelist_out(N)) 276 */ 277 // a simple functional model for now 278 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 279 280 // psrc(n) + pdest(1) 281 val bypassCond: Vec[MixedVec[UInt]] = Wire(Vec(numRegSrc + 1, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 282 require(io.in(0).bits.srcType.size == io.in(0).bits.numSrc) 283 private val pdestLoc = io.in.head.bits.srcType.size // 2 vector src: v0, vl&vtype 284 println(s"[Rename] idx of pdest in bypassCond $pdestLoc") 285 for (i <- 1 until RenameWidth) { 286 val vecCond = io.in(i).bits.srcType.map(_ === SrcType.vp) :+ needVecDest(i) 287 val fpCond = io.in(i).bits.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 288 val intCond = io.in(i).bits.srcType.map(_ === SrcType.xp) :+ needIntDest(i) 289 val target = io.in(i).bits.lsrc :+ io.in(i).bits.ldest 290 for (((((cond1, cond2), cond3), t), j) <- vecCond.zip(fpCond).zip(intCond).zip(target).zipWithIndex) { 291 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 292 val indexMatch = in.bits.ldest === t 293 val writeMatch = cond3 && needIntDest(j) || cond2 && needFpDest(j) || cond1 && needVecDest(j) 294 indexMatch && writeMatch 295 } 296 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 297 } 298 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 299 (z, next) => Mux(next._2, next._1, z) 300 } 301 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 302 (z, next) => Mux(next._2, next._1, z) 303 } 304 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 305 (z, next) => Mux(next._2, next._1, z) 306 } 307 io.out(i).bits.psrc(3) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).psrc(3)) { 308 (z, next) => Mux(next._2, next._1, z) 309 } 310 io.out(i).bits.psrc(4) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(4)(i-1).asBools).foldLeft(uops(i).psrc(4)) { 311 (z, next) => Mux(next._2, next._1, z) 312 } 313 io.out(i).bits.oldPdest := io.out.take(i).map(_.bits.pdest).zip(bypassCond(pdestLoc)(i-1).asBools).foldLeft(uops(i).oldPdest) { 314 (z, next) => Mux(next._2, next._1, z) 315 } 316 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 317 318 // Todo: better implementation for fields reuse 319 // For fused-lui-load, load.src(0) is replaced by the imm. 320 val last_is_lui = io.in(i - 1).bits.selImm === SelImm.IMM_U && io.in(i - 1).bits.srcType(0) =/= SrcType.pc 321 val this_is_load = io.in(i).bits.fuType === FuType.ldu.U 322 val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ldest === io.in(i).bits.lsrc(0) 323 val fused_lui_load = last_is_lui && this_is_load && lui_to_load && false.B // Todo: enable it 324 when (fused_lui_load) { 325 // The first LOAD operand (base address) is replaced by LUI-imm and stored in {psrc, imm} 326 val lui_imm = io.in(i - 1).bits.imm(19, 0) 327 val ld_imm = io.in(i).bits.imm 328 io.out(i).bits.srcType(0) := SrcType.imm 329 io.out(i).bits.imm := Imm_LUI_LOAD().immFromLuiLoad(lui_imm, ld_imm) 330 val psrcWidth = uops(i).psrc.head.getWidth 331 val lui_imm_in_imm = 20/*Todo: uops(i).imm.getWidth*/ - Imm_I().len 332 val left_lui_imm = Imm_U().len - lui_imm_in_imm 333 require(2 * psrcWidth >= left_lui_imm, "cannot fused lui and load with psrc") 334 io.out(i).bits.psrc(0) := lui_imm(lui_imm_in_imm + psrcWidth - 1, lui_imm_in_imm) 335 io.out(i).bits.psrc(1) := lui_imm(lui_imm.getWidth - 1, lui_imm_in_imm + psrcWidth) 336 } 337 338 } 339 340 /** 341 * Instructions commit: update freelist and rename table 342 */ 343 for (i <- 0 until CommitWidth) { 344 val commitValid = io.robCommits.isCommit && io.robCommits.commitValid(i) 345 val walkValid = io.robCommits.isWalk && io.robCommits.walkValid(i) 346 347 // I. RAT Update 348 // When redirect happens (mis-prediction), don't update the rename table 349 io.intRenamePorts(i).wen := intSpecWen(i) 350 io.intRenamePorts(i).addr := uops(i).ldest 351 io.intRenamePorts(i).data := io.out(i).bits.pdest 352 353 io.fpRenamePorts(i).wen := fpSpecWen(i) 354 io.fpRenamePorts(i).addr := uops(i).ldest 355 io.fpRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 356 357 io.vecRenamePorts(i).wen := vecSpecWen(i) 358 io.vecRenamePorts(i).addr := uops(i).ldest 359 io.vecRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 360 361 // II. Free List Update 362 intFreeList.io.freeReq(i) := intRefCounter.io.freeRegs(i).valid 363 intFreeList.io.freePhyReg(i) := intRefCounter.io.freeRegs(i).bits 364 fpFreeList.io.freeReq(i) := commitValid && (needDestRegCommit(Reg_F, io.robCommits.info(i)) || needDestRegCommit(Reg_V, io.robCommits.info(i))) 365 fpFreeList.io.freePhyReg(i) := io.robCommits.info(i).old_pdest 366 367 intRefCounter.io.deallocate(i).valid := commitValid && needDestRegCommit(Reg_I, io.robCommits.info(i)) && !io.robCommits.isWalk 368 intRefCounter.io.deallocate(i).bits := io.robCommits.info(i).old_pdest 369 } 370 371 when(io.robCommits.isWalk) { 372 (intFreeList.io.allocateReq zip intFreeList.io.allocatePhyReg).take(CommitWidth) zip io.robCommits.info foreach { 373 case ((reqValid, allocReg), commitInfo) => when(reqValid) { 374 XSError(allocReg =/= commitInfo.pdest, "walk alloc reg =/= rob reg\n") 375 } 376 } 377 (fpFreeList.io.allocateReq zip fpFreeList.io.allocatePhyReg).take(CommitWidth) zip io.robCommits.info foreach { 378 case ((reqValid, allocReg), commitInfo) => when(reqValid) { 379 XSError(allocReg =/= commitInfo.pdest, "walk alloc reg =/= rob reg\n") 380 } 381 } 382 } 383 384 /* 385 Debug and performance counters 386 */ 387 def printRenameInfo(in: DecoupledIO[DecodedInst], out: DecoupledIO[DynInst]) = { 388 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.pc)} in(${in.valid},${in.ready}) " + 389 p"lsrc(0):${in.bits.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 390 p"lsrc(1):${in.bits.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 391 p"lsrc(2):${in.bits.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 392 p"ldest:${in.bits.ldest} -> pdest:${out.bits.pdest} " + 393 p"old_pdest:${out.bits.oldPdest}\n" 394 // Todo: add no lsrc -> psrc map print 395 ) 396 } 397 398 for ((x,y) <- io.in.zip(io.out)) { 399 printRenameInfo(x, y) 400 } 401 402 XSDebug(io.robCommits.isWalk, p"Walk Recovery Enabled\n") 403 XSDebug(io.robCommits.isWalk, p"validVec:${Binary(io.robCommits.walkValid.asUInt)}\n") 404 for (i <- 0 until CommitWidth) { 405 val info = io.robCommits.info(i) 406 XSDebug(io.robCommits.isWalk && io.robCommits.walkValid(i), p"[#$i walk info] pc:${Hexadecimal(info.pc)} " + 407 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} vecWen:${info.vecWen}" + 408 p"pdest:${info.pdest} old_pdest:${info.old_pdest}\n") 409 } 410 411 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 412 413 XSPerfAccumulate("in", Mux(RegNext(io.in(0).ready), PopCount(io.in.map(_.valid)), 0.U)) 414 XSPerfAccumulate("utilization", PopCount(io.in.map(_.valid))) 415 XSPerfAccumulate("waitInstr", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready))) 416 XSPerfAccumulate("stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 417 XSPerfAccumulate("stall_cycle_fp", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 418 XSPerfAccumulate("stall_cycle_int", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk) 419 XSPerfAccumulate("stall_cycle_walk", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 420 XSPerfAccumulate("recovery_bubbles", PopCount(io.in.map(_.valid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk))) 421 422 XSPerfHistogram("slots_fire", PopCount(io.out.map(_.fire)), true.B, 0, RenameWidth+1, 1) 423 // Explaination: when out(0) not fire, PopCount(valid) is not meaningfull 424 XSPerfHistogram("slots_valid_pure", PopCount(io.in.map(_.valid)), io.out(0).fire, 0, RenameWidth+1, 1) 425 XSPerfHistogram("slots_valid_rough", PopCount(io.in.map(_.valid)), true.B, 0, RenameWidth+1, 1) 426 427 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire && out.bits.isMove))) 428 val is_fused_lui_load = io.out.map(o => o.fire && o.bits.fuType === FuType.ldu.U && o.bits.srcType(0) === SrcType.imm) 429 XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load)) 430 431 432 val renamePerf = Seq( 433 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 434 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 435 ("rename_stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk), 436 ("rename_stall_cycle_fp ", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk), 437 ("rename_stall_cycle_int ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk), 438 ("rename_stall_cycle_walk ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 439 ) 440 val intFlPerf = intFreeList.getPerfEvents 441 val fpFlPerf = fpFreeList.getPerfEvents 442 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf 443 generatePerfEvent() 444} 445