1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import system._ 24import chipsalliance.rocketchip.config._ 25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 26import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 27import xiangshan.backend.dispatch.DispatchParameters 28import xiangshan.backend.exu.ExuParameters 29import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters} 30import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 31 32class DefaultConfig(n: Int) extends Config((site, here, up) => { 33 case XLen => 64 34 case DebugOptionsKey => DebugOptions() 35 case SoCParamsKey => SoCParameters( 36 cores = List.tabulate(n){ i => XSCoreParameters(HartId = i) } 37 ) 38}) 39 40// Synthesizable minimal XiangShan 41// * It is still an out-of-order, super-scalaer arch 42// * L1 cache included 43// * L2 cache NOT included 44// * L3 cache included 45class MinimalConfig(n: Int = 1) extends Config( 46 new DefaultConfig(n).alter((site, here, up) => { 47 case SoCParamsKey => up(SoCParamsKey).copy( 48 cores = up(SoCParamsKey).cores.map(_.copy( 49 DecodeWidth = 2, 50 RenameWidth = 2, 51 FetchWidth = 4, 52 IssQueSize = 8, 53 NRPhyRegs = 64, 54 LoadQueueSize = 16, 55 StoreQueueSize = 12, 56 RoqSize = 32, 57 BrqSize = 8, 58 FtqSize = 8, 59 IBufSize = 16, 60 StoreBufferSize = 4, 61 StoreBufferThreshold = 3, 62 dpParams = DispatchParameters( 63 IntDqSize = 12, 64 FpDqSize = 12, 65 LsDqSize = 12, 66 IntDqDeqWidth = 4, 67 FpDqDeqWidth = 4, 68 LsDqDeqWidth = 4 69 ), 70 exuParameters = ExuParameters( 71 JmpCnt = 1, 72 AluCnt = 2, 73 MulCnt = 0, 74 MduCnt = 1, 75 FmacCnt = 1, 76 FmiscCnt = 1, 77 FmiscDivSqrtCnt = 0, 78 LduCnt = 2, 79 StuCnt = 2 80 ), 81 icacheParameters = ICacheParameters( 82 nSets = 64, // 16KB ICache 83 tagECC = Some("parity"), 84 dataECC = Some("parity"), 85 replacer = Some("setplru"), 86 nMissEntries = 2 87 ), 88 dcacheParameters = DCacheParameters( 89 nSets = 64, // 32KB DCache 90 nWays = 8, 91 tagECC = Some("secded"), 92 dataECC = Some("secded"), 93 replacer = Some("setplru"), 94 nMissEntries = 4, 95 nProbeEntries = 4, 96 nReleaseEntries = 4, 97 nStoreReplayEntries = 4, 98 ), 99 L2Size = 128 * 1024, // 128KB 100 L2NWays = 8, 101 EnableBPD = false, // disable TAGE 102 EnableLoop = false, 103 TlbEntrySize = 4, 104 TlbSPEntrySize = 2, 105 PtwL1EntrySize = 2, 106 PtwL2EntrySize = 64, 107 PtwL3EntrySize = 128, 108 PtwSPEntrySize = 2, 109 useFakeL2Cache = true, 110 )), 111 L3Size = 32 * 1024, // 32KB 112 ) 113 }) 114) 115 116// Non-synthesizable MinimalConfig, for fast simulation only 117class MinimalSimConfig(n: Int = 1) extends Config( 118 new MinimalConfig(n).alter((site, here, up) => { 119 case SoCParamsKey => up(SoCParamsKey).copy( 120 cores = up(SoCParamsKey).cores.map(_.copy( 121 useFakeDCache = true, 122 useFakePTW = true, 123 useFakeL1plusCache = true, 124 )), 125 useFakeL3Cache = true 126 ) 127 }) 128) 129