mem: enable non pow of 2 load queue size (#912)

* Fix allocated flag update logic

mem,sq: replace !hasInflightMMIO flag with s_idle

mem,sq: don't set commited flag when mmio commits

For simplicity, we increase cmtPtr and set commited flags when
store instructions commit from ROB. However, this causes problems
when there's an MMI

mem,sq: don't set commited flag when mmio commits

For simplicity, we increase cmtPtr and set commited flags when
store instructions commit from ROB. However, this causes problems
when there's an MMIO at the head and new instructions enqueue after
the MMIO finishes but before the MMIO commits.

For example, at cycle T0 mmio store instruction with sqPtr p0
finishes and deqPtr is increased. At cycle T1, a new store
instruction enqueues and the p0 is allocated for this new instruction.
At cycle T2, the mmio instruction commits from ROB. With cmtPtr,
p0 is set to commited. However, since p0 is allocated to the new
store instruction, the commited flag should be false.

The example causes at least two issues. (1) when redirect happens, p0
will not be flushed. (2) p0 will be commit to sbuffer before p0
writes back to store queue.

In this commit, we change how commited flag works. We add a
`hasInflightMMIO` flag. When store instructions commit, we only
set commited flag when `hasInflightMMIO` is not set.

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sbuffer: ignore invalid forward request

mem: drain sbuffer when v/ptag mismatch

mem: use vaddr match, paddr fix forward in sbuffer

Now we use vaddr tag to select data to be forwarded in sbuffer.
Vtag / ptag match result will be compared latter to check if vaddr
based forward is

mem: use vaddr match, paddr fix forward in sbuffer

Now we use vaddr tag to select data to be forwarded in sbuffer.
Vtag / ptag match result will be compared latter to check if vaddr
based forward is correct. If not, an microarichitectural exception
should be raised to flush SQ and committed sbuffer.

TODO: forward fail microarichitectural exception

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mem: use vaddr match, paddr fix forward in SQ

Vaddr Match, Paddr Fix (VMPF) store to load forward uses vaddr cam
result to select data to be forwarded. Vaddr cam result and paddr cam
result will be

mem: use vaddr match, paddr fix forward in SQ

Vaddr Match, Paddr Fix (VMPF) store to load forward uses vaddr cam
result to select data to be forwarded. Vaddr cam result and paddr cam
result will be compared to check if vaddr based forward is correct.
If not, an microarichitectural exception should be raised to flush SQ
and committed sbuffer.

TODO: forward fail microarichitectural exception

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mem: add vaddr forward profiling framework

misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

cache,mmu: split PTW and TLB into several files (#890)

core: move ftq to frontend

Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.

Configs: update MinimalConfig for FPGA (#809)

* Configs: add MinimalFPGAConfig

* TODO: change cache parameters

* Chore: add parameter print

* README: add simulation usage

Currently, Xian

Configs: update MinimalConfig for FPGA (#809)

* Configs: add MinimalFPGAConfig

* TODO: change cache parameters

* Chore: add parameter print

* README: add simulation usage

Currently, XiangShan does not support NOOP FPGA. FPGA related
instructions are removed

* Configs: limit frontend width in MinimalConfig

* MinimalConfig: limit L1/L2 cache size

* MinimalConfig: limit ptw size, disable L2

* MinimalConfig: limit L3 size

* Sbuffer: force trigger write if sbuffer fulls

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backend,mem: add Store Sets memory dependence predictor (#796)

* LoadQueue: send stFtqIdx via rollback request

* It will make it possible for setore set to update its SSIT

* StoreSet: setup st

backend,mem: add Store Sets memory dependence predictor (#796)

* LoadQueue: send stFtqIdx via rollback request

* It will make it possible for setore set to update its SSIT

* StoreSet: setup store set update req

* StoreSet: add store set identifier table (SSIT)

* StoreSet: add last fetched store table (LFST)

* StoreSet: put SSIT into decode stage

* StoreSet: put LFST into dispatch1

* Future work: optimize timing

* RS: store rs now supports delayed issue

* StoreSet: add perf counter

* StoreSet: fix SSIT update logic

* StoreSet: delay LFST update input for 1 cycle

* StoreSet: fix LFST update logic

* StoreSet: fix LFST raddr width

* StoreSet: do not force store in ss issue in order

Classic store set requires store in the same store set issue in seq.
However, in current micro-architecture, such restrict will lead to
severe perf lost. We choose to disable it until we find another way
to fix it.

* StoreSet: support ooo store in the same store set

* StoreSet: fix store set merge logic

* StoreSet: check earlier store when read LFST

* If store-load pair is in the same dispatch bundle, loadWaitBit should
also be set for load

* StoreSet: increase default SSIT flush period

* StoreSet: fix LFST read logic

* Fix commit c0e541d14

* StoreSet: add StoreSetEnable parameter

* RSFeedback: add source type

* StoreQueue: split store addr and store data

* StoreQueue: update ls forward logic

* Now it supports splited addr and data

* Chore: force assign name for load/store unit

* RS: add rs'support for store a-d split

* StoreQueue: fix stlf logic

* StoreQueue: fix addr wb sq update logic

* AtomicsUnit: support splited a/d

* Parameters: disable store set by default

* WaitTable: wait table will not cause store delay

* WaitTable: recover default reset period to 2^17

* Fix dev-stad merge conflict

* StoreSet: enable storeset

* RS: disable store rs delay logic

CI perf shows that current delay logic will cause perf loss. Disable
unnecessary delay logic will help.

To be more specific, `io.readyVec` caused the problem. It will be
updated in future commits.

* RS: opt select logic with load delay (ldWait)

* StoreSet: disable 2-bit lwt

Co-authored-by: ZhangZifei <[email protected]>

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cache: support fake dcache, ptw, l1pluscache, l2cache and l3cache (#795)

In this commit, we add support for using DPI-C calls to replace
DCache, PTW and L1plusCache. L2Cache and L3 Cache are also a

cache: support fake dcache, ptw, l1pluscache, l2cache and l3cache (#795)

In this commit, we add support for using DPI-C calls to replace
DCache, PTW and L1plusCache. L2Cache and L3 Cache are also allowed to
be ignored or bypassed. Configurations are controlled by useFakeDCache,
useFakePTW, useFakeL1plusCache, useFakeL2Cache and useFakeL3Cache.
However, some configurations may not work correctly.

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MemBlock: split store addr and store data (#781)

* RSFeedback: add source type

* StoreQueue: split store addr and store data

* StoreQueue: update ls forward logic

* Now it supports splited

MemBlock: split store addr and store data (#781)

* RSFeedback: add source type

* StoreQueue: split store addr and store data

* StoreQueue: update ls forward logic

* Now it supports splited addr and data

* Chore: force assign name for load/store unit

* RS: add rs'support for store a-d split

* StoreQueue: fix stlf logic

* StoreQueue: fix addr wb sq update logic

* AtomicsUnit: support splited a/d

* StoreQueue: add sbuffer enq condition assertion

Store data op (std) may still be invalid after store addr op's (sta)
commitment, so datavalid needs to be checked before commiting
store data to sbuffer

Note that at current commit a non-completed std op for a
commited store may exist. We should make sure that uop
will not be cancelled by a latter branch mispredict. More work
to be done!

* Roq: add std/sta split writeback logic

Now store will commit only if both sta & std have been writebacked

Co-authored-by: ZhangZifei <[email protected]>

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difftest: support SMP difftest (#786)

* difftest: revise coreid assignment

* nemuproxy: compatible for smp difftest

* difftest: fix goldenMem initialization problem

* difftest: goldenMem up

difftest: support SMP difftest (#786)

* difftest: revise coreid assignment

* nemuproxy: compatible for smp difftest

* difftest: fix goldenMem initialization problem

* difftest: goldenMem update works

* difftest: api compatible for modified nemu

* difftest: support load check for smp difftest
* verification is required later

* misc: remove unused xstrap wiring

* Remove unused code

* difftest: add latch for difftest-loadevent

* misc: update inclusivecache

* difftest: reset resp for sbuffer & atomic-unit to avoid duplicate update
of goldenMem

* difftest: dump coreid when difftest failed

* difftest: dump corresponding memory of another core when smp difftest failed
* Only works for dual-core

* difftest: fix interrupt handler

* difftest: cleanup code

* roq: remove legacy signal for difftest

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Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr.
(2) DPI-C is cross-platform (Verilator, VCS, ...)
(3) difftest APIs are splited from emu.cpp to possibly support more backend platforms
(NEMU, Spike, ...)

The performance at this commit is quite slower than the original emu.
Performance issues will be fixed later.

* [WIP] SimTop: try to use 'XSTop' as soc

* CircularQueuePtr: ues F-bounded polymorphis instead implict helper

* Refactor parameters & Clean up code

* difftest: support basic difftest

* Support diffetst in new sim top

* Difftest; convert recode fmt to ieee754 when comparing fp regs

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Debug: add int/exc inst wb to debug queue

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Difftest: fix naive commit num limit

Co-authored-by: Yinan Xu <[email protected]>
Co-authored-by: William Wang <[email protected]>

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CircularQueuePtr: use F-bounded polymorphism instead of implicit helper (#750)

Add some in-core hardware performance counters (#731)

* csr: remove unused input perfcnt io

* perfcnt: add some in-core hardware performance counters

* perfcnt: optimize timing for hardware pe

Add some in-core hardware performance counters (#731)

* csr: remove unused input perfcnt io

* perfcnt: add some in-core hardware performance counters

* perfcnt: optimize timing for hardware performance counters

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Merge branch 'master' of github.com:RISCVERS/XiangShan

Refactor XSPerf, now we have three XSPerf Functions.
XSPerfAccumulate: sum up performance values.
XSPerfHistogram: count the occurrence of performance values, split them
into bins, so that we can est

Refactor XSPerf, now we have three XSPerf Functions.
XSPerfAccumulate: sum up performance values.
XSPerfHistogram: count the occurrence of performance values, split them
into bins, so that we can estimate their distribution.
XSPerfMax: get max of performance values.

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Perf: add queue perf analysis utility (#714)

* perf: set acc arg of XSPerf as false by default

* perf: add write-port competition counter for intBlock & floatBlock

* perf: remove prefix of per

Perf: add queue perf analysis utility (#714)

* perf: set acc arg of XSPerf as false by default

* perf: add write-port competition counter for intBlock & floatBlock

* perf: remove prefix of perf signal

* perf: add perf-cnt for interface between frontend & backend

* perf: modify perf-cnt for prefetchers

* Ftq: bypass 'commit state' to fix dequeue bug

* perf: uptimize perf-cnt in ctrlblock & ftq

* perf: fix compilation problem in ftq

* perf: remove duplicate perf-cnt

* perf: calcu extra walk cycle exceeding frontend flush bubble

* Revert "perf: calcu extra walk cycle exceeding frontend flush bubble"

This reverts commit 2c30e9896b6af93a34e2d8d78055d810ebd0ac70.

* perf: add perf-cnt for ifu

* perf: add perf-cnt for rs

* RS: optimize numExist signal

* RS: fix some typo

* perf: add QueuePerf util to monitor usage info of queues

* perf: remove some duprecate perfcnt

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Add more performance counters (#662)

StoreQueue: issuePtr should not exceed enqPtr (#636)