1package top 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import utils._ 7import system._ 8import chipsalliance.rocketchip.config._ 9import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 10import sifive.blocks.inclusivecache.{InclusiveCache, InclusiveCacheMicroParameters, CacheParameters} 11import xiangshan.backend.dispatch.DispatchParameters 12import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters} 13import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 14 15class DefaultConfig(n: Int) extends Config((site, here, up) => { 16 case XLen => 64 17 case DebugOptionsKey => DebugOptions() 18 case SoCParamsKey => SoCParameters( 19 cores = List.tabulate(n){ i => XSCoreParameters(HartId = i) } 20 ) 21}) 22 23// Synthesizable minimal XiangShan 24// * It is still an out-of-order, super-scalaer arch 25// * L1 cache included 26// * L2 cache NOT included 27// * L3 cache included 28class MinimalConfig(n: Int = 1) extends Config( 29 new DefaultConfig(n).alter((site, here, up) => { 30 case SoCParamsKey => up(SoCParamsKey).copy( 31 cores = up(SoCParamsKey).cores.map(_.copy( 32 DecodeWidth = 2, 33 RenameWidth = 2, 34 FetchWidth = 4, 35 IssQueSize = 8, 36 NRPhyRegs = 80, 37 LoadQueueSize = 16, 38 StoreQueueSize = 16, 39 RoqSize = 32, 40 BrqSize = 8, 41 FtqSize = 16, 42 IBufSize = 16, 43 StoreBufferSize = 4, 44 StoreBufferThreshold = 3, 45 dpParams = DispatchParameters( 46 IntDqSize = 8, 47 FpDqSize = 8, 48 LsDqSize = 8, 49 IntDqDeqWidth = 4, 50 FpDqDeqWidth = 4, 51 LsDqDeqWidth = 4 52 ), 53 icacheParameters = ICacheParameters( 54 nSets = 8, // 4KB ICache 55 tagECC = Some("parity"), 56 dataECC = Some("parity"), 57 replacer = Some("setplru"), 58 nMissEntries = 2 59 ), 60 dcacheParameters = DCacheParameters( 61 nSets = 8, // 4KB DCache 62 nWays = 4, 63 tagECC = Some("secded"), 64 dataECC = Some("secded"), 65 replacer = Some("setplru"), 66 nMissEntries = 4, 67 nProbeEntries = 4, 68 nReleaseEntries = 4, 69 nStoreReplayEntries = 4, 70 ), 71 L2Size = 16 * 1024, // 16KB 72 L2NWays = 8, 73 EnableBPD = false, // disable TAGE 74 EnableLoop = false, 75 TlbEntrySize = 4, 76 TlbSPEntrySize = 2, 77 PtwL1EntrySize = 2, 78 PtwL2EntrySize = 64, 79 PtwL3EntrySize = 128, 80 PtwSPEntrySize = 2, 81 useFakeL2Cache = true, 82 )), 83 L3Size = 32 * 1024, // 32KB 84 ) 85 }) 86) 87 88// Non-synthesizable MinimalConfig, for fast simulation only 89class MinimalSimConfig(n: Int = 1) extends Config( 90 new MinimalConfig(n).alter((site, here, up) => { 91 case SoCParamsKey => up(SoCParamsKey).copy( 92 cores = up(SoCParamsKey).cores.map(_.copy( 93 useFakeDCache = true, 94 useFakePTW = true, 95 useFakeL1plusCache = true, 96 )), 97 useFakeL3Cache = true 98 ) 99 }) 100) 101