1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.{DecodeStage, ImmUnion, WaitTableParameters} 8import xiangshan.backend.rename.{BusyTable, Rename} 9import xiangshan.backend.dispatch.Dispatch 10import xiangshan.backend.exu._ 11import xiangshan.backend.exu.Exu.exuConfigs 12import xiangshan.backend.ftq.{Ftq, FtqRead, GetPcByFtq} 13import xiangshan.backend.regfile.RfReadPort 14import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqLsqIO, RoqPtr} 15import xiangshan.mem.LsqEnqIO 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val readRf = Vec(NRIntReadPorts, Output(UInt(PhyRegIdxWidth.W))) 20 val jumpPc = Output(UInt(VAddrBits.W)) 21 val jalr_target = Output(UInt(VAddrBits.W)) 22 // int block only uses port 0~7 23 val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(8 / 2).W))) // TODO parameterize 8 here 24 val redirect = ValidIO(new Redirect) 25 val flush = Output(Bool()) 26} 27 28class CtrlToFpBlockIO extends XSBundle { 29 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 30 val readRf = Vec(NRFpReadPorts, Output(UInt(PhyRegIdxWidth.W))) 31 // fp block uses port 0~11 32 val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W))) 33 val redirect = ValidIO(new Redirect) 34 val flush = Output(Bool()) 35} 36 37class CtrlToLsBlockIO extends XSBundle { 38 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 39 val enqLsq = Flipped(new LsqEnqIO) 40 val waitTableUpdate = Vec(StorePipelineWidth, Input(new WaitTableUpdateReq)) 41 val redirect = ValidIO(new Redirect) 42 val flush = Output(Bool()) 43} 44 45class RedirectGenerator extends XSModule with HasCircularQueuePtrHelper with WaitTableParameters { 46 val numRedirect = exuParameters.JmpCnt + exuParameters.AluCnt 47 val io = IO(new Bundle() { 48 val exuMispredict = Vec(numRedirect, Flipped(ValidIO(new ExuOutput))) 49 val loadReplay = Flipped(ValidIO(new Redirect)) 50 val flush = Input(Bool()) 51 val stage1FtqRead = Vec(numRedirect + 1, new FtqRead) 52 val stage2FtqRead = new FtqRead 53 val stage2Redirect = ValidIO(new Redirect) 54 val stage3Redirect = ValidIO(new Redirect) 55 val waitTableUpdate = Output(new WaitTableUpdateReq) 56 }) 57 /* 58 LoadQueue Jump ALU0 ALU1 ALU2 ALU3 exception Stage1 59 | | | | | | | 60 |============= reg & compare =====| | ======== 61 | | 62 | | 63 | | Stage2 64 | | 65 redirect (flush backend) | 66 | | 67 === reg === | ======== 68 | | 69 |----- mux (exception first) -----| Stage3 70 | 71 redirect (send to frontend) 72 */ 73 private class Wrapper(val n: Int) extends Bundle { 74 val redirect = new Redirect 75 val valid = Bool() 76 val idx = UInt(log2Up(n).W) 77 } 78 def selectOldestRedirect(xs: Seq[Valid[Redirect]]): Vec[Bool] = { 79 val compareVec = (0 until xs.length).map(i => (0 until i).map(j => isAfter(xs(j).bits.roqIdx, xs(i).bits.roqIdx))) 80 val resultOnehot = VecInit((0 until xs.length).map(i => Cat((0 until xs.length).map(j => 81 (if (j < i) !xs(j).valid || compareVec(i)(j) 82 else if (j == i) xs(i).valid 83 else !xs(j).valid || !compareVec(j)(i)) 84 )).andR)) 85 resultOnehot 86 } 87 88 for((ptr, redirect) <- io.stage1FtqRead.map(_.ptr).zip( 89 io.exuMispredict.map(_.bits.redirect) :+ io.loadReplay.bits 90 )){ ptr := redirect.ftqIdx } 91 92 def getRedirect(exuOut: Valid[ExuOutput]): ValidIO[Redirect] = { 93 val redirect = Wire(Valid(new Redirect)) 94 redirect.valid := exuOut.valid && exuOut.bits.redirect.cfiUpdate.isMisPred 95 redirect.bits := exuOut.bits.redirect 96 redirect 97 } 98 99 val jumpOut = io.exuMispredict.head 100 val allRedirect = VecInit(io.exuMispredict.map(x => getRedirect(x)) :+ io.loadReplay) 101 val oldestOneHot = selectOldestRedirect(allRedirect) 102 val needFlushVec = VecInit(allRedirect.map(_.bits.roqIdx.needFlush(io.stage2Redirect, io.flush))) 103 val oldestValid = VecInit(oldestOneHot.zip(needFlushVec).map{ case (v, f) => v && !f }).asUInt.orR 104 val oldestExuOutput = Mux1H((0 until 5).map(oldestOneHot), io.exuMispredict) 105 val oldestRedirect = Mux1H(oldestOneHot, allRedirect) 106 107 val s1_jumpTarget = RegEnable(jumpOut.bits.redirect.cfiUpdate.target, jumpOut.valid) 108 val s1_imm12_reg = RegNext(oldestExuOutput.bits.uop.ctrl.imm(11, 0)) 109 val s1_pd = RegNext(oldestExuOutput.bits.uop.cf.pd) 110 val s1_redirect_bits_reg = RegNext(oldestRedirect.bits) 111 val s1_redirect_valid_reg = RegNext(oldestValid) 112 val s1_redirect_onehot = RegNext(oldestOneHot) 113 114 // stage1 -> stage2 115 io.stage2Redirect.valid := s1_redirect_valid_reg && !io.flush 116 io.stage2Redirect.bits := s1_redirect_bits_reg 117 io.stage2Redirect.bits.cfiUpdate := DontCare 118 // at stage2, we read ftq to get pc 119 io.stage2FtqRead.ptr := s1_redirect_bits_reg.ftqIdx 120 121 val s1_isReplay = s1_redirect_onehot(5) 122 val s1_isJump = s1_redirect_onehot(0) 123 val ftqRead = Mux1H(s1_redirect_onehot, io.stage1FtqRead).entry 124 val cfiUpdate_pc = Cat( 125 ftqRead.ftqPC.head(VAddrBits - s1_redirect_bits_reg.ftqOffset.getWidth - instOffsetBits), 126 s1_redirect_bits_reg.ftqOffset, 127 0.U(instOffsetBits.W) 128 ) 129 val real_pc = GetPcByFtq(ftqRead.ftqPC, s1_redirect_bits_reg.ftqOffset, 130 ftqRead.lastPacketPC.valid, 131 ftqRead.lastPacketPC.bits 132 ) 133 val brTarget = real_pc + SignExt(ImmUnion.B.toImm32(s1_imm12_reg), XLEN) 134 val snpc = real_pc + Mux(s1_pd.isRVC, 2.U, 4.U) 135 val target = Mux(s1_isReplay, 136 real_pc, // repaly from itself 137 Mux(s1_redirect_bits_reg.cfiUpdate.taken, 138 Mux(s1_isJump, s1_jumpTarget, brTarget), 139 snpc 140 ) 141 ) 142 143 // update waittable if load violation redirect triggered 144 io.waitTableUpdate.valid := RegNext(s1_isReplay && s1_redirect_valid_reg, init = false.B) 145 io.waitTableUpdate.waddr := RegNext(XORFold(real_pc(VAddrBits-1, 1), WaitTableAddrWidth)) 146 io.waitTableUpdate.wdata := true.B 147 148 io.stage2FtqRead.ptr := s1_redirect_bits_reg.ftqIdx 149 150 val s2_br_mask = RegEnable(ftqRead.br_mask, enable = s1_redirect_valid_reg) 151 val s2_sawNotTakenBranch = RegEnable(VecInit((0 until PredictWidth).map{ i => 152 if(i == 0) false.B else Cat(ftqRead.br_mask.take(i)).orR() 153 })(s1_redirect_bits_reg.ftqOffset), enable = s1_redirect_valid_reg) 154 val s2_hist = RegEnable(ftqRead.hist, enable = s1_redirect_valid_reg) 155 val s2_target = RegEnable(target, enable = s1_redirect_valid_reg) 156 val s2_pd = RegEnable(s1_pd, enable = s1_redirect_valid_reg) 157 val s2_cfiUpdata_pc = RegEnable(cfiUpdate_pc, enable = s1_redirect_valid_reg) 158 val s2_redirect_bits_reg = RegEnable(s1_redirect_bits_reg, enable = s1_redirect_valid_reg) 159 val s2_redirect_valid_reg = RegNext(s1_redirect_valid_reg && !io.flush, init = false.B) 160 val s2_ftqRead = io.stage2FtqRead.entry 161 162 io.stage3Redirect.valid := s2_redirect_valid_reg 163 io.stage3Redirect.bits := s2_redirect_bits_reg 164 val stage3CfiUpdate = io.stage3Redirect.bits.cfiUpdate 165 stage3CfiUpdate.pc := s2_cfiUpdata_pc 166 stage3CfiUpdate.pd := s2_pd 167 stage3CfiUpdate.rasSp := s2_ftqRead.rasSp 168 stage3CfiUpdate.rasEntry := s2_ftqRead.rasTop 169 stage3CfiUpdate.predHist := s2_ftqRead.predHist 170 stage3CfiUpdate.specCnt := s2_ftqRead.specCnt 171 stage3CfiUpdate.hist := s2_hist 172 stage3CfiUpdate.predTaken := s2_redirect_bits_reg.cfiUpdate.predTaken 173 stage3CfiUpdate.sawNotTakenBranch := s2_sawNotTakenBranch 174 stage3CfiUpdate.target := s2_target 175 stage3CfiUpdate.taken := s2_redirect_bits_reg.cfiUpdate.taken 176 stage3CfiUpdate.isMisPred := s2_redirect_bits_reg.cfiUpdate.isMisPred 177} 178 179class CtrlBlock extends XSModule with HasCircularQueuePtrHelper { 180 val io = IO(new Bundle { 181 val frontend = Flipped(new FrontendToBackendIO) 182 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 183 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 184 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 185 val toIntBlock = new CtrlToIntBlockIO 186 val toFpBlock = new CtrlToFpBlockIO 187 val toLsBlock = new CtrlToLsBlockIO 188 val roqio = new Bundle { 189 // to int block 190 val toCSR = new RoqCSRIO 191 val exception = ValidIO(new ExceptionInfo) 192 // to mem block 193 val lsq = new RoqLsqIO 194 } 195 val csrCtrl = Input(new CustomCSRCtrlIO) 196 val perfInfo = Output(new Bundle{ 197 val ctrlInfo = new Bundle { 198 val roqFull = Input(Bool()) 199 val intdqFull = Input(Bool()) 200 val fpdqFull = Input(Bool()) 201 val lsdqFull = Input(Bool()) 202 } 203 val bpuInfo = new Bundle { 204 val bpRight = Output(UInt(XLEN.W)) 205 val bpWrong = Output(UInt(XLEN.W)) 206 } 207 }) 208 }) 209 210 val difftestIO = IO(new Bundle() { 211 val fromRoq = new Bundle() { 212 val commit = Output(UInt(32.W)) 213 val thisPC = Output(UInt(XLEN.W)) 214 val thisINST = Output(UInt(32.W)) 215 val skip = Output(UInt(32.W)) 216 val wen = Output(UInt(32.W)) 217 val wdata = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6 218 val wdst = Output(Vec(CommitWidth, UInt(32.W))) // set difftest width to 6 219 val wpc = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6 220 val isRVC = Output(UInt(32.W)) 221 val scFailed = Output(Bool()) 222 val lpaddr = Output(Vec(CommitWidth, UInt(64.W))) 223 val ltype = Output(Vec(CommitWidth, UInt(32.W))) 224 val lfu = Output(Vec(CommitWidth, UInt(4.W))) 225 } 226 }) 227 difftestIO <> DontCare 228 229 val ftq = Module(new Ftq) 230 val trapIO = IO(new TrapIO()) 231 trapIO <> DontCare 232 233 val decode = Module(new DecodeStage) 234 val rename = Module(new Rename) 235 val dispatch = Module(new Dispatch) 236 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 237 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 238 val redirectGen = Module(new RedirectGenerator) 239 240 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt 241 val roq = Module(new Roq(roqWbSize)) 242 243 val backendRedirect = redirectGen.io.stage2Redirect 244 val frontendRedirect = redirectGen.io.stage3Redirect 245 val flush = roq.io.flushOut.valid 246 val flushReg = RegNext(flush) 247 248 val exuRedirect = io.fromIntBlock.exuRedirect.map(x => { 249 val valid = x.valid && x.bits.redirectValid 250 val killedByOlder = x.bits.uop.roqIdx.needFlush(backendRedirect, flushReg) 251 val delayed = Wire(Valid(new ExuOutput)) 252 delayed.valid := RegNext(valid && !killedByOlder, init = false.B) 253 delayed.bits := RegEnable(x.bits, x.valid) 254 delayed 255 }) 256 val loadReplay = Wire(Valid(new Redirect)) 257 loadReplay.valid := RegNext(io.fromLsBlock.replay.valid && 258 !io.fromLsBlock.replay.bits.roqIdx.needFlush(backendRedirect, flushReg), 259 init = false.B 260 ) 261 loadReplay.bits := RegEnable(io.fromLsBlock.replay.bits, io.fromLsBlock.replay.valid) 262 VecInit(ftq.io.ftqRead.tail.dropRight(1)) <> redirectGen.io.stage1FtqRead 263 ftq.io.cfiRead <> redirectGen.io.stage2FtqRead 264 redirectGen.io.exuMispredict <> exuRedirect 265 redirectGen.io.loadReplay <> loadReplay 266 redirectGen.io.flush := flushReg 267 268 ftq.io.enq <> io.frontend.fetchInfo 269 for(i <- 0 until CommitWidth){ 270 ftq.io.roq_commits(i).valid := roq.io.commits.valid(i) && !roq.io.commits.isWalk 271 ftq.io.roq_commits(i).bits := roq.io.commits.info(i) 272 } 273 ftq.io.redirect <> backendRedirect 274 ftq.io.flush := flushReg 275 ftq.io.flushIdx := RegNext(roq.io.flushOut.bits.ftqIdx) 276 ftq.io.flushOffset := RegNext(roq.io.flushOut.bits.ftqOffset) 277 ftq.io.frontendRedirect <> frontendRedirect 278 ftq.io.exuWriteback <> exuRedirect 279 280 ftq.io.ftqRead.last.ptr := roq.io.flushOut.bits.ftqIdx 281 val flushPC = GetPcByFtq( 282 ftq.io.ftqRead.last.entry.ftqPC, 283 RegEnable(roq.io.flushOut.bits.ftqOffset, roq.io.flushOut.valid), 284 ftq.io.ftqRead.last.entry.lastPacketPC.valid, 285 ftq.io.ftqRead.last.entry.lastPacketPC.bits 286 ) 287 288 val flushRedirect = Wire(Valid(new Redirect)) 289 flushRedirect.valid := flushReg 290 flushRedirect.bits := DontCare 291 flushRedirect.bits.ftqIdx := RegEnable(roq.io.flushOut.bits.ftqIdx, flush) 292 flushRedirect.bits.interrupt := true.B 293 flushRedirect.bits.cfiUpdate.target := Mux(io.roqio.toCSR.isXRet || roq.io.exception.valid, 294 io.roqio.toCSR.trapTarget, 295 flushPC + 4.U // flush pipe 296 ) 297 val flushRedirectReg = Wire(Valid(new Redirect)) 298 flushRedirectReg.valid := RegNext(flushRedirect.valid, init = false.B) 299 flushRedirectReg.bits := RegEnable(flushRedirect.bits, enable = flushRedirect.valid) 300 301 io.frontend.redirect_cfiUpdate := Mux(flushRedirectReg.valid, flushRedirectReg, frontendRedirect) 302 io.frontend.commit_cfiUpdate := ftq.io.commit_ftqEntry 303 io.frontend.ftqEnqPtr := ftq.io.enqPtr 304 io.frontend.ftqLeftOne := ftq.io.leftOne 305 306 decode.io.in <> io.frontend.cfVec 307 // currently, we only update wait table when isReplay 308 decode.io.waitTableUpdate(0) <> RegNext(redirectGen.io.waitTableUpdate) 309 decode.io.waitTableUpdate(1) := DontCare 310 decode.io.waitTableUpdate(1).valid := false.B 311 // decode.io.waitTableUpdate <> io.toLsBlock.waitTableUpdate 312 decode.io.csrCtrl := RegNext(io.csrCtrl) 313 314 315 val jumpInst = dispatch.io.enqIQCtrl(0).bits 316 val ftqOffsetReg = Reg(UInt(log2Up(PredictWidth).W)) 317 ftqOffsetReg := jumpInst.cf.ftqOffset 318 ftq.io.ftqRead(0).ptr := jumpInst.cf.ftqPtr // jump 319 io.toIntBlock.jumpPc := GetPcByFtq( 320 ftq.io.ftqRead(0).entry.ftqPC, ftqOffsetReg, 321 ftq.io.ftqRead(0).entry.lastPacketPC.valid, 322 ftq.io.ftqRead(0).entry.lastPacketPC.bits 323 ) 324 io.toIntBlock.jalr_target := ftq.io.ftqRead(0).entry.target 325 326 // pipeline between decode and dispatch 327 for (i <- 0 until RenameWidth) { 328 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, 329 flushReg || io.frontend.redirect_cfiUpdate.valid) 330 } 331 332 rename.io.redirect <> backendRedirect 333 rename.io.flush := flushReg 334 rename.io.roqCommits <> roq.io.commits 335 rename.io.out <> dispatch.io.fromRename 336 rename.io.renameBypass <> dispatch.io.renameBypass 337 rename.io.dispatchInfo <> dispatch.io.preDpInfo 338 rename.io.csrCtrl <> RegNext(io.csrCtrl) 339 340 dispatch.io.redirect <> backendRedirect 341 dispatch.io.flush := flushReg 342 dispatch.io.enqRoq <> roq.io.enq 343 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 344 dispatch.io.readIntRf <> io.toIntBlock.readRf 345 dispatch.io.readFpRf <> io.toFpBlock.readRf 346 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 347 intBusyTable.io.allocPregs(i).valid := preg.isInt 348 fpBusyTable.io.allocPregs(i).valid := preg.isFp 349 intBusyTable.io.allocPregs(i).bits := preg.preg 350 fpBusyTable.io.allocPregs(i).bits := preg.preg 351 } 352 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 353 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 354// dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 355 356 357 fpBusyTable.io.flush := flushReg 358 intBusyTable.io.flush := flushReg 359 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 360 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 361 setPhyRegRdy.bits := wb.bits.uop.pdest 362 } 363 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 364 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 365 setPhyRegRdy.bits := wb.bits.uop.pdest 366 } 367 intBusyTable.io.read <> dispatch.io.readIntState 368 fpBusyTable.io.read <> dispatch.io.readFpState 369 370 roq.io.redirect <> backendRedirect 371 val exeWbResults = VecInit(io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut) 372 for((roq_wb, wb) <- roq.io.exeWbResults.zip(exeWbResults)) { 373 roq_wb.valid := RegNext(wb.valid && !wb.bits.uop.roqIdx.needFlush(backendRedirect, flushReg)) 374 roq_wb.bits := RegNext(wb.bits) 375 } 376 377 // TODO: is 'backendRedirect' necesscary? 378 io.toIntBlock.redirect <> backendRedirect 379 io.toIntBlock.flush <> flushReg 380 io.toFpBlock.redirect <> backendRedirect 381 io.toFpBlock.flush <> flushReg 382 io.toLsBlock.redirect <> backendRedirect 383 io.toLsBlock.flush <> flushReg 384 385 if (!env.FPGAPlatform) { 386 difftestIO.fromRoq <> roq.difftestIO 387 trapIO <> roq.trapIO 388 } 389 390 dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 391 dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 392 393 // roq to int block 394 io.roqio.toCSR <> roq.io.csr 395 io.roqio.toCSR.perfinfo.retiredInstr <> RegNext(roq.io.csr.perfinfo.retiredInstr) 396 io.roqio.exception := roq.io.exception 397 io.roqio.exception.bits.uop.cf.pc := flushPC 398 // roq to mem block 399 io.roqio.lsq <> roq.io.lsq 400 401 io.perfInfo.ctrlInfo.roqFull := RegNext(roq.io.roqFull) 402 io.perfInfo.ctrlInfo.intdqFull := RegNext(dispatch.io.ctrlInfo.intdqFull) 403 io.perfInfo.ctrlInfo.fpdqFull := RegNext(dispatch.io.ctrlInfo.fpdqFull) 404 io.perfInfo.ctrlInfo.lsdqFull := RegNext(dispatch.io.ctrlInfo.lsdqFull) 405 io.perfInfo.bpuInfo <> RegNext(ftq.io.bpuInfo) 406} 407