fix(FusionDecoder): tie output to false when disabled (#4456)

fix(fusion): block fusion when trigger fire and exception happen (#4439)

fix(reidrectGen): fix redirectGen valid signal (#4392)

fix(PFEvent): use `CSRModule` for distribute_csr in PFEvent (#4321)

chore(dispatch): remove useless code and files (#4288)

feat(busytable): support eliminate old vd in new dispatch (#4198)

fix(snapshot): fix bug of snptSelect when only flag is diffrent form redirect robidx

fix(redirectGen): fix bug of csr's cfiUpdate (#4118)

style(decode): add comments and small modification on code style (#3774)

timing(vecExcpMod): add pipe from rab and rat's signals

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
Wh

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
WhenContext. For example, when(cond1){XSDebug(cond2, pable)} to
XSDebug(cond1 && cond2, pable)

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area(trace, pcMem): Trace only get `startAddr` from pcmem

fix(ctrlBlock): fix bug of useSnpt when only flag diffrence

fix(pcmem): add read target from newestEntryTarget

timing(redirectGen): fix timing of addr trans type exception

timing(rob): enqRob pipe for better timing

area(backend): only use startAddr in pcMem

area(backend): remove memCtrl and disble mdp

area(Backend): merge pcMem and pcTargetMem

feat(backend): NewDispatch

fix(CSR, Trace): remove reg `isXRetFlag` in CSR

* remove useless reg `isXRetFlag` in CSR.scala
* fix update of itype for xret instruction

fix(trace): add pipe for traceCoreInterface in memblock and l2top

fix(trace): remove traceTrap & tracePriv from trace pipeline

feat(trace): add TraceCoreInterface in top.

feat(trace): add trace buffer.