1package xiangshan.backend.fu.fpu 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.{FPUCtrlSignals, XSModule} 7import xiangshan.backend.fu.{FunctionUnit, HasPipelineReg} 8 9trait HasUIntToSIntHelper { 10 implicit class UIntToSIntHelper(x: UInt){ 11 def toSInt: SInt = Cat(0.U(1.W), x).asSInt() 12 } 13} 14 15abstract class FPUDataModule(implicit p: Parameters) extends XSModule { 16 val io = IO(new Bundle() { 17 val in = Input(new Bundle() { 18 val src = Vec(3, UInt(65.W)) 19 val fpCtrl = new FPUCtrlSignals 20 val rm = UInt(3.W) 21 }) 22 val out = Output(new Bundle() { 23 val data = UInt(65.W) 24 val fflags = UInt(5.W) 25 }) 26 }) 27 28 val rm = io.in.rm 29 val fflags = io.out.fflags 30} 31 32abstract class FPUSubModule(implicit p: Parameters) extends FunctionUnit(len = 65) 33 with HasUIntToSIntHelper 34{ 35 val rm = IO(Input(UInt(3.W))) 36 val fflags = IO(Output(UInt(5.W))) 37 val dataModule: FPUDataModule 38 def connectDataModule = { 39 dataModule.io.in.src <> io.in.bits.src 40 dataModule.io.in.fpCtrl <> io.in.bits.uop.ctrl.fpu 41 dataModule.io.in.rm <> rm 42 io.out.bits.data := dataModule.io.out.data 43 fflags := dataModule.io.out.fflags 44 } 45} 46 47abstract class FPUPipelineModule(implicit p: Parameters) 48 extends FPUSubModule 49 with HasPipelineReg 50