1package xiangshan.backend.fu.util 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend._ 8import utils.XSDebug 9 10trait HasCSRConst { 11 12 // User Trap Setup 13 val Ustatus = 0x000 14 val Uie = 0x004 15 val Utvec = 0x005 16 17 // User Trap Handling 18 val Uscratch = 0x040 19 val Uepc = 0x041 20 val Ucause = 0x042 21 val Utval = 0x043 22 val Uip = 0x044 23 24 // User Floating-Point CSRs (not implemented) 25 val Fflags = 0x001 26 val Frm = 0x002 27 val Fcsr = 0x003 28 29 // User Counter/Timers 30 val Cycle = 0xC00 31 val Time = 0xC01 32 val Instret = 0xC02 33 34 // Supervisor Trap Setup 35 val Sstatus = 0x100 36 val Sedeleg = 0x102 37 val Sideleg = 0x103 38 val Sie = 0x104 39 val Stvec = 0x105 40 val Scounteren = 0x106 41 42 // Supervisor Trap Handling 43 val Sscratch = 0x140 44 val Sepc = 0x141 45 val Scause = 0x142 46 val Stval = 0x143 47 val Sip = 0x144 48 49 // Supervisor Protection and Translation 50 val Satp = 0x180 51 52 // Supervisor Custom Read/Write 53 val Sbpctl = 0x5C0 54 val Spfctl = 0x5C1 55 val Slvpredctl = 0x5C2 56 val Smblockctl = 0x5C3 57 val Srnctl = 0x5C4 58 59 val Sdsid = 0x9C0 60 61 // Machine Information Registers 62 val Mvendorid = 0xF11 63 val Marchid = 0xF12 64 val Mimpid = 0xF13 65 val Mhartid = 0xF14 66 67 // Machine Trap Setup 68 val Mstatus = 0x300 69 val Misa = 0x301 70 val Medeleg = 0x302 71 val Mideleg = 0x303 72 val Mie = 0x304 73 val Mtvec = 0x305 74 val Mcounteren = 0x306 75 76 // Machine Trap Handling 77 val Mscratch = 0x340 78 val Mepc = 0x341 79 val Mcause = 0x342 80 val Mtval = 0x343 81 val Mip = 0x344 82 83 // Machine Memory Protection 84 // TBD 85 val Pmpcfg0 = 0x3A0 86 val Pmpcfg1 = 0x3A1 87 val Pmpcfg2 = 0x3A2 88 val Pmpcfg3 = 0x3A3 89 val PmpaddrBase = 0x3B0 90 91 // Machine Counter/Timers 92 // Currently, we uses perfcnt csr set instead of standard Machine Counter/Timers 93 // 0xB80 - 0x89F are also used as perfcnt csr 94 val Mcycle = 0xb00 95 val Minstret = 0xb02 96 97 val Mhpmcounter3 = 0xB03 98 val Mhpmcounter4 = 0xB04 99 val Mhpmcounter5 = 0xB05 100 val Mhpmcounter6 = 0xB06 101 val Mhpmcounter7 = 0xB07 102 val Mhpmcounter8 = 0xB08 103 val Mhpmcounter9 = 0xB09 104 val Mhpmcounter10 = 0xB0A 105 val Mhpmcounter11 = 0xB0B 106 val Mhpmcounter12 = 0xB0C 107 val Mhpmcounter13 = 0xB0D 108 val Mhpmcounter14 = 0xB0E 109 val Mhpmcounter15 = 0xB0F 110 val Mhpmcounter16 = 0xB10 111 val Mhpmcounter17 = 0xB11 112 val Mhpmcounter18 = 0xB12 113 val Mhpmcounter19 = 0xB13 114 val Mhpmcounter20 = 0xB14 115 val Mhpmcounter21 = 0xB15 116 val Mhpmcounter22 = 0xB16 117 val Mhpmcounter23 = 0xB17 118 val Mhpmcounter24 = 0xB18 119 val Mhpmcounter25 = 0xB19 120 val Mhpmcounter26 = 0xB1A 121 val Mhpmcounter27 = 0xB1B 122 val Mhpmcounter28 = 0xB1C 123 val Mhpmcounter29 = 0xB1D 124 val Mhpmcounter30 = 0xB1E 125 val Mhpmcounter31 = 0xB1F 126 127 // Machine Counter Setup (not implemented) 128 val Mcountinhibit = 0x320 129 val Mhpmevent3 = 0x323 130 val Mhpmevent4 = 0x324 131 val Mhpmevent5 = 0x325 132 val Mhpmevent6 = 0x326 133 val Mhpmevent7 = 0x327 134 val Mhpmevent8 = 0x328 135 val Mhpmevent9 = 0x329 136 val Mhpmevent10 = 0x32A 137 val Mhpmevent11 = 0x32B 138 val Mhpmevent12 = 0x32C 139 val Mhpmevent13 = 0x32D 140 val Mhpmevent14 = 0x32E 141 val Mhpmevent15 = 0x32F 142 val Mhpmevent16 = 0x330 143 val Mhpmevent17 = 0x331 144 val Mhpmevent18 = 0x332 145 val Mhpmevent19 = 0x333 146 val Mhpmevent20 = 0x334 147 val Mhpmevent21 = 0x335 148 val Mhpmevent22 = 0x336 149 val Mhpmevent23 = 0x337 150 val Mhpmevent24 = 0x338 151 val Mhpmevent25 = 0x339 152 val Mhpmevent26 = 0x33A 153 val Mhpmevent27 = 0x33B 154 val Mhpmevent28 = 0x33C 155 val Mhpmevent29 = 0x33D 156 val Mhpmevent30 = 0x33E 157 val Mhpmevent31 = 0x33F 158 159 // Debug/Trace Registers (shared with Debug Mode) (not implemented) 160 // Debug Mode Registers (not implemented) 161 162 def privEcall = 0x000.U 163 def privEbreak = 0x001.U 164 def privMret = 0x302.U 165 def privSret = 0x102.U 166 def privUret = 0x002.U 167 168 def ModeM = 0x3.U 169 def ModeH = 0x2.U 170 def ModeS = 0x1.U 171 def ModeU = 0x0.U 172 173 def IRQ_UEIP = 0 174 def IRQ_SEIP = 1 175 def IRQ_MEIP = 3 176 177 def IRQ_UTIP = 4 178 def IRQ_STIP = 5 179 def IRQ_MTIP = 7 180 181 def IRQ_USIP = 8 182 def IRQ_SSIP = 9 183 def IRQ_MSIP = 11 184 185 val IntPriority = Seq( 186 IRQ_MEIP, IRQ_MSIP, IRQ_MTIP, 187 IRQ_SEIP, IRQ_SSIP, IRQ_STIP, 188 IRQ_UEIP, IRQ_USIP, IRQ_UTIP 189 ) 190 191 def csrAccessPermissionCheck(addr: UInt, wen: Bool, mode: UInt): Bool = { 192 val readOnly = addr(11,10) === "b11".U 193 val lowestAccessPrivilegeLevel = addr(9,8) 194 mode >= lowestAccessPrivilegeLevel && !(wen && readOnly) 195 } 196 197 def perfcntPermissionCheck(addr: UInt, mode: UInt, mmask: UInt, smask: UInt): Bool = { 198 val index = UIntToOH(addr & 31.U) 199 Mux(mode === ModeM, true.B, Mux(mode === ModeS, (index & mmask) =/= 0.U, (index & mmask & smask) =/= 0.U)) 200 } 201} 202