1package xiangshan.mem 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils._ 7import xiangshan._ 8import xiangshan.backend.decode.ImmUnion 9import xiangshan.cache._ 10 11class LoadToLsqIO(implicit p: Parameters) extends XSBundle { 12 val loadIn = ValidIO(new LsPipelineBundle) 13 val ldout = Flipped(DecoupledIO(new ExuOutput)) 14 val loadDataForwarded = Output(Bool()) 15 val needReplayFromRS = Output(Bool()) 16 val forward = new MaskedLoadForwardQueryIO 17} 18 19// Load Pipeline Stage 0 20// Generate addr, use addr to query DCache and DTLB 21class LoadUnit_S0(implicit p: Parameters) extends XSModule { 22 val io = IO(new Bundle() { 23 val in = Flipped(Decoupled(new ExuInput)) 24 val out = Decoupled(new LsPipelineBundle) 25 val dtlbReq = DecoupledIO(new TlbReq) 26 val dcacheReq = DecoupledIO(new DCacheWordReq) 27 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 28 val isFirstIssue = Input(Bool()) 29 }) 30 31 val s0_uop = io.in.bits.uop 32 // val s0_vaddr = io.in.bits.src1 + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits) 33 // val s0_mask = genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0)) 34 val imm12 = WireInit(s0_uop.ctrl.imm(11,0)) 35 val s0_vaddr_lo = io.in.bits.src1(11,0) + Cat(0.U(1.W), imm12) 36 val s0_vaddr_hi = Mux(s0_vaddr_lo(12), 37 Mux(imm12(11), io.in.bits.src1(VAddrBits-1, 12), io.in.bits.src1(VAddrBits-1, 12)+1.U), 38 Mux(imm12(11), io.in.bits.src1(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src1(VAddrBits-1, 12)), 39 ) 40 val s0_vaddr = Cat(s0_vaddr_hi, s0_vaddr_lo(11,0)) 41 val s0_mask = genWmask(s0_vaddr_lo, s0_uop.ctrl.fuOpType(1,0)) 42 43 // query DTLB 44 io.dtlbReq.valid := io.in.valid 45 io.dtlbReq.bits.vaddr := s0_vaddr 46 io.dtlbReq.bits.cmd := TlbCmd.read 47 io.dtlbReq.bits.roqIdx := s0_uop.roqIdx 48 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 49 io.dtlbReq.bits.debug.isFirstIssue := io.isFirstIssue 50 51 // query DCache 52 io.dcacheReq.valid := io.in.valid 53 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 54 io.dcacheReq.bits.addr := s0_vaddr 55 io.dcacheReq.bits.mask := s0_mask 56 io.dcacheReq.bits.data := DontCare 57 58 // TODO: update cache meta 59 io.dcacheReq.bits.id := DontCare 60 61 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 62 "b00".U -> true.B, //b 63 "b01".U -> (s0_vaddr(0) === 0.U), //h 64 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 65 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 66 )) 67 68 io.out.valid := io.in.valid && io.dcacheReq.ready 69 70 io.out.bits := DontCare 71 io.out.bits.vaddr := s0_vaddr 72 io.out.bits.mask := s0_mask 73 io.out.bits.uop := s0_uop 74 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 75 io.out.bits.rsIdx := io.rsIdx 76 77 io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready) 78 79 XSDebug(io.dcacheReq.fire(), 80 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 81 ) 82 XSPerfAccumulate("in", io.in.valid) 83 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready && io.dcacheReq.ready) 84 XSPerfAccumulate("stall_dcache", io.out.valid && io.out.ready && !io.dcacheReq.ready) 85} 86 87 88// Load Pipeline Stage 1 89// TLB resp (send paddr to dcache) 90class LoadUnit_S1(implicit p: Parameters) extends XSModule { 91 val io = IO(new Bundle() { 92 val in = Flipped(Decoupled(new LsPipelineBundle)) 93 val out = Decoupled(new LsPipelineBundle) 94 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 95 val dcachePAddr = Output(UInt(PAddrBits.W)) 96 val dcacheKill = Output(Bool()) 97 val sbuffer = new LoadForwardQueryIO 98 val lsq = new MaskedLoadForwardQueryIO 99 }) 100 101 val s1_uop = io.in.bits.uop 102 val s1_paddr = io.dtlbResp.bits.paddr 103 val s1_exception = selectLoad(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 104 val s1_tlb_miss = io.dtlbResp.bits.miss 105 val s1_mmio = !s1_tlb_miss && io.dtlbResp.bits.mmio 106 val s1_mask = io.in.bits.mask 107 108 io.out.bits := io.in.bits // forwardXX field will be updated in s1 109 110 io.dtlbResp.ready := true.B 111 112 // TOOD: PMA check 113 io.dcachePAddr := s1_paddr 114 io.dcacheKill := s1_tlb_miss || s1_exception || s1_mmio 115 116 // load forward query datapath 117 io.sbuffer.valid := io.in.valid 118 io.sbuffer.paddr := s1_paddr 119 io.sbuffer.uop := s1_uop 120 io.sbuffer.sqIdx := s1_uop.sqIdx 121 io.sbuffer.mask := s1_mask 122 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 123 124 io.lsq.valid := io.in.valid 125 io.lsq.paddr := s1_paddr 126 io.lsq.uop := s1_uop 127 io.lsq.sqIdx := s1_uop.sqIdx 128 io.lsq.sqIdxMask := DontCare // will be overwritten by sqIdxMask pre-generated in s0 129 io.lsq.mask := s1_mask 130 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 131 132 io.out.valid := io.in.valid// && !s1_tlb_miss 133 io.out.bits.paddr := s1_paddr 134 io.out.bits.mmio := s1_mmio && !s1_exception 135 io.out.bits.tlbMiss := s1_tlb_miss 136 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 137 io.out.bits.uop.cf.exceptionVec(loadAccessFault) := io.dtlbResp.bits.excp.af.ld 138 io.out.bits.ptwBack := io.dtlbResp.bits.ptwBack 139 io.out.bits.rsIdx := io.in.bits.rsIdx 140 141 io.in.ready := !io.in.valid || io.out.ready 142 143 XSPerfAccumulate("in", io.in.valid) 144 XSPerfAccumulate("tlb_miss", io.in.valid && s1_tlb_miss) 145 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready) 146} 147 148 149// Load Pipeline Stage 2 150// DCache resp 151class LoadUnit_S2(implicit p: Parameters) extends XSModule with HasLoadHelper { 152 val io = IO(new Bundle() { 153 val in = Flipped(Decoupled(new LsPipelineBundle)) 154 val out = Decoupled(new LsPipelineBundle) 155 val tlbFeedback = ValidIO(new TlbFeedback) 156 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 157 val lsq = new LoadForwardQueryIO 158 val sbuffer = new LoadForwardQueryIO 159 val dataForwarded = Output(Bool()) 160 val needReplayFromRS = Output(Bool()) 161 }) 162 163 val s2_uop = io.in.bits.uop 164 val s2_mask = io.in.bits.mask 165 val s2_paddr = io.in.bits.paddr 166 val s2_tlb_miss = io.in.bits.tlbMiss 167 val s2_exception = selectLoad(io.in.bits.uop.cf.exceptionVec, false).asUInt.orR 168 val s2_mmio = io.in.bits.mmio && !s2_exception 169 val s2_cache_miss = io.dcacheResp.bits.miss 170 val s2_cache_replay = io.dcacheResp.bits.replay 171 172 io.dcacheResp.ready := true.B 173 val dcacheShouldResp = !(s2_tlb_miss || s2_exception || s2_mmio) 174 assert(!(io.in.valid && dcacheShouldResp && !io.dcacheResp.valid), "DCache response got lost") 175 176 // feedback tlb result to RS 177 io.tlbFeedback.valid := io.in.valid 178 io.tlbFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception) 179 io.tlbFeedback.bits.rsIdx := io.in.bits.rsIdx 180 io.tlbFeedback.bits.flushState := io.in.bits.ptwBack 181 io.needReplayFromRS := s2_cache_replay 182 183 // merge forward result 184 // lsq has higher priority than sbuffer 185 val forwardMask = Wire(Vec(8, Bool())) 186 val forwardData = Wire(Vec(8, UInt(8.W))) 187 188 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U 189 io.lsq := DontCare 190 io.sbuffer := DontCare 191 192 // generate XLEN/8 Muxs 193 for (i <- 0 until XLEN / 8) { 194 forwardMask(i) := io.lsq.forwardMask(i) || io.sbuffer.forwardMask(i) 195 forwardData(i) := Mux(io.lsq.forwardMask(i), io.lsq.forwardData(i), io.sbuffer.forwardData(i)) 196 } 197 198 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 199 s2_uop.cf.pc, 200 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 201 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 202 ) 203 204 // data merge 205 val rdataVec = VecInit((0 until XLEN / 8).map(j => 206 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))) 207 val rdata = rdataVec.asUInt 208 val rdataSel = LookupTree(s2_paddr(2, 0), List( 209 "b000".U -> rdata(63, 0), 210 "b001".U -> rdata(63, 8), 211 "b010".U -> rdata(63, 16), 212 "b011".U -> rdata(63, 24), 213 "b100".U -> rdata(63, 32), 214 "b101".U -> rdata(63, 40), 215 "b110".U -> rdata(63, 48), 216 "b111".U -> rdata(63, 56) 217 )) 218 val rdataPartialLoad = rdataHelper(s2_uop, rdataSel) 219 220 io.out.valid := io.in.valid && !s2_tlb_miss 221 // Inst will be canceled in store queue / lsq, 222 // so we do not need to care about flush in load / store unit's out.valid 223 io.out.bits := io.in.bits 224 io.out.bits.data := rdataPartialLoad 225 // when exception occurs, set it to not miss and let it write back to roq (via int port) 226 io.out.bits.miss := s2_cache_miss && !s2_exception 227 io.out.bits.uop.ctrl.fpWen := io.in.bits.uop.ctrl.fpWen && !s2_exception 228 io.out.bits.mmio := s2_mmio 229 230 // For timing reasons, we can not let 231 // io.out.bits.miss := s2_cache_miss && !s2_exception && !fullForward 232 // We use io.dataForwarded instead. It means forward logic have prepared all data needed, 233 // and dcache query is no longer needed. 234 // Such inst will be writebacked from load queue. 235 io.dataForwarded := s2_cache_miss && fullForward && !s2_exception 236 // io.out.bits.forwardX will be send to lq 237 io.out.bits.forwardMask := forwardMask 238 // data retbrived from dcache is also included in io.out.bits.forwardData 239 io.out.bits.forwardData := rdataVec 240 241 io.in.ready := io.out.ready || !io.in.valid 242 243 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 244 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 245 forwardData.asUInt, forwardMask.asUInt 246 ) 247 248 XSPerfAccumulate("in", io.in.valid) 249 XSPerfAccumulate("dcache_miss", io.in.valid && s2_cache_miss) 250 XSPerfAccumulate("full_forward", io.in.valid && fullForward) 251 XSPerfAccumulate("dcache_miss_full_forward", io.in.valid && s2_cache_miss && fullForward) 252 XSPerfAccumulate("replay", io.tlbFeedback.valid && !io.tlbFeedback.bits.hit) 253 XSPerfAccumulate("replay_tlb_miss", io.tlbFeedback.valid && !io.tlbFeedback.bits.hit && s2_tlb_miss) 254 XSPerfAccumulate("replay_cache", io.tlbFeedback.valid && !io.tlbFeedback.bits.hit && !s2_tlb_miss && s2_cache_replay) 255 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready) 256} 257 258class LoadUnit(implicit p: Parameters) extends XSModule with HasLoadHelper { 259 val io = IO(new Bundle() { 260 val ldin = Flipped(Decoupled(new ExuInput)) 261 val ldout = Decoupled(new ExuOutput) 262 val redirect = Flipped(ValidIO(new Redirect)) 263 val flush = Input(Bool()) 264 val tlbFeedback = ValidIO(new TlbFeedback) 265 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 266 val isFirstIssue = Input(Bool()) 267 val dcache = new DCacheLoadIO 268 val dtlb = new TlbRequestIO() 269 val sbuffer = new LoadForwardQueryIO 270 val lsq = new LoadToLsqIO 271 val fastUop = ValidIO(new MicroOp) // early wakup signal generated in load_s1 272 }) 273 274 val load_s0 = Module(new LoadUnit_S0) 275 val load_s1 = Module(new LoadUnit_S1) 276 val load_s2 = Module(new LoadUnit_S2) 277 278 load_s0.io.in <> io.ldin 279 load_s0.io.dtlbReq <> io.dtlb.req 280 load_s0.io.dcacheReq <> io.dcache.req 281 load_s0.io.rsIdx := io.rsIdx 282 load_s0.io.isFirstIssue := io.isFirstIssue 283 284 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 285 286 load_s1.io.dtlbResp <> io.dtlb.resp 287 io.dcache.s1_paddr <> load_s1.io.dcachePAddr 288 io.dcache.s1_kill <> load_s1.io.dcacheKill 289 load_s1.io.sbuffer <> io.sbuffer 290 load_s1.io.lsq <> io.lsq.forward 291 292 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, load_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 293 294 load_s2.io.dcacheResp <> io.dcache.resp 295 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 296 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 297 load_s2.io.sbuffer.forwardData <> io.sbuffer.forwardData 298 load_s2.io.sbuffer.forwardMask <> io.sbuffer.forwardMask 299 load_s2.io.dataForwarded <> io.lsq.loadDataForwarded 300 io.tlbFeedback.bits := RegNext(load_s2.io.tlbFeedback.bits) 301 io.tlbFeedback.valid := RegNext(load_s2.io.tlbFeedback.valid && !load_s2.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 302 io.lsq.needReplayFromRS := load_s2.io.needReplayFromRS 303 304 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 305 val sqIdxMaskReg = RegNext(UIntToMask(load_s0.io.in.bits.uop.sqIdx.value, StoreQueueSize)) 306 io.lsq.forward.sqIdxMask := sqIdxMaskReg 307 308 // // use s2_hit_way to select data received in s1 309 // load_s2.io.dcacheResp.bits.data := Mux1H(RegNext(io.dcache.s1_hit_way), RegNext(io.dcache.s1_data)) 310 // assert(load_s2.io.dcacheResp.bits.data === io.dcache.resp.bits.data) 311 312 io.fastUop.valid := io.dcache.s1_hit_way.orR && !io.dcache.s1_disable_fast_wakeup && load_s1.io.in.valid 313 io.fastUop.bits := load_s1.io.out.bits.uop 314 315 XSDebug(load_s0.io.out.valid, 316 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 317 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 318 XSDebug(load_s1.io.out.valid, 319 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 320 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 321 322 // writeback to LSQ 323 // Current dcache use MSHR 324 // Load queue will be updated at s2 for both hit/miss int/fp load 325 io.lsq.loadIn.valid := load_s2.io.out.valid 326 io.lsq.loadIn.bits := load_s2.io.out.bits 327 328 // write to rob and writeback bus 329 val s2_wb_valid = load_s2.io.out.valid && !load_s2.io.out.bits.miss 330 331 // Int load, if hit, will be writebacked at s2 332 val hitLoadOut = Wire(Valid(new ExuOutput)) 333 hitLoadOut.valid := s2_wb_valid 334 hitLoadOut.bits.uop := load_s2.io.out.bits.uop 335 hitLoadOut.bits.data := load_s2.io.out.bits.data 336 hitLoadOut.bits.redirectValid := false.B 337 hitLoadOut.bits.redirect := DontCare 338 hitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 339 hitLoadOut.bits.debug.isPerfCnt := false.B 340 hitLoadOut.bits.debug.paddr := load_s2.io.out.bits.paddr 341 hitLoadOut.bits.fflags := DontCare 342 343 load_s2.io.out.ready := true.B 344 345 io.ldout.bits := Mux(hitLoadOut.valid, hitLoadOut.bits, io.lsq.ldout.bits) 346 io.ldout.valid := hitLoadOut.valid || io.lsq.ldout.valid 347 348 io.lsq.ldout.ready := !hitLoadOut.valid 349 350 when(io.ldout.fire()){ 351 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 352 } 353} 354