1package xiangshan.backend.rename 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan._ 7import utils._ 8import xiangshan.backend.roq.RoqPtr 9import xiangshan.backend.dispatch.PreDispatchInfo 10 11class RenameBypassInfo(implicit p: Parameters) extends XSBundle { 12 val lsrc1_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 13 val lsrc2_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 14 val lsrc3_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 15 val ldest_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 16 val move_eliminated_src1 = Vec(RenameWidth-1, Bool()) 17 val move_eliminated_src2 = Vec(RenameWidth-1, Bool()) 18} 19 20class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper { 21 val io = IO(new Bundle() { 22 val redirect = Flipped(ValidIO(new Redirect)) 23 val flush = Input(Bool()) 24 val roqCommits = Flipped(new RoqCommitIO) 25 // from decode buffer 26 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 27 // to dispatch1 28 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 29 val renameBypass = Output(new RenameBypassInfo) 30 val dispatchInfo = Output(new PreDispatchInfo) 31 val csrCtrl = Flipped(new CustomCSRCtrlIO) 32 val debug_int_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 33 val debug_fp_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 34 }) 35 36 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 37 XSInfo( 38 in.valid && in.ready, 39 p"pc:${Hexadecimal(in.bits.cf.pc)} in v:${in.valid} in rdy:${in.ready} " + 40 p"lsrc1:${in.bits.ctrl.lsrc1} -> psrc1:${out.bits.psrc1} " + 41 p"lsrc2:${in.bits.ctrl.lsrc2} -> psrc2:${out.bits.psrc2} " + 42 p"lsrc3:${in.bits.ctrl.lsrc3} -> psrc3:${out.bits.psrc3} " + 43 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 44 p"old_pdest:${out.bits.old_pdest} " + 45 p"out v:${out.valid} r:${out.ready}\n" 46 ) 47 } 48 49 for((x,y) <- io.in.zip(io.out)){ 50 printRenameInfo(x, y) 51 } 52 53 val intFreeList, fpFreeList = Module(new FreeList).io 54 val intRat = Module(new RenameTable(float = false)).io 55 val fpRat = Module(new RenameTable(float = true)).io 56 val allPhyResource = Seq((intRat, intFreeList, false), (fpRat, fpFreeList, true)) 57 intRat.debug_rdata <> io.debug_int_rat 58 fpRat.debug_rdata <> io.debug_fp_rat 59 60 allPhyResource.map{ case (rat, freelist, _) => 61 rat.redirect := io.redirect.valid 62 rat.flush := io.flush 63 rat.walkWen := io.roqCommits.isWalk 64 freelist.redirect := io.redirect.valid 65 freelist.flush := io.flush 66 freelist.walk.valid := io.roqCommits.isWalk 67 } 68 val canOut = io.out(0).ready && fpFreeList.req.canAlloc && intFreeList.req.canAlloc && !io.roqCommits.isWalk 69 70 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 71 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 72 } 73 def needDestRegCommit[T <: RoqCommitInfo](fp: Boolean, x: T): Bool = { 74 {if(fp) x.fpWen else x.rfWen && (x.ldest =/= 0.U)} 75 } 76 fpFreeList.walk.bits := PopCount(io.roqCommits.valid.zip(io.roqCommits.info).map{case (v, i) => v && needDestRegCommit(true, i)}) 77 intFreeList.walk.bits := PopCount(io.roqCommits.valid.zip(io.roqCommits.info).map{case (v, i) => v && needDestRegCommit(false, i)}) 78 // walk has higher priority than allocation and thus we don't use isWalk here 79 fpFreeList.req.doAlloc := intFreeList.req.canAlloc && io.out(0).ready 80 intFreeList.req.doAlloc := fpFreeList.req.canAlloc && io.out(0).ready 81 82 // speculatively assign the instruction with an roqIdx 83 val validCount = PopCount(io.in.map(_.valid)) 84 val roqIdxHead = RegInit(0.U.asTypeOf(new RoqPtr)) 85 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 86 val roqIdxHeadNext = Mux(io.flush, 87 0.U.asTypeOf(new RoqPtr), 88 Mux(io.redirect.valid, 89 io.redirect.bits.roqIdx, 90 Mux(lastCycleMisprediction, 91 roqIdxHead + 1.U, 92 Mux(canOut, roqIdxHead + validCount, roqIdxHead)) 93 ) 94 ) 95 roqIdxHead := roqIdxHeadNext 96 97 /** 98 * Rename: allocate free physical register and update rename table 99 */ 100 val uops = Wire(Vec(RenameWidth, new MicroOp)) 101 102 uops.foreach( uop => { 103// uop.brMask := DontCare 104// uop.brTag := DontCare 105 uop.src1State := DontCare 106 uop.src2State := DontCare 107 uop.src3State := DontCare 108 uop.roqIdx := DontCare 109 uop.diffTestDebugLrScValid := DontCare 110 uop.debugInfo := DontCare 111 uop.lqIdx := DontCare 112 uop.sqIdx := DontCare 113 }) 114 115 val needFpDest = Wire(Vec(RenameWidth, Bool())) 116 val needIntDest = Wire(Vec(RenameWidth, Bool())) 117 val hasValid = Cat(io.in.map(_.valid)).orR 118 for (i <- 0 until RenameWidth) { 119 uops(i).cf := io.in(i).bits.cf 120 uops(i).ctrl := io.in(i).bits.ctrl 121 122 val inValid = io.in(i).valid 123 124 // alloc a new phy reg 125 needFpDest(i) := inValid && needDestReg(fp = true, io.in(i).bits) 126 needIntDest(i) := inValid && needDestReg(fp = false, io.in(i).bits) 127 fpFreeList.req.allocReqs(i) := needFpDest(i) 128 intFreeList.req.allocReqs(i) := needIntDest(i) 129 130 io.in(i).ready := !hasValid || canOut 131 132 // do checkpoints when a branch inst come 133 // for(fl <- Seq(fpFreeList, intFreeList)){ 134 // fl.cpReqs(i).valid := inValid 135 // fl.cpReqs(i).bits := io.in(i).bits.brTag 136 // } 137 138 uops(i).pdest := Mux(needIntDest(i), 139 intFreeList.req.pdests(i), 140 Mux( 141 uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen, 142 0.U, fpFreeList.req.pdests(i) 143 ) 144 ) 145 146 uops(i).roqIdx := roqIdxHead + i.U 147 148 io.out(i).valid := io.in(i).valid && intFreeList.req.canAlloc && fpFreeList.req.canAlloc && !io.roqCommits.isWalk 149 io.out(i).bits := uops(i) 150 151 // write speculative rename table 152 allPhyResource.map{ case (rat, freelist, _) => 153 val specWen = freelist.req.allocReqs(i) && freelist.req.canAlloc && freelist.req.doAlloc && !io.roqCommits.isWalk 154 155 rat.specWritePorts(i).wen := specWen 156 rat.specWritePorts(i).addr := uops(i).ctrl.ldest 157 rat.specWritePorts(i).wdata := freelist.req.pdests(i) 158 159 freelist.deallocReqs(i) := specWen 160 } 161 162 // read rename table 163 def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = { 164 val rat = if(fp) fpRat else intRat 165 val srcCnt = lsrcList.size 166 val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W))) 167 val old_pdest = Wire(UInt(PhyRegIdxWidth.W)) 168 for(k <- 0 until srcCnt+1){ 169 val rportIdx = i * (srcCnt+1) + k 170 if(k != srcCnt){ 171 rat.readPorts(rportIdx).addr := lsrcList(k) 172 psrcVec(k) := rat.readPorts(rportIdx).rdata 173 } else { 174 rat.readPorts(rportIdx).addr := ldest 175 old_pdest := rat.readPorts(rportIdx).rdata 176 } 177 } 178 (psrcVec, old_pdest) 179 } 180 val lsrcList = List(uops(i).ctrl.lsrc1, uops(i).ctrl.lsrc2, uops(i).ctrl.lsrc3) 181 val ldest = uops(i).ctrl.ldest 182 val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false) 183 val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true) 184 uops(i).psrc1 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 185 uops(i).psrc2 := Mux(uops(i).ctrl.src2Type === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 186 uops(i).psrc3 := fpPhySrcVec(2) 187 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 188 } 189 190 // We don't bypass the old_pdest from valid instructions with the same ldest currently in rename stage. 191 // Instead, we determine whether there're some dependences between the valid instructions. 192 for (i <- 1 until RenameWidth) { 193 io.renameBypass.lsrc1_bypass(i-1) := Cat((0 until i).map(j => { 194 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src1Type === SrcType.fp 195 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src1Type === SrcType.reg 196 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc1 197 }).reverse) 198 io.renameBypass.lsrc2_bypass(i-1) := Cat((0 until i).map(j => { 199 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src2Type === SrcType.fp 200 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src2Type === SrcType.reg 201 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc2 202 }).reverse) 203 io.renameBypass.lsrc3_bypass(i-1) := Cat((0 until i).map(j => { 204 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src3Type === SrcType.fp 205 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src3Type === SrcType.reg 206 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc3 207 }).reverse) 208 io.renameBypass.ldest_bypass(i-1) := Cat((0 until i).map(j => { 209 val fpMatch = needFpDest(j) && needFpDest(i) 210 val intMatch = needIntDest(j) && needIntDest(i) 211 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.ldest 212 }).reverse) 213 io.renameBypass.move_eliminated_src1(i-1) := 214 // the producer move instruction writes to non-zero register 215 io.in(i-1).bits.ctrl.isMove && io.in(i-1).bits.ctrl.ldest =/= 0.U && 216 // the consumer instruction uses the move's destination register 217 io.in(i).bits.ctrl.src1Type === SrcType.reg && io.in(i).bits.ctrl.lsrc1 === io.in(i-1).bits.ctrl.ldest && 218 // CSR control (by srnctl) 219 io.csrCtrl.move_elim_enable 220 io.renameBypass.move_eliminated_src2(i-1) := 221 // the producer move instruction writes to non-zero register 222 io.in(i-1).bits.ctrl.isMove && io.in(i-1).bits.ctrl.ldest =/= 0.U && 223 // the consumer instruction uses the move's destination register 224 io.in(i).bits.ctrl.src2Type === SrcType.reg && io.in(i).bits.ctrl.lsrc2 === io.in(i-1).bits.ctrl.ldest && 225 // CSR control (by srnctl) 226 io.csrCtrl.move_elim_enable 227 } 228 229 val isLs = VecInit(uops.map(uop => FuType.isLoadStore(uop.ctrl.fuType))) 230 val isStore = VecInit(uops.map(uop => FuType.isStoreExu(uop.ctrl.fuType))) 231 val isAMO = VecInit(uops.map(uop => FuType.isAMO(uop.ctrl.fuType))) 232 io.dispatchInfo.lsqNeedAlloc := VecInit((0 until RenameWidth).map(i => 233 Mux(isLs(i), Mux(isStore(i) && !isAMO(i), 2.U, 1.U), 0.U))) 234 235 /** 236 * Instructions commit: update freelist and rename table 237 */ 238 for (i <- 0 until CommitWidth) { 239 if (i >= RenameWidth) { 240 allPhyResource.map{ case (rat, _, _) => 241 rat.specWritePorts(i).wen := false.B 242 rat.specWritePorts(i).addr := DontCare 243 rat.specWritePorts(i).wdata := DontCare 244 } 245 } 246 247 allPhyResource.map{ case (rat, freelist, fp) => 248 // walk back write 249 val commitDestValid = io.roqCommits.valid(i) && needDestRegCommit(fp, io.roqCommits.info(i)) 250 251 when (commitDestValid && io.roqCommits.isWalk) { 252 rat.specWritePorts(i).wen := true.B 253 rat.specWritePorts(i).addr := io.roqCommits.info(i).ldest 254 rat.specWritePorts(i).wdata := io.roqCommits.info(i).old_pdest 255 XSInfo({if(fp) p"fp" else p"int "} + p"walk: " + 256 p" ldest:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n") 257 } 258 259 rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits.isWalk 260 rat.archWritePorts(i).addr := io.roqCommits.info(i).ldest 261 rat.archWritePorts(i).wdata := io.roqCommits.info(i).pdest 262 263 XSInfo(rat.archWritePorts(i).wen, 264 {if(fp) p"fp" else p"int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" + 265 p" pdest:${rat.archWritePorts(i).wdata}\n" 266 ) 267 268 freelist.deallocReqs(i) := rat.archWritePorts(i).wen 269 freelist.deallocPregs(i) := io.roqCommits.info(i).old_pdest 270 } 271 } 272 273 XSPerfAccumulate("in", Mux(RegNext(io.in(0).ready), PopCount(io.in.map(_.valid)), 0.U)) 274 XSPerfAccumulate("utilization", PopCount(io.in.map(_.valid))) 275 XSPerfAccumulate("waitInstr", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready))) 276 XSPerfAccumulate("stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.req.canAlloc && intFreeList.req.canAlloc && !io.roqCommits.isWalk) 277 XSPerfAccumulate("stall_cycle_fp", hasValid && io.out(0).ready && !fpFreeList.req.canAlloc && intFreeList.req.canAlloc && !io.roqCommits.isWalk) 278 XSPerfAccumulate("stall_cycle_int", hasValid && io.out(0).ready && fpFreeList.req.canAlloc && !intFreeList.req.canAlloc && !io.roqCommits.isWalk) 279 XSPerfAccumulate("stall_cycle_walk", hasValid && io.out(0).ready && fpFreeList.req.canAlloc && intFreeList.req.canAlloc && io.roqCommits.isWalk) 280 281 282} 283