1package xiangshan.backend.decode 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.rocket.DecodeLogic 7import xiangshan.backend.decode.Instructions._ 8import xiangshan.{FPUCtrlSignals, XSModule} 9 10class FPDecoder(implicit p: Parameters) extends XSModule{ 11 val io = IO(new Bundle() { 12 val instr = Input(UInt(32.W)) 13 val fpCtrl = Output(new FPUCtrlSignals) 14 }) 15 16 def X = BitPat("b?") 17 def N = BitPat("b0") 18 def Y = BitPat("b1") 19 val s = BitPat(S) 20 val d = BitPat(D) 21 val i = BitPat(I) 22 23 val default = List(X,X,X,N,N,N,X,X,X) 24 25 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 26 val single: Array[(BitPat, List[BitPat])] = Array( 27 FMV_W_X -> List(N,s,d,Y,N,Y,N,N,N), 28 FCVT_S_W -> List(N,s,s,Y,Y,Y,N,N,Y), 29 FCVT_S_WU-> List(N,s,s,Y,Y,Y,N,N,Y), 30 FCVT_S_L -> List(N,s,s,Y,Y,Y,N,N,Y), 31 FCVT_S_LU-> List(N,s,s,Y,Y,Y,N,N,Y), 32 FMV_X_W -> List(N,d,i,N,N,N,N,N,N), 33 FCLASS_S -> List(N,s,i,N,N,N,N,N,N), 34 FCVT_W_S -> List(N,s,i,N,Y,N,N,N,Y), 35 FCVT_WU_S-> List(N,s,i,N,Y,N,N,N,Y), 36 FCVT_L_S -> List(N,s,i,N,Y,N,N,N,Y), 37 FCVT_LU_S-> List(N,s,i,N,Y,N,N,N,Y), 38 FEQ_S -> List(N,s,i,N,Y,N,N,N,N), 39 FLT_S -> List(N,s,i,N,Y,N,N,N,N), 40 FLE_S -> List(N,s,i,N,Y,N,N,N,N), 41 FSGNJ_S -> List(N,s,s,N,N,Y,N,N,N), 42 FSGNJN_S -> List(N,s,s,N,N,Y,N,N,N), 43 FSGNJX_S -> List(N,s,s,N,N,Y,N,N,N), 44 FMIN_S -> List(N,s,s,N,Y,Y,N,N,N), 45 FMAX_S -> List(N,s,s,N,Y,Y,N,N,N), 46 FADD_S -> List(Y,s,s,N,Y,Y,N,N,N), 47 FSUB_S -> List(Y,s,s,N,Y,Y,N,N,N), 48 FMUL_S -> List(N,s,s,N,Y,Y,N,N,N), 49 FMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 50 FMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 51 FNMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 52 FNMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 53 FDIV_S -> List(N,s,s,N,Y,Y,Y,N,N), 54 FSQRT_S -> List(N,s,s,N,Y,Y,N,Y,N) 55 ) 56 57 58 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 59 val double: Array[(BitPat, List[BitPat])] = Array( 60 FMV_D_X -> List(N,d,d,Y,N,Y,N,N,N), 61 FCVT_D_W -> List(N,d,d,Y,Y,Y,N,N,Y), 62 FCVT_D_WU-> List(N,d,d,Y,Y,Y,N,N,Y), 63 FCVT_D_L -> List(N,d,d,Y,Y,Y,N,N,Y), 64 FCVT_D_LU-> List(N,d,d,Y,Y,Y,N,N,Y), 65 FMV_X_D -> List(N,d,i,N,N,N,N,N,N), 66 FCLASS_D -> List(N,d,i,N,N,N,N,N,N), 67 FCVT_W_D -> List(N,d,i,N,Y,N,N,N,Y), 68 FCVT_WU_D-> List(N,d,i,N,Y,N,N,N,Y), 69 FCVT_L_D -> List(N,d,i,N,Y,N,N,N,Y), 70 FCVT_LU_D-> List(N,d,i,N,Y,N,N,N,Y), 71 FCVT_S_D -> List(N,d,s,N,Y,Y,N,N,Y), 72 FCVT_D_S -> List(N,s,d,N,Y,Y,N,N,Y), 73 FEQ_D -> List(N,d,i,N,Y,N,N,N,N), 74 FLT_D -> List(N,d,i,N,Y,N,N,N,N), 75 FLE_D -> List(N,d,i,N,Y,N,N,N,N), 76 FSGNJ_D -> List(N,d,d,N,N,Y,N,N,N), 77 FSGNJN_D -> List(N,d,d,N,N,Y,N,N,N), 78 FSGNJX_D -> List(N,d,d,N,N,Y,N,N,N), 79 FMIN_D -> List(N,d,d,N,Y,Y,N,N,N), 80 FMAX_D -> List(N,d,d,N,Y,Y,N,N,N), 81 FADD_D -> List(Y,d,d,N,Y,Y,N,N,N), 82 FSUB_D -> List(Y,d,d,N,Y,Y,N,N,N), 83 FMUL_D -> List(N,d,d,N,Y,Y,N,N,N), 84 FMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 85 FMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 86 FNMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 87 FNMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 88 FDIV_D -> List(N,d,d,N,Y,Y,Y,N,N), 89 FSQRT_D -> List(N,d,d,N,Y,Y,N,Y,N) 90 ) 91 92 val table = single ++ double 93 94 val decoder = DecodeLogic(io.instr, default, table) 95 96 val ctrl = io.fpCtrl 97 val sigs = Seq( 98 ctrl.isAddSub, ctrl.typeTagIn, ctrl.typeTagOut, 99 ctrl.fromInt, ctrl.wflags, ctrl.fpWen, 100 ctrl.div, ctrl.sqrt, ctrl.fcvt 101 ) 102 sigs.zip(decoder).foreach({case (s, d) => s := d}) 103 ctrl.typ := io.instr(21, 20) 104 ctrl.fmt := io.instr(26, 25) 105 ctrl.rm := io.instr(14, 12) 106 107 val fmaTable: Array[(BitPat, List[BitPat])] = Array( 108 FADD_S -> List(BitPat("b00"),N), 109 FADD_D -> List(BitPat("b00"),N), 110 FSUB_S -> List(BitPat("b01"),N), 111 FSUB_D -> List(BitPat("b01"),N), 112 FMUL_S -> List(BitPat("b00"),N), 113 FMUL_D -> List(BitPat("b00"),N), 114 FMADD_S -> List(BitPat("b00"),Y), 115 FMADD_D -> List(BitPat("b00"),Y), 116 FMSUB_S -> List(BitPat("b01"),Y), 117 FMSUB_D -> List(BitPat("b01"),Y), 118 FNMADD_S-> List(BitPat("b11"),Y), 119 FNMADD_D-> List(BitPat("b11"),Y), 120 FNMSUB_S-> List(BitPat("b10"),Y), 121 FNMSUB_D-> List(BitPat("b10"),Y) 122 ) 123 val fmaDefault = List(BitPat("b??"), N) 124 Seq(ctrl.fmaCmd, ctrl.ren3).zip( 125 DecodeLogic(io.instr, fmaDefault, fmaTable) 126 ).foreach({ 127 case (s, d) => s := d 128 }) 129} 130