1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.backend.exu.Exu._ 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.backend.fu.HasExceptionNO 13import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, PTWRepeater} 14import xiangshan.cache.prefetch._ 15import chipsalliance.rocketchip.config 16import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 17import freechips.rocketchip.tile.HasFPUParameters 18import system.L1CacheErrorInfo 19import utils._ 20 21object hartIdCore extends (() => Int) { 22 var x = 0 23 24 def apply(): Int = { 25 x = x + 1 26 x - 1 27 } 28} 29 30case class XSCoreParameters 31( 32 XLEN: Int = 64, 33 HasMExtension: Boolean = true, 34 HasCExtension: Boolean = true, 35 HasDiv: Boolean = true, 36 HasICache: Boolean = true, 37 HasDCache: Boolean = true, 38 EnableStoreQueue: Boolean = true, 39 AddrBits: Int = 64, 40 VAddrBits: Int = 39, 41 PAddrBits: Int = 40, 42 HasFPU: Boolean = true, 43 FetchWidth: Int = 8, 44 EnableBPU: Boolean = true, 45 EnableBPD: Boolean = true, 46 EnableRAS: Boolean = true, 47 EnableLB: Boolean = false, 48 EnableLoop: Boolean = true, 49 EnableSC: Boolean = true, 50 EnbaleTlbDebug: Boolean = false, 51 EnableJal: Boolean = false, 52 EnableUBTB: Boolean = true, 53 HistoryLength: Int = 64, 54 BtbSize: Int = 2048, 55 JbtacSize: Int = 1024, 56 JbtacBanks: Int = 8, 57 RasSize: Int = 16, 58 CacheLineSize: Int = 512, 59 UBtbWays: Int = 16, 60 BtbWays: Int = 2, 61 62 EnableL1plusPrefetcher: Boolean = true, 63 IBufSize: Int = 48, 64 DecodeWidth: Int = 6, 65 RenameWidth: Int = 6, 66 CommitWidth: Int = 6, 67 BrqSize: Int = 32, 68 FtqSize: Int = 48, 69 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 70 IssQueSize: Int = 16, 71 NRPhyRegs: Int = 160, 72 NRIntReadPorts: Int = 14, 73 NRIntWritePorts: Int = 8, 74 NRFpReadPorts: Int = 14, 75 NRFpWritePorts: Int = 8, 76 LoadQueueSize: Int = 64, 77 StoreQueueSize: Int = 48, 78 RoqSize: Int = 192, 79 dpParams: DispatchParameters = DispatchParameters( 80 IntDqSize = 16, 81 FpDqSize = 16, 82 LsDqSize = 16, 83 IntDqDeqWidth = 4, 84 FpDqDeqWidth = 4, 85 LsDqDeqWidth = 4 86 ), 87 exuParameters: ExuParameters = ExuParameters( 88 JmpCnt = 1, 89 AluCnt = 4, 90 MulCnt = 0, 91 MduCnt = 2, 92 FmacCnt = 4, 93 FmiscCnt = 2, 94 FmiscDivSqrtCnt = 0, 95 LduCnt = 2, 96 StuCnt = 2 97 ), 98 LoadPipelineWidth: Int = 2, 99 StorePipelineWidth: Int = 2, 100 StoreBufferSize: Int = 16, 101 RefillSize: Int = 512, 102 TlbEntrySize: Int = 32, 103 TlbSPEntrySize: Int = 4, 104 PtwL3EntrySize: Int = 4096, //(256 * 16) or 512 105 PtwSPEntrySize: Int = 16, 106 PtwL1EntrySize: Int = 16, 107 PtwL2EntrySize: Int = 2048, //(256 * 8) 108 NumPerfCounters: Int = 16, 109 NrExtIntr: Int = 150 110) 111 112trait HasXSParameter { 113 114 val coreParams = Parameters.get.coreParameters 115 val env = Parameters.get.envParameters 116 117 val XLEN = 64 118 val minFLen = 32 119 val fLen = 64 120 121 def xLen = 64 122 123 val HasMExtension = coreParams.HasMExtension 124 val HasCExtension = coreParams.HasCExtension 125 val HasDiv = coreParams.HasDiv 126 val HasIcache = coreParams.HasICache 127 val HasDcache = coreParams.HasDCache 128 val EnableStoreQueue = coreParams.EnableStoreQueue 129 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 130 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 131 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 132 val AddrBytes = AddrBits / 8 // unused 133 val DataBits = XLEN 134 val DataBytes = DataBits / 8 135 val HasFPU = coreParams.HasFPU 136 val FetchWidth = coreParams.FetchWidth 137 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 138 val EnableBPU = coreParams.EnableBPU 139 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 140 val EnableRAS = coreParams.EnableRAS 141 val EnableLB = coreParams.EnableLB 142 val EnableLoop = coreParams.EnableLoop 143 val EnableSC = coreParams.EnableSC 144 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 145 val HistoryLength = coreParams.HistoryLength 146 val BtbSize = coreParams.BtbSize 147 // val BtbWays = 4 148 val BtbBanks = PredictWidth 149 // val BtbSets = BtbSize / BtbWays 150 val JbtacSize = coreParams.JbtacSize 151 val JbtacBanks = coreParams.JbtacBanks 152 val RasSize = coreParams.RasSize 153 val CacheLineSize = coreParams.CacheLineSize 154 val CacheLineHalfWord = CacheLineSize / 16 155 val ExtHistoryLength = HistoryLength + 64 156 val UBtbWays = coreParams.UBtbWays 157 val BtbWays = coreParams.BtbWays 158 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 159 val IBufSize = coreParams.IBufSize 160 val DecodeWidth = coreParams.DecodeWidth 161 val RenameWidth = coreParams.RenameWidth 162 val CommitWidth = coreParams.CommitWidth 163 val BrqSize = coreParams.BrqSize 164 val FtqSize = coreParams.FtqSize 165 val IssQueSize = coreParams.IssQueSize 166 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 167 val BrTagWidth = log2Up(BrqSize) 168 val NRPhyRegs = coreParams.NRPhyRegs 169 val PhyRegIdxWidth = log2Up(NRPhyRegs) 170 val RoqSize = coreParams.RoqSize 171 val LoadQueueSize = coreParams.LoadQueueSize 172 val StoreQueueSize = coreParams.StoreQueueSize 173 val dpParams = coreParams.dpParams 174 val exuParameters = coreParams.exuParameters 175 val NRIntReadPorts = coreParams.NRIntReadPorts 176 val NRIntWritePorts = coreParams.NRIntWritePorts 177 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 178 val NRFpReadPorts = coreParams.NRFpReadPorts 179 val NRFpWritePorts = coreParams.NRFpWritePorts 180 val LoadPipelineWidth = coreParams.LoadPipelineWidth 181 val StorePipelineWidth = coreParams.StorePipelineWidth 182 val StoreBufferSize = coreParams.StoreBufferSize 183 val RefillSize = coreParams.RefillSize 184 val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 185 val TlbEntrySize = coreParams.TlbEntrySize 186 val TlbSPEntrySize = coreParams.TlbSPEntrySize 187 val PtwL3EntrySize = coreParams.PtwL3EntrySize 188 val PtwSPEntrySize = coreParams.PtwSPEntrySize 189 val PtwL1EntrySize = coreParams.PtwL1EntrySize 190 val PtwL2EntrySize = coreParams.PtwL2EntrySize 191 val NumPerfCounters = coreParams.NumPerfCounters 192 val NrExtIntr = coreParams.NrExtIntr 193 194 val instBytes = if (HasCExtension) 2 else 4 195 val instOffsetBits = log2Ceil(instBytes) 196 197 val icacheParameters = ICacheParameters( 198 tagECC = Some("parity"), 199 dataECC = Some("parity"), 200 replacer = Some("setplru"), 201 nMissEntries = 2 202 ) 203 204 val l1plusCacheParameters = L1plusCacheParameters( 205 tagECC = Some("secded"), 206 dataECC = Some("secded"), 207 replacer = Some("setplru"), 208 nMissEntries = 8 209 ) 210 211 val dcacheParameters = DCacheParameters( 212 tagECC = Some("secded"), 213 dataECC = Some("secded"), 214 replacer = Some("setplru"), 215 nMissEntries = 16, 216 nProbeEntries = 16, 217 nReleaseEntries = 16, 218 nStoreReplayEntries = 16 219 ) 220 221 val LRSCCycles = 100 222 223 224 // cache hierarchy configurations 225 val l1BusDataWidth = 256 226 227 // L2 configurations 228 val L1BusWidth = 256 229 val L2Size = 512 * 1024 // 512KB 230 val L2BlockSize = 64 231 val L2NWays = 8 232 val L2NSets = L2Size / L2BlockSize / L2NWays 233 234 // L3 configurations 235 val L2BusWidth = 256 236 val L3Size = 4 * 1024 * 1024 // 4MB 237 val L3BlockSize = 64 238 val L3NBanks = 4 239 val L3NWays = 8 240 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 241 242 // on chip network configurations 243 val L3BusWidth = 256 244 245 // icache prefetcher 246 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 247 enable = true, 248 _type = "stream", 249 streamParams = StreamPrefetchParameters( 250 streamCnt = 2, 251 streamSize = 4, 252 ageWidth = 4, 253 blockBytes = l1plusCacheParameters.blockBytes, 254 reallocStreamOnMissInstantly = true, 255 cacheName = "icache" 256 ) 257 ) 258 259 // dcache prefetcher 260 val l2PrefetcherParameters = L2PrefetcherParameters( 261 enable = true, 262 _type = "bop", // "stream" or "bop" 263 streamParams = StreamPrefetchParameters( 264 streamCnt = 4, 265 streamSize = 4, 266 ageWidth = 4, 267 blockBytes = L2BlockSize, 268 reallocStreamOnMissInstantly = true, 269 cacheName = "dcache" 270 ), 271 bopParams = BOPParameters( 272 rrTableEntries = 256, 273 rrTagBits = 12, 274 scoreBits = 5, 275 roundMax = 50, 276 badScore = 1, 277 blockBytes = L2BlockSize, 278 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 279 ), 280 ) 281} 282 283abstract class XSModule extends MultiIOModule 284 with HasXSParameter 285 with HasExceptionNO 286 with HasFPUParameters { 287 def io: Record 288} 289 290//remove this trait after impl module logic 291trait NeedImpl { 292 this: RawModule => 293 override protected def IO[T <: Data](iodef: T): T = { 294 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 295 val io = chisel3.experimental.IO(iodef) 296 io <> DontCare 297 io 298 } 299} 300 301abstract class XSBundle extends Bundle 302 with HasXSParameter 303 304case class EnviromentParameters 305( 306 FPGAPlatform: Boolean = true, 307 EnableDebug: Boolean = false, 308 EnablePerfDebug: Boolean = true, 309 DualCore: Boolean = false 310) 311 312class XSCore()(implicit p: config.Parameters) extends LazyModule 313 with HasXSParameter 314 with HasExeBlockHelper { 315 // outer facing nodes 316 val frontend = LazyModule(new Frontend()) 317 val l1pluscache = LazyModule(new L1plusCache()) 318 val ptw = LazyModule(new PTW()) 319 val memBlock = LazyModule(new MemBlock( 320 fastWakeUpIn = intExuConfigs.filter(_.hasCertainLatency), 321 slowWakeUpIn = intExuConfigs.filter(_.hasUncertainlatency) ++ fpExuConfigs, 322 fastWakeUpOut = Seq(), 323 slowWakeUpOut = loadExuConfigs, 324 numIntWakeUpFp = intExuConfigs.count(_.writeFpRf) 325 )) 326 327 lazy val module = new XSCoreImp(this) 328} 329 330class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) 331 with HasXSParameter 332 with HasExeBlockHelper { 333 val io = IO(new Bundle { 334 val hartId = Input(UInt(64.W)) 335 val externalInterrupt = new ExternalInterruptIO 336 val l2_pf_enable = Output(Bool()) 337 val l1plus_error, icache_error, dcache_error = Output(new L1CacheErrorInfo) 338 }) 339 340 val difftestIO = IO(new DifftestBundle()) 341 difftestIO <> DontCare 342 343 val trapIO = IO(new TrapIO()) 344 trapIO <> DontCare 345 346 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 347 AddressSpace.checkMemmap() 348 AddressSpace.printMemmap() 349 350 // to fast wake up fp, mem rs 351 val intBlockFastWakeUp = intExuConfigs.filter(_.hasCertainLatency) 352 val intBlockSlowWakeUp = intExuConfigs.filter(_.hasUncertainlatency) 353 354 val ctrlBlock = Module(new CtrlBlock) 355 val integerBlock = Module(new IntegerBlock( 356 fastWakeUpIn = Seq(), 357 slowWakeUpIn = fpExuConfigs.filter(_.writeIntRf) ++ loadExuConfigs, 358 memFastWakeUpIn = loadExuConfigs, 359 fastWakeUpOut = intBlockFastWakeUp, 360 slowWakeUpOut = intBlockSlowWakeUp 361 )) 362 val floatBlock = Module(new FloatBlock( 363 intSlowWakeUpIn = intExuConfigs.filter(_.writeFpRf), 364 memSlowWakeUpIn = loadExuConfigs, 365 fastWakeUpOut = Seq(), 366 slowWakeUpOut = fpExuConfigs 367 )) 368 369 val frontend = outer.frontend.module 370 val memBlock = outer.memBlock.module 371 val l1pluscache = outer.l1pluscache.module 372 val ptw = outer.ptw.module 373 374 io.l1plus_error <> l1pluscache.io.error 375 io.icache_error <> frontend.io.error 376 io.dcache_error <> memBlock.io.error 377 378 frontend.io.backend <> ctrlBlock.io.frontend 379 frontend.io.sfence <> integerBlock.io.fenceio.sfence 380 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 381 frontend.io.csrCtrl <> integerBlock.io.csrio.customCtrl 382 383 frontend.io.icacheMemAcq <> l1pluscache.io.req 384 l1pluscache.io.resp <> frontend.io.icacheMemGrant 385 l1pluscache.io.flush := frontend.io.l1plusFlush 386 frontend.io.fencei := integerBlock.io.fenceio.fencei 387 388 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 389 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 390 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 391 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 392 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 393 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 394 ctrlBlock.io.csrCtrl <> integerBlock.io.csrio.customCtrl 395 396 val memBlockWakeUpInt = memBlock.io.wakeUpOutInt.slow.map(WireInit(_)) 397 val memBlockWakeUpFp = memBlock.io.wakeUpOutFp.slow.map(WireInit(_)) 398 memBlock.io.wakeUpOutInt.slow.foreach(_.ready := true.B) 399 memBlock.io.wakeUpOutFp.slow.foreach(_.ready := true.B) 400 401 fpExuConfigs.zip(floatBlock.io.wakeUpOut.slow).filterNot(_._1.writeIntRf).map(_._2.ready := true.B) 402 val fpBlockWakeUpInt = fpExuConfigs 403 .zip(floatBlock.io.wakeUpOut.slow) 404 .filter(_._1.writeIntRf) 405 .map(_._2) 406 407 intExuConfigs.zip(integerBlock.io.wakeUpOut.slow).filterNot(_._1.writeFpRf).map(_._2.ready := true.B) 408 val intBlockWakeUpFp = intExuConfigs.filter(_.hasUncertainlatency) 409 .zip(integerBlock.io.wakeUpOut.slow) 410 .filter(_._1.writeFpRf) 411 .map(_._2) 412 413 integerBlock.io.wakeUpIn.slow <> fpBlockWakeUpInt ++ memBlockWakeUpInt 414 integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock 415 integerBlock.io.memFastWakeUp <> memBlock.io.ldFastWakeUpInt 416 417 floatBlock.io.intWakeUpFp <> intBlockWakeUpFp 418 floatBlock.io.memWakeUpFp <> memBlockWakeUpFp 419 floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock 420 421 val wakeUpMem = Seq( 422 integerBlock.io.wakeUpOut, 423 floatBlock.io.wakeUpOut, 424 ) 425 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 426 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(_.fast) 427 // Note: 'WireInit' is used to block 'ready's from memBlock, 428 // we don't need 'ready's from memBlock 429 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(_.slow.map(x => WireInit(x))) 430 memBlock.io.intWakeUpFp <> floatBlock.io.intWakeUpOut 431 432 integerBlock.io.csrio.hartId <> io.hartId 433 integerBlock.io.csrio.perf <> DontCare 434 integerBlock.io.csrio.perf.retiredInstr <> ctrlBlock.io.roqio.toCSR.perfinfo.retiredInstr 435 integerBlock.io.csrio.perf.bpuInfo <> ctrlBlock.io.perfInfo.bpuInfo 436 integerBlock.io.csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 437 integerBlock.io.csrio.perf.memInfo <> memBlock.io.memInfo 438 integerBlock.io.csrio.perf.frontendInfo <> frontend.io.frontendInfo 439 440 integerBlock.io.csrio.fpu.fflags <> ctrlBlock.io.roqio.toCSR.fflags 441 integerBlock.io.csrio.fpu.isIllegal := false.B 442 integerBlock.io.csrio.fpu.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 443 integerBlock.io.csrio.fpu.frm <> floatBlock.io.frm 444 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 445 integerBlock.io.csrio.isXRet <> ctrlBlock.io.roqio.toCSR.isXRet 446 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 447 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 448 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 449 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 450 451 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 452 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 453 454 memBlock.io.csrCtrl <> integerBlock.io.csrio.customCtrl 455 memBlock.io.tlbCsr <> integerBlock.io.csrio.tlb 456 memBlock.io.lsqio.roq <> ctrlBlock.io.roqio.lsq 457 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.uop.lqIdx 458 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.uop.sqIdx 459 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.uop.ctrl.commitType) 460 461 val itlbRepeater = Module(new PTWRepeater()) 462 val dtlbRepeater = Module(new PTWRepeater()) 463 itlbRepeater.io.tlb <> frontend.io.ptw 464 dtlbRepeater.io.tlb <> memBlock.io.ptw 465 itlbRepeater.io.sfence <> integerBlock.io.fenceio.sfence 466 dtlbRepeater.io.sfence <> integerBlock.io.fenceio.sfence 467 ptw.io.tlb(0) <> dtlbRepeater.io.ptw 468 ptw.io.tlb(1) <> itlbRepeater.io.ptw 469 ptw.io.sfence <> integerBlock.io.fenceio.sfence 470 ptw.io.csr <> integerBlock.io.csrio.tlb 471 472 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 473 assert(l2PrefetcherParameters._type == "bop") 474 io.l2_pf_enable := integerBlock.io.csrio.customCtrl.l2_pf_enable 475 476 if (!env.FPGAPlatform) { 477 val id = hartIdCore() 478 difftestIO.fromSbuffer <> memBlock.difftestIO.fromSbuffer 479 difftestIO.fromSQ <> memBlock.difftestIO.fromSQ 480 difftestIO.fromCSR <> integerBlock.difftestIO.fromCSR 481 difftestIO.fromRoq <> ctrlBlock.difftestIO.fromRoq 482 difftestIO.fromAtomic <> memBlock.difftestIO.fromAtomic 483 difftestIO.fromPtw <> ptw.difftestIO 484 trapIO <> ctrlBlock.trapIO 485 486 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 487 ExcitingUtils.addSink(debugIntReg, s"DEBUG_INT_ARCH_REG$id", ExcitingUtils.Debug) 488 ExcitingUtils.addSink(debugFpReg, s"DEBUG_FP_ARCH_REG$id", ExcitingUtils.Debug) 489 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 490 difftestIO.fromXSCore.r := debugArchReg 491 } 492 493} 494