1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.backend.exu.Exu._ 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.backend.fu.HasExceptionNO 13import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, PTWRepeater} 14import xiangshan.cache.prefetch._ 15import chipsalliance.rocketchip.config 16import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 17import freechips.rocketchip.tile.HasFPUParameters 18import utils._ 19 20object hartIdCore extends (() => Int) { 21 var x = 0 22 23 def apply(): Int = { 24 x = x + 1 25 x - 1 26 } 27} 28 29case class XSCoreParameters 30( 31 XLEN: Int = 64, 32 HasMExtension: Boolean = true, 33 HasCExtension: Boolean = true, 34 HasDiv: Boolean = true, 35 HasICache: Boolean = true, 36 HasDCache: Boolean = true, 37 EnableStoreQueue: Boolean = true, 38 AddrBits: Int = 64, 39 VAddrBits: Int = 39, 40 PAddrBits: Int = 40, 41 HasFPU: Boolean = true, 42 FetchWidth: Int = 8, 43 EnableBPU: Boolean = true, 44 EnableBPD: Boolean = true, 45 EnableRAS: Boolean = true, 46 EnableLB: Boolean = false, 47 EnableLoop: Boolean = true, 48 EnableSC: Boolean = true, 49 EnbaleTlbDebug: Boolean = false, 50 EnableJal: Boolean = false, 51 EnableUBTB: Boolean = true, 52 HistoryLength: Int = 64, 53 BtbSize: Int = 2048, 54 JbtacSize: Int = 1024, 55 JbtacBanks: Int = 8, 56 RasSize: Int = 16, 57 CacheLineSize: Int = 512, 58 UBtbWays: Int = 16, 59 BtbWays: Int = 2, 60 61 EnableL1plusPrefetcher: Boolean = true, 62 IBufSize: Int = 32, 63 DecodeWidth: Int = 6, 64 RenameWidth: Int = 6, 65 CommitWidth: Int = 6, 66 BrqSize: Int = 32, 67 FtqSize: Int = 48, 68 IssQueSize: Int = 12, 69 NRPhyRegs: Int = 160, 70 NRIntReadPorts: Int = 14, 71 NRIntWritePorts: Int = 8, 72 NRFpReadPorts: Int = 14, 73 NRFpWritePorts: Int = 8, 74 LoadQueueSize: Int = 64, 75 StoreQueueSize: Int = 48, 76 RoqSize: Int = 192, 77 dpParams: DispatchParameters = DispatchParameters( 78 IntDqSize = 16, 79 FpDqSize = 16, 80 LsDqSize = 16, 81 IntDqDeqWidth = 4, 82 FpDqDeqWidth = 4, 83 LsDqDeqWidth = 4 84 ), 85 exuParameters: ExuParameters = ExuParameters( 86 JmpCnt = 1, 87 AluCnt = 4, 88 MulCnt = 0, 89 MduCnt = 2, 90 FmacCnt = 4, 91 FmiscCnt = 2, 92 FmiscDivSqrtCnt = 0, 93 LduCnt = 2, 94 StuCnt = 2 95 ), 96 LoadPipelineWidth: Int = 2, 97 StorePipelineWidth: Int = 2, 98 StoreBufferSize: Int = 16, 99 RefillSize: Int = 512, 100 TlbEntrySize: Int = 32, 101 TlbSPEntrySize: Int = 4, 102 PtwL3EntrySize: Int = 4096, //(256 * 16) or 512 103 PtwSPEntrySize: Int = 16, 104 PtwL1EntrySize: Int = 16, 105 PtwL2EntrySize: Int = 2048, //(256 * 8) 106 NumPerfCounters: Int = 16, 107 NrExtIntr: Int = 150, 108 PerfRealTime: Boolean = false, 109 PerfIntervalBits: Int = 15 110) 111 112trait HasXSParameter { 113 114 val coreParams = Parameters.get.coreParameters 115 val env = Parameters.get.envParameters 116 117 val XLEN = 64 118 val minFLen = 32 119 val fLen = 64 120 121 def xLen = 64 122 123 val HasMExtension = coreParams.HasMExtension 124 val HasCExtension = coreParams.HasCExtension 125 val HasDiv = coreParams.HasDiv 126 val HasIcache = coreParams.HasICache 127 val HasDcache = coreParams.HasDCache 128 val EnableStoreQueue = coreParams.EnableStoreQueue 129 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 130 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 131 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 132 val AddrBytes = AddrBits / 8 // unused 133 val DataBits = XLEN 134 val DataBytes = DataBits / 8 135 val HasFPU = coreParams.HasFPU 136 val FetchWidth = coreParams.FetchWidth 137 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 138 val EnableBPU = coreParams.EnableBPU 139 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 140 val EnableRAS = coreParams.EnableRAS 141 val EnableLB = coreParams.EnableLB 142 val EnableLoop = coreParams.EnableLoop 143 val EnableSC = coreParams.EnableSC 144 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 145 val HistoryLength = coreParams.HistoryLength 146 val BtbSize = coreParams.BtbSize 147 // val BtbWays = 4 148 val BtbBanks = PredictWidth 149 // val BtbSets = BtbSize / BtbWays 150 val JbtacSize = coreParams.JbtacSize 151 val JbtacBanks = coreParams.JbtacBanks 152 val RasSize = coreParams.RasSize 153 val CacheLineSize = coreParams.CacheLineSize 154 val CacheLineHalfWord = CacheLineSize / 16 155 val ExtHistoryLength = HistoryLength + 64 156 val UBtbWays = coreParams.UBtbWays 157 val BtbWays = coreParams.BtbWays 158 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 159 val IBufSize = coreParams.IBufSize 160 val DecodeWidth = coreParams.DecodeWidth 161 val RenameWidth = coreParams.RenameWidth 162 val CommitWidth = coreParams.CommitWidth 163 val BrqSize = coreParams.BrqSize 164 val FtqSize = coreParams.FtqSize 165 val IssQueSize = coreParams.IssQueSize 166 val BrTagWidth = log2Up(BrqSize) 167 val NRPhyRegs = coreParams.NRPhyRegs 168 val PhyRegIdxWidth = log2Up(NRPhyRegs) 169 val RoqSize = coreParams.RoqSize 170 val LoadQueueSize = coreParams.LoadQueueSize 171 val StoreQueueSize = coreParams.StoreQueueSize 172 val dpParams = coreParams.dpParams 173 val exuParameters = coreParams.exuParameters 174 val NRIntReadPorts = coreParams.NRIntReadPorts 175 val NRIntWritePorts = coreParams.NRIntWritePorts 176 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 177 val NRFpReadPorts = coreParams.NRFpReadPorts 178 val NRFpWritePorts = coreParams.NRFpWritePorts 179 val LoadPipelineWidth = coreParams.LoadPipelineWidth 180 val StorePipelineWidth = coreParams.StorePipelineWidth 181 val StoreBufferSize = coreParams.StoreBufferSize 182 val RefillSize = coreParams.RefillSize 183 val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 184 val TlbEntrySize = coreParams.TlbEntrySize 185 val TlbSPEntrySize = coreParams.TlbSPEntrySize 186 val PtwL3EntrySize = coreParams.PtwL3EntrySize 187 val PtwSPEntrySize = coreParams.PtwSPEntrySize 188 val PtwL1EntrySize = coreParams.PtwL1EntrySize 189 val PtwL2EntrySize = coreParams.PtwL2EntrySize 190 val NumPerfCounters = coreParams.NumPerfCounters 191 val NrExtIntr = coreParams.NrExtIntr 192 val PerfRealTime = coreParams.PerfRealTime 193 val PerfIntervalBits = coreParams.PerfIntervalBits 194 195 val instBytes = if (HasCExtension) 2 else 4 196 val instOffsetBits = log2Ceil(instBytes) 197 198 val icacheParameters = ICacheParameters( 199 tagECC = Some("parity"), 200 dataECC = Some("parity"), 201 replacer = Some("setplru"), 202 nMissEntries = 2 203 ) 204 205 val l1plusCacheParameters = L1plusCacheParameters( 206 tagECC = Some("secded"), 207 dataECC = Some("secded"), 208 replacer = Some("setplru"), 209 nMissEntries = 8 210 ) 211 212 val dcacheParameters = DCacheParameters( 213 tagECC = Some("secded"), 214 dataECC = Some("secded"), 215 replacer = Some("setplru"), 216 nMissEntries = 16, 217 nProbeEntries = 16, 218 nReleaseEntries = 16, 219 nStoreReplayEntries = 16 220 ) 221 222 val LRSCCycles = 100 223 224 225 // cache hierarchy configurations 226 val l1BusDataWidth = 256 227 228 // L2 configurations 229 val L1BusWidth = 256 230 val L2Size = 512 * 1024 // 512KB 231 val L2BlockSize = 64 232 val L2NWays = 8 233 val L2NSets = L2Size / L2BlockSize / L2NWays 234 235 // L3 configurations 236 val L2BusWidth = 256 237 val L3Size = 4 * 1024 * 1024 // 4MB 238 val L3BlockSize = 64 239 val L3NBanks = 4 240 val L3NWays = 8 241 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 242 243 // on chip network configurations 244 val L3BusWidth = 256 245 246 // icache prefetcher 247 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 248 enable = true, 249 _type = "stream", 250 streamParams = StreamPrefetchParameters( 251 streamCnt = 2, 252 streamSize = 4, 253 ageWidth = 4, 254 blockBytes = l1plusCacheParameters.blockBytes, 255 reallocStreamOnMissInstantly = true, 256 cacheName = "icache" 257 ) 258 ) 259 260 // dcache prefetcher 261 val l2PrefetcherParameters = L2PrefetcherParameters( 262 enable = true, 263 _type = "bop", // "stream" or "bop" 264 streamParams = StreamPrefetchParameters( 265 streamCnt = 4, 266 streamSize = 4, 267 ageWidth = 4, 268 blockBytes = L2BlockSize, 269 reallocStreamOnMissInstantly = true, 270 cacheName = "dcache" 271 ), 272 bopParams = BOPParameters( 273 rrTableEntries = 256, 274 rrTagBits = 12, 275 scoreBits = 5, 276 roundMax = 50, 277 badScore = 1, 278 blockBytes = L2BlockSize, 279 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 280 ), 281 ) 282} 283 284trait HasXSLog { 285 this: RawModule => 286 implicit val moduleName: String = this.name 287} 288 289abstract class XSModule extends MultiIOModule 290 with HasXSParameter 291 with HasExceptionNO 292 with HasXSLog 293 with HasFPUParameters { 294 def io: Record 295} 296 297//remove this trait after impl module logic 298trait NeedImpl { 299 this: RawModule => 300 override protected def IO[T <: Data](iodef: T): T = { 301 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 302 val io = chisel3.experimental.IO(iodef) 303 io <> DontCare 304 io 305 } 306} 307 308abstract class XSBundle extends Bundle 309 with HasXSParameter 310 311case class EnviromentParameters 312( 313 FPGAPlatform: Boolean = true, 314 EnableDebug: Boolean = false, 315 EnablePerfDebug: Boolean = true, 316 DualCore: Boolean = false 317) 318 319// object AddressSpace extends HasXSParameter { 320// // (start, size) 321// // address out of MMIO will be considered as DRAM 322// def mmio = List( 323// (0x00000000L, 0x40000000L), // internal devices, such as CLINT and PLIC 324// (0x40000000L, 0x40000000L) // external devices 325// ) 326 327// def isMMIO(addr: UInt): Bool = mmio.map(range => { 328// require(isPow2(range._2)) 329// val bits = log2Up(range._2) 330// (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 331// }).reduce(_ || _) 332// } 333 334 335class XSCore()(implicit p: config.Parameters) extends LazyModule 336 with HasXSParameter 337 with HasExeBlockHelper { 338 // outer facing nodes 339 val frontend = LazyModule(new Frontend()) 340 val l1pluscache = LazyModule(new L1plusCache()) 341 val ptw = LazyModule(new PTW()) 342 val memBlock = LazyModule(new MemBlock( 343 fastWakeUpIn = intExuConfigs.filter(_.hasCertainLatency), 344 slowWakeUpIn = intExuConfigs.filter(_.hasUncertainlatency) ++ fpExuConfigs, 345 fastWakeUpOut = Seq(), 346 slowWakeUpOut = loadExuConfigs, 347 numIntWakeUpFp = intExuConfigs.count(_.writeFpRf) 348 )) 349 350 lazy val module = new XSCoreImp(this) 351} 352 353class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) 354 with HasXSParameter 355 with HasExeBlockHelper { 356 val io = IO(new Bundle { 357 val hartId = Input(UInt(64.W)) 358 val externalInterrupt = new ExternalInterruptIO 359 val l2_pf_enable = Output(Bool()) 360 }) 361 362 val difftestIO = IO(new DifftestBundle()) 363 difftestIO <> DontCare 364 365 val trapIO = IO(new TrapIO()) 366 trapIO <> DontCare 367 368 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 369 AddressSpace.checkMemmap() 370 AddressSpace.printMemmap() 371 372 // to fast wake up fp, mem rs 373 val intBlockFastWakeUp = intExuConfigs.filter(_.hasCertainLatency) 374 val intBlockSlowWakeUp = intExuConfigs.filter(_.hasUncertainlatency) 375 376 val ctrlBlock = Module(new CtrlBlock) 377 val integerBlock = Module(new IntegerBlock( 378 fastWakeUpIn = Seq(), 379 slowWakeUpIn = fpExuConfigs.filter(_.writeIntRf) ++ loadExuConfigs, 380 fastWakeUpOut = intBlockFastWakeUp, 381 slowWakeUpOut = intBlockSlowWakeUp 382 )) 383 val floatBlock = Module(new FloatBlock( 384 intSlowWakeUpIn = intExuConfigs.filter(_.writeFpRf), 385 memSlowWakeUpIn = loadExuConfigs, 386 fastWakeUpOut = Seq(), 387 slowWakeUpOut = fpExuConfigs 388 )) 389 390 val frontend = outer.frontend.module 391 val memBlock = outer.memBlock.module 392 val l1pluscache = outer.l1pluscache.module 393 val ptw = outer.ptw.module 394 395 frontend.io.backend <> ctrlBlock.io.frontend 396 frontend.io.sfence <> integerBlock.io.fenceio.sfence 397 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 398 frontend.io.csrCtrl <> integerBlock.io.csrio.customCtrl 399 400 frontend.io.icacheMemAcq <> l1pluscache.io.req 401 l1pluscache.io.resp <> frontend.io.icacheMemGrant 402 l1pluscache.io.flush := frontend.io.l1plusFlush 403 frontend.io.fencei := integerBlock.io.fenceio.fencei 404 405 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 406 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 407 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 408 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 409 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 410 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 411 ctrlBlock.io.csrCtrl <> integerBlock.io.csrio.customCtrl 412 413 val memBlockWakeUpInt = memBlock.io.wakeUpOutInt.slow.map(WireInit(_)) 414 val memBlockWakeUpFp = memBlock.io.wakeUpOutFp.slow.map(WireInit(_)) 415 memBlock.io.wakeUpOutInt.slow.foreach(_.ready := true.B) 416 memBlock.io.wakeUpOutFp.slow.foreach(_.ready := true.B) 417 418 fpExuConfigs.zip(floatBlock.io.wakeUpOut.slow).filterNot(_._1.writeIntRf).map(_._2.ready := true.B) 419 val fpBlockWakeUpInt = fpExuConfigs 420 .zip(floatBlock.io.wakeUpOut.slow) 421 .filter(_._1.writeIntRf) 422 .map(_._2) 423 424 intExuConfigs.zip(integerBlock.io.wakeUpOut.slow).filterNot(_._1.writeFpRf).map(_._2.ready := true.B) 425 val intBlockWakeUpFp = intExuConfigs.filter(_.hasUncertainlatency) 426 .zip(integerBlock.io.wakeUpOut.slow) 427 .filter(_._1.writeFpRf) 428 .map(_._2) 429 430 integerBlock.io.wakeUpIn.slow <> fpBlockWakeUpInt ++ memBlockWakeUpInt 431 integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock 432 433 floatBlock.io.intWakeUpFp <> intBlockWakeUpFp 434 floatBlock.io.memWakeUpFp <> memBlockWakeUpFp 435 floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock 436 437 val wakeUpMem = Seq( 438 integerBlock.io.wakeUpOut, 439 floatBlock.io.wakeUpOut, 440 ) 441 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 442 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(_.fast) 443 // Note: 'WireInit' is used to block 'ready's from memBlock, 444 // we don't need 'ready's from memBlock 445 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(_.slow.map(x => WireInit(x))) 446 memBlock.io.intWakeUpFp <> floatBlock.io.intWakeUpOut 447 448 integerBlock.io.csrio.hartId <> io.hartId 449 integerBlock.io.csrio.perf <> DontCare 450 integerBlock.io.csrio.perf.retiredInstr <> ctrlBlock.io.roqio.toCSR.perfinfo.retiredInstr 451 integerBlock.io.csrio.fpu.fflags <> ctrlBlock.io.roqio.toCSR.fflags 452 integerBlock.io.csrio.fpu.isIllegal := false.B 453 integerBlock.io.csrio.fpu.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 454 integerBlock.io.csrio.fpu.frm <> floatBlock.io.frm 455 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 456 integerBlock.io.csrio.isXRet <> ctrlBlock.io.roqio.toCSR.isXRet 457 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 458 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 459 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 460 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 461 462 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 463 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 464 465 memBlock.io.csrCtrl <> integerBlock.io.csrio.customCtrl 466 memBlock.io.tlbCsr <> integerBlock.io.csrio.tlb 467 memBlock.io.lsqio.roq <> ctrlBlock.io.roqio.lsq 468 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.uop.lqIdx 469 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.uop.sqIdx 470 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.uop.ctrl.commitType) 471 472 val itlbRepeater = Module(new PTWRepeater()) 473 val dtlbRepeater = Module(new PTWRepeater()) 474 itlbRepeater.io.tlb <> frontend.io.ptw 475 dtlbRepeater.io.tlb <> memBlock.io.ptw 476 itlbRepeater.io.sfence <> integerBlock.io.fenceio.sfence 477 dtlbRepeater.io.sfence <> integerBlock.io.fenceio.sfence 478 ptw.io.tlb(0) <> dtlbRepeater.io.ptw 479 ptw.io.tlb(1) <> itlbRepeater.io.ptw 480 ptw.io.sfence <> integerBlock.io.fenceio.sfence 481 ptw.io.csr <> integerBlock.io.csrio.tlb 482 483 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 484 assert(l2PrefetcherParameters._type == "bop") 485 io.l2_pf_enable := integerBlock.io.csrio.customCtrl.l2_pf_enable 486 487 if (!env.FPGAPlatform) { 488 val id = hartIdCore() 489 difftestIO.fromSbuffer <> memBlock.difftestIO.fromSbuffer 490 difftestIO.fromSQ <> memBlock.difftestIO.fromSQ 491 difftestIO.fromCSR <> integerBlock.difftestIO.fromCSR 492 difftestIO.fromRoq <> ctrlBlock.difftestIO.fromRoq 493 difftestIO.fromAtomic <> memBlock.difftestIO.fromAtomic 494 difftestIO.fromPtw <> ptw.difftestIO 495 trapIO <> ctrlBlock.trapIO 496 497 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 498 ExcitingUtils.addSink(debugIntReg, s"DEBUG_INT_ARCH_REG$id", ExcitingUtils.Debug) 499 ExcitingUtils.addSink(debugFpReg, s"DEBUG_FP_ARCH_REG$id", ExcitingUtils.Debug) 500 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 501 difftestIO.fromXSCore.r := debugArchReg 502 } 503 504} 505