1package xiangshan.backend.rename 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan._ 7 8class RatReadPort(implicit p: Parameters) extends XSBundle { 9 val addr = Input(UInt(5.W)) 10 val rdata = Output(UInt(PhyRegIdxWidth.W)) 11} 12 13class RatWritePort(implicit p: Parameters) extends XSBundle { 14 val wen = Input(Bool()) 15 val addr = Input(UInt(5.W)) 16 val wdata = Input(UInt(PhyRegIdxWidth.W)) 17} 18 19class RenameTable(float: Boolean)(implicit p: Parameters) extends XSModule { 20 val io = IO(new Bundle() { 21 val redirect = Input(Bool()) 22 val flush = Input(Bool()) 23 val walkWen = Input(Bool()) 24 val readPorts = Vec({if(float) 4 else 3} * RenameWidth, new RatReadPort) 25 val specWritePorts = Vec(CommitWidth, new RatWritePort) 26 val archWritePorts = Vec(CommitWidth, new RatWritePort) 27 val debug_rdata = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 28 }) 29 30 // speculative rename table 31 val spec_table = RegInit(VecInit(Seq.tabulate(32)(i => i.U(PhyRegIdxWidth.W)))) 32 33 // arch state rename table 34 val arch_table = RegInit(VecInit(Seq.tabulate(32)(i => i.U(PhyRegIdxWidth.W)))) 35 36 // When redirect happens (mis-prediction), don't update the rename table 37 // However, when mis-prediction and walk happens at the same time, rename table needs to be updated 38 for (w <- io.specWritePorts){ 39 when (w.wen && (!(io.redirect || io.flush) || io.walkWen)) { 40 spec_table(w.addr) := w.wdata 41 } 42 } 43 44 for((r, i) <- io.readPorts.zipWithIndex){ 45 r.rdata := spec_table(r.addr) 46 } 47 48 for(w <- io.archWritePorts){ 49 when(w.wen){ arch_table(w.addr) := w.wdata } 50 } 51 52 when (io.flush) { 53 spec_table := arch_table 54 // spec table needs to be updated when flushPipe 55 for (w <- io.archWritePorts) { 56 when(w.wen){ spec_table(w.addr) := w.wdata } 57 } 58 } 59 60 io.debug_rdata := arch_table 61} 62