1package xiangshan 2 3import chipsalliance.rocketchip.config.{Field, Parameters} 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.exu._ 7import xiangshan.backend.fu._ 8import xiangshan.backend.fu.fpu._ 9import xiangshan.backend.dispatch.DispatchParameters 10import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters} 11import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 12 13case object XSCoreParamsKey extends Field[XSCoreParameters] 14 15case class XSCoreParameters 16( 17 HasPrefetch: Boolean = false, 18 HartId: Int = 0, 19 XLEN: Int = 64, 20 HasMExtension: Boolean = true, 21 HasCExtension: Boolean = true, 22 HasDiv: Boolean = true, 23 HasICache: Boolean = true, 24 HasDCache: Boolean = true, 25 AddrBits: Int = 64, 26 VAddrBits: Int = 39, 27 PAddrBits: Int = 40, 28 HasFPU: Boolean = true, 29 FetchWidth: Int = 8, 30 EnableBPU: Boolean = true, 31 EnableBPD: Boolean = true, 32 EnableRAS: Boolean = true, 33 EnableLB: Boolean = false, 34 EnableLoop: Boolean = true, 35 EnableSC: Boolean = true, 36 EnbaleTlbDebug: Boolean = false, 37 EnableJal: Boolean = false, 38 EnableUBTB: Boolean = true, 39 HistoryLength: Int = 64, 40 BtbSize: Int = 2048, 41 JbtacSize: Int = 1024, 42 JbtacBanks: Int = 8, 43 RasSize: Int = 16, 44 CacheLineSize: Int = 512, 45 UBtbWays: Int = 16, 46 BtbWays: Int = 2, 47 48 EnableL1plusPrefetcher: Boolean = true, 49 IBufSize: Int = 48, 50 DecodeWidth: Int = 6, 51 RenameWidth: Int = 6, 52 CommitWidth: Int = 6, 53 BrqSize: Int = 32, 54 FtqSize: Int = 48, 55 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 56 IssQueSize: Int = 16, 57 NRPhyRegs: Int = 160, 58 NRIntReadPorts: Int = 14, 59 NRIntWritePorts: Int = 8, 60 NRFpReadPorts: Int = 14, 61 NRFpWritePorts: Int = 8, 62 LoadQueueSize: Int = 64, 63 StoreQueueSize: Int = 48, 64 RoqSize: Int = 192, 65 dpParams: DispatchParameters = DispatchParameters( 66 IntDqSize = 16, 67 FpDqSize = 16, 68 LsDqSize = 16, 69 IntDqDeqWidth = 4, 70 FpDqDeqWidth = 4, 71 LsDqDeqWidth = 4 72 ), 73 exuParameters: ExuParameters = ExuParameters( 74 JmpCnt = 1, 75 AluCnt = 4, 76 MulCnt = 0, 77 MduCnt = 2, 78 FmacCnt = 4, 79 FmiscCnt = 2, 80 FmiscDivSqrtCnt = 0, 81 LduCnt = 2, 82 StuCnt = 2 83 ), 84 LoadPipelineWidth: Int = 2, 85 StorePipelineWidth: Int = 2, 86 StoreBufferSize: Int = 16, 87 StoreBufferThreshold: Int = 7, 88 RefillSize: Int = 512, 89 TlbEntrySize: Int = 32, 90 TlbSPEntrySize: Int = 4, 91 PtwL3EntrySize: Int = 4096, //(256 * 16) or 512 92 PtwSPEntrySize: Int = 16, 93 PtwL1EntrySize: Int = 16, 94 PtwL2EntrySize: Int = 2048, //(256 * 8) 95 NumPerfCounters: Int = 16, 96 icacheParameters: ICacheParameters = ICacheParameters( 97 tagECC = Some("parity"), 98 dataECC = Some("parity"), 99 replacer = Some("setplru"), 100 nMissEntries = 2 101 ), 102 l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters( 103 tagECC = Some("secded"), 104 dataECC = Some("secded"), 105 replacer = Some("setplru"), 106 nMissEntries = 8 107 ), 108 dcacheParameters: DCacheParameters = DCacheParameters( 109 tagECC = Some("secded"), 110 dataECC = Some("secded"), 111 replacer = Some("setplru"), 112 nMissEntries = 16, 113 nProbeEntries = 16, 114 nReleaseEntries = 16, 115 nStoreReplayEntries = 16 116 ), 117 L2Size: Int = 512 * 1024, // 512KB 118 L2NWays: Int = 8, 119 useFakePTW: Boolean = false, 120 useFakeDCache: Boolean = false, 121 useFakeL1plusCache: Boolean = false, 122 useFakeL2Cache: Boolean = false 123){ 124 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 125 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StExeUnitCfg) 126 127 val intExuConfigs = JumpExeUnitCfg +: ( 128 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) ++ 129 Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) 130 ) 131 132 val fpExuConfigs = 133 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 134 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 135 136 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 137} 138 139case object DebugOptionsKey extends Field[DebugOptions] 140 141case class DebugOptions 142( 143 FPGAPlatform: Boolean = true, 144 EnableDebug: Boolean = true, 145 EnablePerfDebug: Boolean = true, 146 UseDRAMSim: Boolean = false 147) 148 149trait HasXSParameter { 150 151 implicit val p: Parameters 152 153 val coreParams = p(XSCoreParamsKey) 154 val env = p(DebugOptionsKey) 155 156 val XLEN = coreParams.XLEN 157 val hardId = coreParams.HartId 158 val minFLen = 32 159 val fLen = 64 160 def xLen = XLEN 161 162 val HasMExtension = coreParams.HasMExtension 163 val HasCExtension = coreParams.HasCExtension 164 val HasDiv = coreParams.HasDiv 165 val HasIcache = coreParams.HasICache 166 val HasDcache = coreParams.HasDCache 167 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 168 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 169 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 170 val AddrBytes = AddrBits / 8 // unused 171 val DataBits = XLEN 172 val DataBytes = DataBits / 8 173 val HasFPU = coreParams.HasFPU 174 val FetchWidth = coreParams.FetchWidth 175 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 176 val EnableBPU = coreParams.EnableBPU 177 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 178 val EnableRAS = coreParams.EnableRAS 179 val EnableLB = coreParams.EnableLB 180 val EnableLoop = coreParams.EnableLoop 181 val EnableSC = coreParams.EnableSC 182 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 183 val HistoryLength = coreParams.HistoryLength 184 val BtbSize = coreParams.BtbSize 185 // val BtbWays = 4 186 val BtbBanks = PredictWidth 187 // val BtbSets = BtbSize / BtbWays 188 val JbtacSize = coreParams.JbtacSize 189 val JbtacBanks = coreParams.JbtacBanks 190 val RasSize = coreParams.RasSize 191 val CacheLineSize = coreParams.CacheLineSize 192 val CacheLineHalfWord = CacheLineSize / 16 193 val ExtHistoryLength = HistoryLength + 64 194 val UBtbWays = coreParams.UBtbWays 195 val BtbWays = coreParams.BtbWays 196 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 197 val IBufSize = coreParams.IBufSize 198 val DecodeWidth = coreParams.DecodeWidth 199 val RenameWidth = coreParams.RenameWidth 200 val CommitWidth = coreParams.CommitWidth 201 val BrqSize = coreParams.BrqSize 202 val FtqSize = coreParams.FtqSize 203 val IssQueSize = coreParams.IssQueSize 204 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 205 val BrTagWidth = log2Up(BrqSize) 206 val NRPhyRegs = coreParams.NRPhyRegs 207 val PhyRegIdxWidth = log2Up(NRPhyRegs) 208 val RoqSize = coreParams.RoqSize 209 val LoadQueueSize = coreParams.LoadQueueSize 210 val StoreQueueSize = coreParams.StoreQueueSize 211 val dpParams = coreParams.dpParams 212 val exuParameters = coreParams.exuParameters 213 val NRIntReadPorts = coreParams.NRIntReadPorts 214 val NRIntWritePorts = coreParams.NRIntWritePorts 215 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 216 val NRFpReadPorts = coreParams.NRFpReadPorts 217 val NRFpWritePorts = coreParams.NRFpWritePorts 218 val LoadPipelineWidth = coreParams.LoadPipelineWidth 219 val StorePipelineWidth = coreParams.StorePipelineWidth 220 val StoreBufferSize = coreParams.StoreBufferSize 221 val StoreBufferThreshold = coreParams.StoreBufferThreshold 222 val RefillSize = coreParams.RefillSize 223 val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 224 val TlbEntrySize = coreParams.TlbEntrySize 225 val TlbSPEntrySize = coreParams.TlbSPEntrySize 226 val PtwL3EntrySize = coreParams.PtwL3EntrySize 227 val PtwSPEntrySize = coreParams.PtwSPEntrySize 228 val PtwL1EntrySize = coreParams.PtwL1EntrySize 229 val PtwL2EntrySize = coreParams.PtwL2EntrySize 230 val NumPerfCounters = coreParams.NumPerfCounters 231 232 val instBytes = if (HasCExtension) 2 else 4 233 val instOffsetBits = log2Ceil(instBytes) 234 235 val icacheParameters = coreParams.icacheParameters 236 val l1plusCacheParameters = coreParams.l1plusCacheParameters 237 val dcacheParameters = coreParams.dcacheParameters 238 239 val LRSCCycles = 100 240 241 242 // cache hierarchy configurations 243 val l1BusDataWidth = 256 244 245 val useFakeDCache = coreParams.useFakeDCache 246 val useFakePTW = coreParams.useFakePTW 247 val useFakeL1plusCache = coreParams.useFakeL1plusCache 248 // L2 configurations 249 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 250 val L1BusWidth = 256 251 val L2Size = coreParams.L2Size 252 val L2BlockSize = 64 253 val L2NWays = coreParams.L2NWays 254 val L2NSets = L2Size / L2BlockSize / L2NWays 255 256 // L3 configurations 257 val L2BusWidth = 256 258 259 // icache prefetcher 260 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 261 enable = true, 262 _type = "stream", 263 streamParams = StreamPrefetchParameters( 264 streamCnt = 2, 265 streamSize = 4, 266 ageWidth = 4, 267 blockBytes = l1plusCacheParameters.blockBytes, 268 reallocStreamOnMissInstantly = true, 269 cacheName = "icache" 270 ) 271 ) 272 273 // dcache prefetcher 274 val l2PrefetcherParameters = L2PrefetcherParameters( 275 enable = true, 276 _type = "bop", // "stream" or "bop" 277 streamParams = StreamPrefetchParameters( 278 streamCnt = 4, 279 streamSize = 4, 280 ageWidth = 4, 281 blockBytes = L2BlockSize, 282 reallocStreamOnMissInstantly = true, 283 cacheName = "dcache" 284 ), 285 bopParams = BOPParameters( 286 rrTableEntries = 256, 287 rrTagBits = 12, 288 scoreBits = 5, 289 roundMax = 50, 290 badScore = 1, 291 blockBytes = L2BlockSize, 292 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 293 ), 294 ) 295 296 // load violation predict 297 val ResetTimeMax2Pow = 20 //1078576 298 val ResetTimeMin2Pow = 10 //1024 299 // wait table parameters 300 val WaitTableSize = 1024 301 val MemPredPCWidth = log2Up(WaitTableSize) 302 val LWTUse2BitCounter = true 303 // store set parameters 304 val SSITSize = WaitTableSize 305 val LFSTSize = 32 306 val SSIDWidth = log2Up(LFSTSize) 307 val LFSTWidth = 4 308 val StoreSetEnable = true // LWT will be disabled if SS is enabled 309 310 val loadExuConfigs = coreParams.loadExuConfigs 311 val storeExuConfigs = coreParams.storeExuConfigs 312 313 val intExuConfigs = coreParams.intExuConfigs 314 315 val fpExuConfigs = coreParams.fpExuConfigs 316 317 val exuConfigs = coreParams.exuConfigs 318 319} 320