1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils._ 7import xiangshan._ 8import xiangshan.backend.decode.{DecodeStage, ImmUnion} 9import xiangshan.backend.rename.{BusyTable, Rename} 10import xiangshan.backend.dispatch.Dispatch 11import xiangshan.backend.exu._ 12import xiangshan.backend.ftq.{Ftq, FtqRead, HasFtqHelper} 13import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqLsqIO, RoqPtr} 14import xiangshan.mem.LsqEnqIO 15 16class CtrlToIntBlockIO(implicit p: Parameters) extends XSBundle { 17 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 18 val readRf = Vec(NRIntReadPorts, Output(UInt(PhyRegIdxWidth.W))) 19 val jumpPc = Output(UInt(VAddrBits.W)) 20 val jalr_target = Output(UInt(VAddrBits.W)) 21 // int block only uses port 0~7 22 val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(8 / 2).W))) // TODO parameterize 8 here 23 val redirect = ValidIO(new Redirect) 24 val flush = Output(Bool()) 25 val debug_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 26} 27 28class CtrlToFpBlockIO(implicit p: Parameters) extends XSBundle { 29 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 30 val readRf = Vec(NRFpReadPorts, Output(UInt(PhyRegIdxWidth.W))) 31 // fp block uses port 0~11 32 val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W))) 33 val redirect = ValidIO(new Redirect) 34 val flush = Output(Bool()) 35 val debug_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 36} 37 38class CtrlToLsBlockIO(implicit p: Parameters) extends XSBundle { 39 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 40 val enqLsq = Flipped(new LsqEnqIO) 41 val memPredUpdate = Vec(StorePipelineWidth, Input(new MemPredUpdateReq)) 42 val redirect = ValidIO(new Redirect) 43 val flush = Output(Bool()) 44} 45 46class RedirectGenerator(implicit p: Parameters) extends XSModule 47 with HasCircularQueuePtrHelper with HasFtqHelper { 48 val numRedirect = exuParameters.JmpCnt + exuParameters.AluCnt 49 val io = IO(new Bundle() { 50 val exuMispredict = Vec(numRedirect, Flipped(ValidIO(new ExuOutput))) 51 val loadReplay = Flipped(ValidIO(new Redirect)) 52 val flush = Input(Bool()) 53 val stage1FtqRead = Vec(numRedirect + 1, new FtqRead) 54 val stage2FtqRead = new FtqRead 55 val stage2Redirect = ValidIO(new Redirect) 56 val stage3Redirect = ValidIO(new Redirect) 57 val memPredUpdate = Output(new MemPredUpdateReq) 58 val memPredFtqRead = new FtqRead // read req send form stage 2 59 }) 60 /* 61 LoadQueue Jump ALU0 ALU1 ALU2 ALU3 exception Stage1 62 | | | | | | | 63 |============= reg & compare =====| | ======== 64 | | 65 | | 66 | | Stage2 67 | | 68 redirect (flush backend) | 69 | | 70 === reg === | ======== 71 | | 72 |----- mux (exception first) -----| Stage3 73 | 74 redirect (send to frontend) 75 */ 76 private class Wrapper(val n: Int) extends Bundle { 77 val redirect = new Redirect 78 val valid = Bool() 79 val idx = UInt(log2Up(n).W) 80 } 81 def selectOldestRedirect(xs: Seq[Valid[Redirect]]): Vec[Bool] = { 82 val compareVec = (0 until xs.length).map(i => (0 until i).map(j => isAfter(xs(j).bits.roqIdx, xs(i).bits.roqIdx))) 83 val resultOnehot = VecInit((0 until xs.length).map(i => Cat((0 until xs.length).map(j => 84 (if (j < i) !xs(j).valid || compareVec(i)(j) 85 else if (j == i) xs(i).valid 86 else !xs(j).valid || !compareVec(j)(i)) 87 )).andR)) 88 resultOnehot 89 } 90 91 for((ptr, redirect) <- io.stage1FtqRead.map(_.ptr).zip( 92 io.exuMispredict.map(_.bits.redirect) :+ io.loadReplay.bits 93 )){ ptr := redirect.ftqIdx } 94 95 def getRedirect(exuOut: Valid[ExuOutput]): ValidIO[Redirect] = { 96 val redirect = Wire(Valid(new Redirect)) 97 redirect.valid := exuOut.valid && exuOut.bits.redirect.cfiUpdate.isMisPred 98 redirect.bits := exuOut.bits.redirect 99 redirect 100 } 101 102 val jumpOut = io.exuMispredict.head 103 val allRedirect = VecInit(io.exuMispredict.map(x => getRedirect(x)) :+ io.loadReplay) 104 val oldestOneHot = selectOldestRedirect(allRedirect) 105 val needFlushVec = VecInit(allRedirect.map(_.bits.roqIdx.needFlush(io.stage2Redirect, io.flush))) 106 val oldestValid = VecInit(oldestOneHot.zip(needFlushVec).map{ case (v, f) => v && !f }).asUInt.orR 107 val oldestExuOutput = Mux1H((0 until 5).map(oldestOneHot), io.exuMispredict) 108 val oldestRedirect = Mux1H(oldestOneHot, allRedirect) 109 110 val s1_jumpTarget = RegEnable(jumpOut.bits.redirect.cfiUpdate.target, jumpOut.valid) 111 val s1_imm12_reg = RegNext(oldestExuOutput.bits.uop.ctrl.imm(11, 0)) 112 val s1_pd = RegNext(oldestExuOutput.bits.uop.cf.pd) 113 val s1_redirect_bits_reg = RegNext(oldestRedirect.bits) 114 val s1_redirect_valid_reg = RegNext(oldestValid) 115 val s1_redirect_onehot = RegNext(oldestOneHot) 116 117 // stage1 -> stage2 118 io.stage2Redirect.valid := s1_redirect_valid_reg && !io.flush 119 io.stage2Redirect.bits := s1_redirect_bits_reg 120 io.stage2Redirect.bits.cfiUpdate := DontCare 121 // at stage2, we read ftq to get pc 122 io.stage2FtqRead.ptr := s1_redirect_bits_reg.ftqIdx 123 124 val s1_isReplay = s1_redirect_onehot(5) 125 val s1_isJump = s1_redirect_onehot(0) 126 val ftqRead = Mux1H(s1_redirect_onehot, io.stage1FtqRead).entry 127 val cfiUpdate_pc = Cat( 128 ftqRead.ftqPC.head(VAddrBits - s1_redirect_bits_reg.ftqOffset.getWidth - instOffsetBits), 129 s1_redirect_bits_reg.ftqOffset, 130 0.U(instOffsetBits.W) 131 ) 132 val real_pc = GetPcByFtq( 133 ftqRead.ftqPC, s1_redirect_bits_reg.ftqOffset, 134 ftqRead.lastPacketPC.valid, 135 ftqRead.lastPacketPC.bits 136 ) 137 val brTarget = real_pc + SignExt(ImmUnion.B.toImm32(s1_imm12_reg), XLEN) 138 val snpc = real_pc + Mux(s1_pd.isRVC, 2.U, 4.U) 139 val target = Mux(s1_isReplay, 140 real_pc, // repaly from itself 141 Mux(s1_redirect_bits_reg.cfiUpdate.taken, 142 Mux(s1_isJump, s1_jumpTarget, brTarget), 143 snpc 144 ) 145 ) 146 147 // get pc from ftq 148 io.memPredFtqRead.ptr := s1_redirect_bits_reg.stFtqIdx 149 // valid only if redirect is caused by load violation 150 // store_pc is used to update store set 151 val memPredFtqRead = io.memPredFtqRead.entry 152 val store_pc = GetPcByFtq(memPredFtqRead.ftqPC, RegNext(s1_redirect_bits_reg).stFtqOffset, 153 memPredFtqRead.lastPacketPC.valid, 154 memPredFtqRead.lastPacketPC.bits 155 ) 156 157 // update load violation predictor if load violation redirect triggered 158 io.memPredUpdate.valid := RegNext(s1_isReplay && s1_redirect_valid_reg, init = false.B) 159 // update wait table 160 io.memPredUpdate.waddr := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth)) 161 io.memPredUpdate.wdata := true.B 162 // update store set 163 io.memPredUpdate.ldpc := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth)) 164 // store pc is ready 1 cycle after s1_isReplay is judged 165 io.memPredUpdate.stpc := XORFold(store_pc(VAddrBits-1, 1), MemPredPCWidth) 166 167 168 val s2_br_mask = RegEnable(ftqRead.br_mask, enable = s1_redirect_valid_reg) 169 val s2_sawNotTakenBranch = RegEnable(VecInit((0 until PredictWidth).map{ i => 170 if(i == 0) false.B else Cat(ftqRead.br_mask.take(i)).orR() 171 })(s1_redirect_bits_reg.ftqOffset), enable = s1_redirect_valid_reg) 172 val s2_hist = RegEnable(ftqRead.hist, enable = s1_redirect_valid_reg) 173 val s2_target = RegEnable(target, enable = s1_redirect_valid_reg) 174 val s2_pd = RegEnable(s1_pd, enable = s1_redirect_valid_reg) 175 val s2_cfiUpdata_pc = RegEnable(cfiUpdate_pc, enable = s1_redirect_valid_reg) 176 val s2_redirect_bits_reg = RegEnable(s1_redirect_bits_reg, enable = s1_redirect_valid_reg) 177 val s2_redirect_valid_reg = RegNext(s1_redirect_valid_reg && !io.flush, init = false.B) 178 val s2_ftqRead = io.stage2FtqRead.entry 179 180 io.stage3Redirect.valid := s2_redirect_valid_reg 181 io.stage3Redirect.bits := s2_redirect_bits_reg 182 val stage3CfiUpdate = io.stage3Redirect.bits.cfiUpdate 183 stage3CfiUpdate.pc := s2_cfiUpdata_pc 184 stage3CfiUpdate.pd := s2_pd 185 stage3CfiUpdate.rasSp := s2_ftqRead.rasSp 186 stage3CfiUpdate.rasEntry := s2_ftqRead.rasTop 187 stage3CfiUpdate.predHist := s2_ftqRead.predHist 188 stage3CfiUpdate.specCnt := s2_ftqRead.specCnt 189 stage3CfiUpdate.hist := s2_hist 190 stage3CfiUpdate.predTaken := s2_redirect_bits_reg.cfiUpdate.predTaken 191 stage3CfiUpdate.sawNotTakenBranch := s2_sawNotTakenBranch 192 stage3CfiUpdate.target := s2_target 193 stage3CfiUpdate.taken := s2_redirect_bits_reg.cfiUpdate.taken 194 stage3CfiUpdate.isMisPred := s2_redirect_bits_reg.cfiUpdate.isMisPred 195} 196 197class CtrlBlock(implicit p: Parameters) extends XSModule 198 with HasCircularQueuePtrHelper with HasFtqHelper { 199 val io = IO(new Bundle { 200 val frontend = Flipped(new FrontendToBackendIO) 201 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 202 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 203 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 204 val toIntBlock = new CtrlToIntBlockIO 205 val toFpBlock = new CtrlToFpBlockIO 206 val toLsBlock = new CtrlToLsBlockIO 207 val roqio = new Bundle { 208 // to int block 209 val toCSR = new RoqCSRIO 210 val exception = ValidIO(new ExceptionInfo) 211 // to mem block 212 val lsq = new RoqLsqIO 213 } 214 val csrCtrl = Input(new CustomCSRCtrlIO) 215 val perfInfo = Output(new Bundle{ 216 val ctrlInfo = new Bundle { 217 val roqFull = Input(Bool()) 218 val intdqFull = Input(Bool()) 219 val fpdqFull = Input(Bool()) 220 val lsdqFull = Input(Bool()) 221 } 222 val bpuInfo = new Bundle { 223 val bpRight = Output(UInt(XLEN.W)) 224 val bpWrong = Output(UInt(XLEN.W)) 225 } 226 }) 227 }) 228 229 val ftq = Module(new Ftq) 230 231 val decode = Module(new DecodeStage) 232 val rename = Module(new Rename) 233 val dispatch = Module(new Dispatch) 234 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 235 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 236 val redirectGen = Module(new RedirectGenerator) 237 238 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt 239 val roq = Module(new Roq(roqWbSize)) 240 241 val backendRedirect = redirectGen.io.stage2Redirect 242 val frontendRedirect = redirectGen.io.stage3Redirect 243 val flush = roq.io.flushOut.valid 244 val flushReg = RegNext(flush) 245 246 val exuRedirect = io.fromIntBlock.exuRedirect.map(x => { 247 val valid = x.valid && x.bits.redirectValid 248 val killedByOlder = x.bits.uop.roqIdx.needFlush(backendRedirect, flushReg) 249 val delayed = Wire(Valid(new ExuOutput)) 250 delayed.valid := RegNext(valid && !killedByOlder, init = false.B) 251 delayed.bits := RegEnable(x.bits, x.valid) 252 delayed 253 }) 254 val loadReplay = Wire(Valid(new Redirect)) 255 loadReplay.valid := RegNext(io.fromLsBlock.replay.valid && 256 !io.fromLsBlock.replay.bits.roqIdx.needFlush(backendRedirect, flushReg), 257 init = false.B 258 ) 259 loadReplay.bits := RegEnable(io.fromLsBlock.replay.bits, io.fromLsBlock.replay.valid) 260 VecInit(ftq.io.ftqRead.tail.dropRight(2)) <> redirectGen.io.stage1FtqRead 261 ftq.io.ftqRead.dropRight(1).last <> redirectGen.io.memPredFtqRead 262 ftq.io.cfiRead <> redirectGen.io.stage2FtqRead 263 redirectGen.io.exuMispredict <> exuRedirect 264 redirectGen.io.loadReplay <> loadReplay 265 redirectGen.io.flush := flushReg 266 267 ftq.io.enq <> io.frontend.fetchInfo 268 for(i <- 0 until CommitWidth){ 269 ftq.io.roq_commits(i).valid := roq.io.commits.valid(i) && !roq.io.commits.isWalk 270 ftq.io.roq_commits(i).bits := roq.io.commits.info(i) 271 } 272 ftq.io.redirect <> backendRedirect 273 ftq.io.flush := flushReg 274 ftq.io.flushIdx := RegNext(roq.io.flushOut.bits.ftqIdx) 275 ftq.io.flushOffset := RegNext(roq.io.flushOut.bits.ftqOffset) 276 ftq.io.frontendRedirect <> frontendRedirect 277 ftq.io.exuWriteback <> exuRedirect 278 279 ftq.io.ftqRead.last.ptr := roq.io.flushOut.bits.ftqIdx 280 val flushPC = GetPcByFtq( 281 ftq.io.ftqRead.last.entry.ftqPC, 282 RegEnable(roq.io.flushOut.bits.ftqOffset, roq.io.flushOut.valid), 283 ftq.io.ftqRead.last.entry.lastPacketPC.valid, 284 ftq.io.ftqRead.last.entry.lastPacketPC.bits 285 ) 286 287 val flushRedirect = Wire(Valid(new Redirect)) 288 flushRedirect.valid := flushReg 289 flushRedirect.bits := DontCare 290 flushRedirect.bits.ftqIdx := RegEnable(roq.io.flushOut.bits.ftqIdx, flush) 291 flushRedirect.bits.interrupt := true.B 292 flushRedirect.bits.cfiUpdate.target := Mux(io.roqio.toCSR.isXRet || roq.io.exception.valid, 293 io.roqio.toCSR.trapTarget, 294 flushPC + 4.U // flush pipe 295 ) 296 val flushRedirectReg = Wire(Valid(new Redirect)) 297 flushRedirectReg.valid := RegNext(flushRedirect.valid, init = false.B) 298 flushRedirectReg.bits := RegEnable(flushRedirect.bits, enable = flushRedirect.valid) 299 300 io.frontend.redirect_cfiUpdate := Mux(flushRedirectReg.valid, flushRedirectReg, frontendRedirect) 301 io.frontend.commit_cfiUpdate := ftq.io.commit_ftqEntry 302 io.frontend.ftqEnqPtr := ftq.io.enqPtr 303 io.frontend.ftqLeftOne := ftq.io.leftOne 304 305 decode.io.in <> io.frontend.cfVec 306 // currently, we only update wait table when isReplay 307 decode.io.memPredUpdate(0) <> RegNext(redirectGen.io.memPredUpdate) 308 decode.io.memPredUpdate(1) := DontCare 309 decode.io.memPredUpdate(1).valid := false.B 310 // decode.io.memPredUpdate <> io.toLsBlock.memPredUpdate 311 decode.io.csrCtrl := RegNext(io.csrCtrl) 312 313 314 val jumpInst = dispatch.io.enqIQCtrl(0).bits 315 val ftqOffsetReg = Reg(UInt(log2Up(PredictWidth).W)) 316 ftqOffsetReg := jumpInst.cf.ftqOffset 317 ftq.io.ftqRead(0).ptr := jumpInst.cf.ftqPtr // jump 318 io.toIntBlock.jumpPc := GetPcByFtq( 319 ftq.io.ftqRead(0).entry.ftqPC, ftqOffsetReg, 320 ftq.io.ftqRead(0).entry.lastPacketPC.valid, 321 ftq.io.ftqRead(0).entry.lastPacketPC.bits 322 ) 323 io.toIntBlock.jalr_target := ftq.io.ftqRead(0).entry.target 324 325 // pipeline between decode and dispatch 326 for (i <- 0 until RenameWidth) { 327 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, 328 flushReg || io.frontend.redirect_cfiUpdate.valid) 329 } 330 331 rename.io.redirect <> backendRedirect 332 rename.io.flush := flushReg 333 rename.io.roqCommits <> roq.io.commits 334 rename.io.out <> dispatch.io.fromRename 335 rename.io.renameBypass <> dispatch.io.renameBypass 336 rename.io.dispatchInfo <> dispatch.io.preDpInfo 337 rename.io.csrCtrl <> RegNext(io.csrCtrl) 338 339 dispatch.io.redirect <> backendRedirect 340 dispatch.io.flush := flushReg 341 dispatch.io.enqRoq <> roq.io.enq 342 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 343 dispatch.io.readIntRf <> io.toIntBlock.readRf 344 dispatch.io.readFpRf <> io.toFpBlock.readRf 345 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 346 intBusyTable.io.allocPregs(i).valid := preg.isInt 347 fpBusyTable.io.allocPregs(i).valid := preg.isFp 348 intBusyTable.io.allocPregs(i).bits := preg.preg 349 fpBusyTable.io.allocPregs(i).bits := preg.preg 350 } 351 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 352 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 353// dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 354 dispatch.io.csrCtrl <> io.csrCtrl 355 dispatch.io.storeIssue <> io.fromLsBlock.stIn 356 357 358 fpBusyTable.io.flush := flushReg 359 intBusyTable.io.flush := flushReg 360 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 361 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 362 setPhyRegRdy.bits := wb.bits.uop.pdest 363 } 364 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 365 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 366 setPhyRegRdy.bits := wb.bits.uop.pdest 367 } 368 intBusyTable.io.read <> dispatch.io.readIntState 369 fpBusyTable.io.read <> dispatch.io.readFpState 370 371 roq.io.redirect <> backendRedirect 372 val exeWbResults = VecInit(io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut) 373 for((roq_wb, wb) <- roq.io.exeWbResults.zip(exeWbResults)) { 374 roq_wb.valid := RegNext(wb.valid && !wb.bits.uop.roqIdx.needFlush(backendRedirect, flushReg)) 375 roq_wb.bits := RegNext(wb.bits) 376 } 377 378 // TODO: is 'backendRedirect' necesscary? 379 io.toIntBlock.redirect <> backendRedirect 380 io.toIntBlock.flush <> flushReg 381 io.toIntBlock.debug_rat <> rename.io.debug_int_rat 382 io.toFpBlock.redirect <> backendRedirect 383 io.toFpBlock.flush <> flushReg 384 io.toFpBlock.debug_rat <> rename.io.debug_fp_rat 385 io.toLsBlock.redirect <> backendRedirect 386 io.toLsBlock.flush <> flushReg 387 388 dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 389 dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 390 391 // roq to int block 392 io.roqio.toCSR <> roq.io.csr 393 io.roqio.toCSR.perfinfo.retiredInstr <> RegNext(roq.io.csr.perfinfo.retiredInstr) 394 io.roqio.exception := roq.io.exception 395 io.roqio.exception.bits.uop.cf.pc := flushPC 396 // roq to mem block 397 io.roqio.lsq <> roq.io.lsq 398 399 io.perfInfo.ctrlInfo.roqFull := RegNext(roq.io.roqFull) 400 io.perfInfo.ctrlInfo.intdqFull := RegNext(dispatch.io.ctrlInfo.intdqFull) 401 io.perfInfo.ctrlInfo.fpdqFull := RegNext(dispatch.io.ctrlInfo.fpdqFull) 402 io.perfInfo.ctrlInfo.lsdqFull := RegNext(dispatch.io.ctrlInfo.lsdqFull) 403 io.perfInfo.bpuInfo <> RegNext(ftq.io.bpuInfo) 404} 405