xref: /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala (revision 2225d46ebbe2fd16b9b29963c27a7d0385a42709) 
1package xiangshan.frontend
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3._
5import chisel3.util._
6import xiangshan._
7import utils._
8import chisel3.experimental.chiselName
9
10trait BimParams extends HasXSParameter {
11  val BimBanks = PredictWidth
12  val BimSize = 4096
13  val nRows = BimSize / BimBanks
14  val bypassEntries = 4
15}
16
17@chiselName
18class BIM(implicit p: Parameters) extends BasePredictor with BimParams {
19  class BIMResp extends Resp {
20    val ctrs = Vec(PredictWidth, UInt(2.W))
21  }
22  class BIMMeta extends Meta {
23    val ctrs = Vec(PredictWidth, UInt(2.W))
24  }
25  class BIMFromOthers extends FromOthers {}
26
27  class BIMIO(implicit p: Parameters) extends DefaultBasePredictorIO {
28    val resp = Output(new BIMResp)
29    val meta = Output(new BIMMeta)
30  }
31
32  override val io = IO(new BIMIO)
33  override val debug = true
34
35  val bimAddr = new TableAddr(log2Up(BimSize), BimBanks)
36
37  val bim = Module(new SRAMTemplate(UInt(2.W), set = nRows, way=BimBanks, shouldReset = false, holdRead = true))
38
39  val doing_reset = RegInit(true.B)
40  val resetRow = RegInit(0.U(log2Ceil(nRows).W))
41  resetRow := resetRow + doing_reset
42  when (resetRow === (nRows-1).U) { doing_reset := false.B }
43
44  val if1_packetAlignedPC = packetAligned(io.pc.bits)
45  val if2_pc = RegEnable(if1_packetAlignedPC, io.pc.valid)
46
47  val if1_mask = io.inMask
48  val if1_row  = bimAddr.getBankIdx(if1_packetAlignedPC)
49
50  bim.io.r.req.valid := io.pc.valid
51  bim.io.r.req.bits.setIdx := if1_row
52
53  val if2_bimRead = bim.io.r.resp.data
54  val ctrlMask = Fill(if2_bimRead.getWidth, ctrl.bim_enable.asUInt).asTypeOf(if2_bimRead)
55  io.resp.ctrs  := VecInit(if2_bimRead zip ctrlMask map {case (a, b) => a & b})
56  io.meta.ctrs  := if2_bimRead
57
58  val updateValid = RegNext(io.update.valid)
59  val u = RegNext(io.update.bits)
60
61  val updateRow = bimAddr.getBankIdx(u.ftqPC)
62
63
64  val wrbypass_ctrs       = RegInit(0.U.asTypeOf(Vec(bypassEntries, Vec(BimBanks, UInt(2.W)))))
65  val wrbypass_ctr_valids = RegInit(0.U.asTypeOf(Vec(bypassEntries, Vec(BimBanks, Bool()))))
66  val wrbypass_rows     = RegInit(0.U.asTypeOf(Vec(bypassEntries, UInt(log2Up(nRows).W))))
67  val wrbypass_enq_idx  = RegInit(0.U(log2Up(bypassEntries).W))
68
69  val wrbypass_hits = VecInit((0 until bypassEntries).map( i =>
70    !doing_reset && wrbypass_rows(i) === updateRow))
71  val wrbypass_hit = wrbypass_hits.reduce(_||_)
72  val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
73
74  val oldCtrs = VecInit((0 until BimBanks).map(b =>
75                  Mux(wrbypass_hit && wrbypass_ctr_valids(wrbypass_hit_idx)(b),
76                    wrbypass_ctrs(wrbypass_hit_idx)(b), u.metas(b).bimCtr)))
77
78  val newTakens = VecInit((0 until BimBanks).map(b => u.cfiIndex.valid && u.cfiIndex.bits === b.U))
79  val newCtrs = VecInit((0 until BimBanks).map(b => satUpdate(oldCtrs(b), 2, newTakens(b))))
80  // val oldSaturated = newCtr === oldCtr
81
82  val needToUpdate = VecInit((0 until PredictWidth).map(i => updateValid && u.br_mask(i) && u.valids(i)))
83
84  when (reset.asBool) { wrbypass_ctr_valids.foreach(_.foreach(_ := false.B))}
85
86  for (b <- 0 until BimBanks) {
87    when (needToUpdate.reduce(_||_)) {
88      when (wrbypass_hit) {
89        when (needToUpdate(b)) {
90          wrbypass_ctrs(wrbypass_hit_idx)(b) := newCtrs(b)
91          wrbypass_ctr_valids(wrbypass_hit_idx)(b) := true.B
92        }
93      }.otherwise {
94        wrbypass_ctr_valids(wrbypass_enq_idx)(b) := false.B
95        when (needToUpdate(b)) {
96          wrbypass_ctr_valids(wrbypass_enq_idx)(b) := true.B
97          wrbypass_ctrs(wrbypass_enq_idx)(b) := newCtrs(b)
98        }
99      }
100    }
101  }
102
103  when (needToUpdate.reduce(_||_) && !wrbypass_hit) {
104    wrbypass_rows(wrbypass_enq_idx) := updateRow
105    wrbypass_enq_idx := (wrbypass_enq_idx + 1.U)(log2Up(bypassEntries)-1,0)
106  }
107
108  bim.io.w.apply(
109    valid = needToUpdate.asUInt.orR || doing_reset,
110    data = Mux(doing_reset, VecInit(Seq.fill(BimBanks)(2.U(2.W))), newCtrs),
111    setIdx = Mux(doing_reset, resetRow, updateRow),
112    waymask = Mux(doing_reset, Fill(BimBanks, "b1".U).asUInt, needToUpdate.asUInt)
113  )
114
115  XSPerfAccumulate("bim_wrbypass_hit", needToUpdate.reduce(_||_) && wrbypass_hit)
116  XSPerfAccumulate("bim_wrbypass_enq", needToUpdate.reduce(_||_) && !wrbypass_hit)
117
118  if (BPUDebug && debug) {
119    val u = io.update.bits
120    XSDebug(doing_reset, "Reseting...\n")
121    XSDebug("[update] v=%d pc=%x valids=%b, tgt=%x\n", updateValid, u.ftqPC, u.valids.asUInt, u.target)
122
123    XSDebug("[update] brMask=%b, taken=%b isMisPred=%b\n", u.br_mask.asUInt, newTakens.asUInt, u.mispred.asUInt)
124    for (i <- 0 until BimBanks) {
125      XSDebug(RegNext(io.pc.valid && io.inMask(i)), p"BimResp[$i]: ctr = ${io.resp.ctrs(i)}\n")
126      XSDebug(needToUpdate(i),
127        p"update bim bank $i: pc:${Hexadecimal(u.ftqPC)}, taken:${u.takens(i)}, " +
128        p"oldCtr:${oldCtrs(i)}, newCtr:${newCtrs(i)}\n")
129      XSDebug(wrbypass_hit && wrbypass_ctr_valids(wrbypass_hit_idx)(i) && needToUpdate(i),
130        p"bank $i wrbypass hit wridx $wrbypass_hit_idx: row:$updateRow, " +
131        p"ctr:${oldCtrs(i)}, newCtr:${newCtrs(i)}\n")
132      XSDebug(true.B, p"bimCtr(${i.U})=${Binary(u.metas(i).bimCtr)} oldCtr=${Binary(oldCtrs(i))} newCtr=${Binary(newCtrs(i))}\n")
133    }
134  }
135
136}
137