1package system 2 3import chipsalliance.rocketchip.config.{Field, Parameters} 4import chisel3._ 5import chisel3.util._ 6import xiangshan.{DebugOptionsKey, HasXSParameter, XSBundle, XSCore, XSCoreParameters} 7import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, L1BusErrors} 8 9case object SoCParamsKey extends Field[SoCParameters] 10 11case class SoCParameters 12( 13 cores: List[XSCoreParameters], 14 EnableILA: Boolean = false, 15 extIntrs: Int = 150 16){ 17 val PAddrBits = cores.map(_.PAddrBits).reduce((x, y) => if(x > y) x else y) 18 // L3 configurations 19 val L3InnerBusWidth = 256 20 val L3Size = 4 * 1024 * 1024 // 4MB 21 val L3BlockSize = 64 22 val L3NBanks = 4 23 val L3NWays = 8 24 25 // on chip network configurations 26 val L3OuterBusWidth = 256 27 28} 29 30trait HasSoCParameter { 31 implicit val p: Parameters 32 33 val soc = p(SoCParamsKey) 34 val debugOpts = p(DebugOptionsKey) 35 val NumCores = soc.cores.size 36 val EnableILA = soc.EnableILA 37 38 // L3 configurations 39 val L3InnerBusWidth = soc.L3InnerBusWidth 40 val L3Size = soc.L3Size 41 val L3BlockSize = soc.L3BlockSize 42 val L3NBanks = soc.L3NBanks 43 val L3NWays = soc.L3NWays 44 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 45 46 // on chip network configurations 47 val L3OuterBusWidth = soc.L3OuterBusWidth 48 49 val NrExtIntr = soc.extIntrs 50} 51 52class ILABundle extends Bundle {} 53 54 55class L1CacheErrorInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter { 56 val paddr = Valid(UInt(soc.PAddrBits.W)) 57 // for now, we only detect ecc 58 val ecc_error = Valid(Bool()) 59} 60 61class XSL1BusErrors(val nCores: Int)(implicit val p: Parameters) extends BusErrors { 62 val icache = Vec(nCores, new L1CacheErrorInfo) 63 val l1plus = Vec(nCores, new L1CacheErrorInfo) 64 val dcache = Vec(nCores, new L1CacheErrorInfo) 65 66 override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] = 67 List.tabulate(nCores){i => 68 List( 69 Some(icache(i).paddr, s"IBUS_$i", s"Icache_$i bus error"), 70 Some(icache(i).ecc_error, s"I_ECC_$i", s"Icache_$i ecc error"), 71 Some(l1plus(i).paddr, s"L1PLUS_$i", s"L1PLUS_$i bus error"), 72 Some(l1plus(i).ecc_error, s"L1PLUS_ECC_$i", s"L1PLUS_$i ecc error"), 73 Some(dcache(i).paddr, s"DBUS_$i", s"Dcache_$i bus error"), 74 Some(dcache(i).ecc_error, s"D_ECC_$i", s"Dcache_$i ecc error") 75 ) 76 }.flatten 77} 78