1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache._ 8import xiangshan.cache.{DCacheWordIO, DCacheLineIO, TlbRequestIO, MemoryOpConstants} 9import xiangshan.backend.LSUOpType 10import xiangshan.mem._ 11import xiangshan.backend.roq.RoqLsqIO 12 13class ExceptionAddrIO extends XSBundle { 14 val lsIdx = Input(new LSIdx) 15 val isStore = Input(Bool()) 16 val vaddr = Output(UInt(VAddrBits.W)) 17} 18 19class FwdEntry extends XSBundle { 20 val valid = Bool() 21 val data = UInt(8.W) 22} 23 24// inflight miss block reqs 25class InflightBlockInfo extends XSBundle { 26 val block_addr = UInt(PAddrBits.W) 27 val valid = Bool() 28} 29 30class LsqEnqIO extends XSBundle { 31 val canAccept = Output(Bool()) 32 val needAlloc = Vec(RenameWidth, Input(UInt(2.W))) 33 val req = Vec(RenameWidth, Flipped(ValidIO(new MicroOp))) 34 val resp = Vec(RenameWidth, Output(new LSIdx)) 35} 36 37// Load / Store Queue Wrapper for XiangShan Out of Order LSU 38class LsqWrappper extends XSModule with HasDCacheParameters { 39 val io = IO(new Bundle() { 40 val enq = new LsqEnqIO 41 val brqRedirect = Flipped(ValidIO(new Redirect)) 42 val flush = Input(Bool()) 43 val loadIn = Vec(LoadPipelineWidth, Flipped(Valid(new LsPipelineBundle))) 44 val storeIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) 45 val loadDataForwarded = Vec(LoadPipelineWidth, Input(Bool())) 46 val needReplayFromRS = Vec(LoadPipelineWidth, Input(Bool())) 47 val sbuffer = Vec(StorePipelineWidth, Decoupled(new DCacheWordReq)) 48 val ldout = Vec(2, DecoupledIO(new ExuOutput)) // writeback int load 49 val mmioStout = DecoupledIO(new ExuOutput) // writeback uncached store 50 val forward = Vec(LoadPipelineWidth, Flipped(new MaskedLoadForwardQueryIO)) 51 val roq = Flipped(new RoqLsqIO) 52 val rollback = Output(Valid(new Redirect)) 53 val dcache = Flipped(ValidIO(new Refill)) 54 val uncache = new DCacheWordIO 55 val exceptionAddr = new ExceptionAddrIO 56 val sqempty = Output(Bool()) 57 val issuePtrExt = Output(new SqPtr) 58 val storeIssue = Vec(StorePipelineWidth, Flipped(Valid(new ExuInput))) 59 val sqFull = Output(Bool()) 60 val lqFull = Output(Bool()) 61 }) 62 val difftestIO = IO(new Bundle() { 63 val fromSQ = new Bundle() { 64 val storeCommit = Output(UInt(2.W)) 65 val storeAddr = Output(Vec(2, UInt(64.W))) 66 val storeData = Output(Vec(2, UInt(64.W))) 67 val storeMask = Output(Vec(2, UInt(8.W))) 68 } 69 }) 70 difftestIO <> DontCare 71 72 val loadQueue = Module(new LoadQueue) 73 val storeQueue = Module(new StoreQueue) 74 75 // io.enq logic 76 // LSQ: send out canAccept when both load queue and store queue are ready 77 // Dispatch: send instructions to LSQ only when they are ready 78 io.enq.canAccept := loadQueue.io.enq.canAccept && storeQueue.io.enq.canAccept 79 loadQueue.io.enq.sqCanAccept := storeQueue.io.enq.canAccept 80 storeQueue.io.enq.lqCanAccept := loadQueue.io.enq.canAccept 81 for (i <- 0 until RenameWidth) { 82 loadQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(0) 83 loadQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(0) && io.enq.req(i).valid 84 loadQueue.io.enq.req(i).bits := io.enq.req(i).bits 85 86 storeQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(1) 87 storeQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(1) && io.enq.req(i).valid 88 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 89 90 io.enq.resp(i).lqIdx := loadQueue.io.enq.resp(i) 91 io.enq.resp(i).sqIdx := storeQueue.io.enq.resp(i) 92 } 93 94 // load queue wiring 95 loadQueue.io.brqRedirect <> io.brqRedirect 96 loadQueue.io.flush <> io.flush 97 loadQueue.io.loadIn <> io.loadIn 98 loadQueue.io.storeIn <> io.storeIn 99 loadQueue.io.loadDataForwarded <> io.loadDataForwarded 100 loadQueue.io.needReplayFromRS <> io.needReplayFromRS 101 loadQueue.io.ldout <> io.ldout 102 loadQueue.io.roq <> io.roq 103 loadQueue.io.rollback <> io.rollback 104 loadQueue.io.dcache <> io.dcache 105 loadQueue.io.exceptionAddr.lsIdx := io.exceptionAddr.lsIdx 106 loadQueue.io.exceptionAddr.isStore := DontCare 107 108 // store queue wiring 109 // storeQueue.io <> DontCare 110 storeQueue.io.brqRedirect <> io.brqRedirect 111 storeQueue.io.flush <> io.flush 112 storeQueue.io.storeIn <> io.storeIn 113 storeQueue.io.sbuffer <> io.sbuffer 114 storeQueue.io.mmioStout <> io.mmioStout 115 storeQueue.io.roq <> io.roq 116 storeQueue.io.exceptionAddr.lsIdx := io.exceptionAddr.lsIdx 117 storeQueue.io.exceptionAddr.isStore := DontCare 118 storeQueue.io.issuePtrExt <> io.issuePtrExt 119 storeQueue.io.storeIssue <> io.storeIssue 120 121 loadQueue.io.load_s1 <> io.forward 122 storeQueue.io.forward <> io.forward // overlap forwardMask & forwardData, DO NOT CHANGE SEQUENCE 123 124 storeQueue.io.sqempty <> io.sqempty 125 126 if (!env.FPGAPlatform) { 127 difftestIO.fromSQ <> storeQueue.difftestIO 128 } 129 130 io.exceptionAddr.vaddr := Mux(io.exceptionAddr.isStore, storeQueue.io.exceptionAddr.vaddr, loadQueue.io.exceptionAddr.vaddr) 131 132 // naive uncache arbiter 133 val s_idle :: s_load :: s_store :: Nil = Enum(3) 134 val pendingstate = RegInit(s_idle) 135 136 switch(pendingstate){ 137 is(s_idle){ 138 when(io.uncache.req.fire()){ 139 pendingstate := Mux(loadQueue.io.uncache.req.valid, s_load, s_store) 140 } 141 } 142 is(s_load){ 143 when(io.uncache.resp.fire()){ 144 pendingstate := s_idle 145 } 146 } 147 is(s_store){ 148 when(io.uncache.resp.fire()){ 149 pendingstate := s_idle 150 } 151 } 152 } 153 154 loadQueue.io.uncache := DontCare 155 storeQueue.io.uncache := DontCare 156 loadQueue.io.uncache.resp.valid := false.B 157 storeQueue.io.uncache.resp.valid := false.B 158 when(loadQueue.io.uncache.req.valid){ 159 io.uncache.req <> loadQueue.io.uncache.req 160 }.otherwise{ 161 io.uncache.req <> storeQueue.io.uncache.req 162 } 163 when(pendingstate === s_load){ 164 io.uncache.resp <> loadQueue.io.uncache.resp 165 }.otherwise{ 166 io.uncache.resp <> storeQueue.io.uncache.resp 167 } 168 169 assert(!(loadQueue.io.uncache.req.valid && storeQueue.io.uncache.req.valid)) 170 assert(!(loadQueue.io.uncache.resp.valid && storeQueue.io.uncache.resp.valid)) 171 assert(!((loadQueue.io.uncache.resp.valid || storeQueue.io.uncache.resp.valid) && pendingstate === s_idle)) 172 173 io.lqFull := loadQueue.io.lqFull 174 io.sqFull := storeQueue.io.sqFull 175} 176