xref: /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala (revision 2225d46ebbe2fd16b9b29963c27a7d0385a42709) 
1package xiangshan.backend.fu
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3._
5import chisel3.util._
6import xiangshan._
7import utils._
8
9abstract class AbstractDivider(len: Int)(implicit p: Parameters) extends FunctionUnit(len){
10  val ctrl = IO(Input(new MulDivCtrl))
11  val sign = ctrl.sign
12}
13
14class Radix2Divider(len: Int)(implicit p: Parameters) extends AbstractDivider(len) {
15
16  def abs(a: UInt, sign: Bool): (Bool, UInt) = {
17    val s = a(len - 1) && sign
18    (s, Mux(s, -a, a))
19  }
20
21  val s_idle :: s_log2 :: s_shift :: s_compute :: s_finish :: Nil = Enum(5)
22  val state = RegInit(s_idle)
23  val newReq = (state === s_idle) && io.in.fire()
24
25  val (a, b) = (io.in.bits.src(0), io.in.bits.src(1))
26  val divBy0 = b === 0.U(len.W)
27  val divBy0Reg = RegEnable(divBy0, newReq)
28
29  val shiftReg = Reg(UInt((1 + len * 2).W))
30  val hi = shiftReg(len * 2, len)
31  val lo = shiftReg(len - 1, 0)
32
33  val uop = io.in.bits.uop
34
35  val (aSign, aVal) = abs(a, sign)
36  val (bSign, bVal) = abs(b, sign)
37  val aSignReg = RegEnable(aSign, newReq)
38  val qSignReg = RegEnable((aSign ^ bSign) && !divBy0, newReq)
39  val bReg = RegEnable(bVal, newReq)
40  val aValx2Reg = RegEnable(Cat(aVal, "b0".U), newReq)
41  val ctrlReg = RegEnable(ctrl, newReq)
42  val uopReg = RegEnable(uop, newReq)
43
44  val cnt = Counter(len)
45  when (newReq && !io.in.bits.uop.roqIdx.needFlush(io.redirectIn, io.flushIn)) {
46    state := s_log2
47  } .elsewhen (state === s_log2) {
48    // `canSkipShift` is calculated as following:
49    //   bEffectiveBit = Log2(bVal, XLEN) + 1.U
50    //   aLeadingZero = 64.U - aEffectiveBit = 64.U - (Log2(aVal, XLEN) + 1.U)
51    //   canSkipShift = aLeadingZero + bEffectiveBit
52    //     = 64.U - (Log2(aVal, XLEN) + 1.U) + Log2(bVal, XLEN) + 1.U
53    //     = 64.U + Log2(bVal, XLEN) - Log2(aVal, XLEN)
54    //     = (64.U | Log2(bVal, XLEN)) - Log2(aVal, XLEN)  // since Log2(bVal, XLEN) < 64.U
55    val canSkipShift = (64.U | Log2(bReg)) - Log2(aValx2Reg)
56    // When divide by 0, the quotient should be all 1's.
57    // Therefore we can not shift in 0s here.
58    // We do not skip any shift to avoid this.
59    cnt.value := Mux(divBy0Reg, 0.U, Mux(canSkipShift >= (len-1).U, (len-1).U, canSkipShift))
60    state := s_shift
61  } .elsewhen (state === s_shift) {
62    shiftReg := aValx2Reg << cnt.value
63    state := s_compute
64  } .elsewhen (state === s_compute) {
65    val enough = hi.asUInt >= bReg.asUInt
66    shiftReg := Cat(Mux(enough, hi - bReg, hi)(len - 1, 0), lo, enough)
67    cnt.inc()
68    when (cnt.value === (len-1).U) { state := s_finish }
69  } .elsewhen (state === s_finish) {
70    when(io.out.ready){
71      state := s_idle
72    }
73  }
74
75  val kill = state=/=s_idle && uopReg.roqIdx.needFlush(io.redirectIn, io.flushIn)
76  when(kill){
77    state := s_idle
78  }
79
80  val r = hi(len, 1)
81  val resQ = Mux(qSignReg, -lo, lo)
82  val resR = Mux(aSignReg, -r, r)
83
84  val xlen = io.out.bits.data.getWidth
85  val res = Mux(ctrlReg.isHi, resR, resQ)
86  io.out.bits.data := Mux(ctrlReg.isW, SignExt(res(31,0),xlen), res)
87  io.out.bits.uop := uopReg
88
89  io.out.valid := state === s_finish
90  io.in.ready := state === s_idle
91}
92