| d011b690 | 24-Apr-2025 |
Ma-YX <[email protected]> |
submodule(CoupledL2): bump CoupledL2 (#4616)
Bump CoupledL2, this pr includes:
1. set data SRAM's dataSplit = 8
* Set data SRAM(`dataArray` in `DataStorage`) dataSplit = 8.
Previously the dataSpl
submodule(CoupledL2): bump CoupledL2 (#4616)
Bump CoupledL2, this pr includes:
1. set data SRAM's dataSplit = 8
* Set data SRAM(`dataArray` in `DataStorage`) dataSplit = 8.
Previously the dataSplit = 4 and encDataBankBits = 137,
due to area demand, the `dataArray` SRAM bankBits should
be 69. Therefore, after ECC encode, the data need further
split = 2, and add 0 padding(4 bits) each cache line.
* Avoid tag split when tag SRAM's `dataSplit` requirement cannot
be met. This occurs when L2 size changes or `dataSplit` changes
or address width.
* Parameterize Split of tag and data.
2. remove unused register of WriteEvictOrEvict logics
3. remove deprecated cache step
4. support parameterized addr width by cde
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|
| e5325730 | 15-Apr-2025 |
cz4e <[email protected]> |
fix(DFT): fix `DFT` cgen connection (#4565) |
| 553ca6a2 | 15-Apr-2025 |
Ma-YX <[email protected]> |
submodule(CoupledL2): bump CoupledL2 (#4562)
* L2 Cache tag split after ECC encode (dataSpilt=2)
encTag width = 38 (31+ 6+1)
* enable `cbo.inval` in CHI test |
| 30f35717 | 14-Apr-2025 |
cz4e <[email protected]> |
refactor(DFT): refactor `DFT` IO (#4530) |
| a74491fc | 07-Apr-2025 |
zhanglinjuan <[email protected]> |
submodule(CoupledL2): parameterize NS assignment (#4507)
This pull request parameterizes the NS (Non-Secure) field in the CHI
bus, making it configurable. By default, the NS field is set to 0
(Secur
submodule(CoupledL2): parameterize NS assignment (#4507)
This pull request parameterizes the NS (Non-Secure) field in the CHI
bus, making it configurable. By default, the NS field is set to 0
(Secure), allowing XiangShan core to function as a secure boot processor
in NoC. For systems that already utilize an MCU for secure boot, access
of XiangShan core should theoretically be non-secure. In the latter
cases, `ENABLE_NS=1` option should be added to the `make` compilation
command.
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|
| 602aa9f1 | 02-Apr-2025 |
cz4e <[email protected]> |
feat(Sram): add `SRAM_CTL` interface (#4474)
* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=
feat(Sram): add `SRAM_CTL` interface (#4474)
* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=1`
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|
| 0e64db5c | 28-Mar-2025 |
zhanglinjuan <[email protected]> |
submodule(CoupledL2): bump CoupledL2 (#4469)
This pull request includes bug fixes as follows:
- https://github.com/OpenXiangShan/CoupledL2/pull/387
- https://github.com/OpenXiangShan/CoupledL2/pull/
submodule(CoupledL2): bump CoupledL2 (#4469)
This pull request includes bug fixes as follows:
- https://github.com/OpenXiangShan/CoupledL2/pull/387
- https://github.com/OpenXiangShan/CoupledL2/pull/390
- https://github.com/OpenXiangShan/CoupledL2/pull/394
- https://github.com/OpenXiangShan/CoupledL2/pull/393
- https://github.com/OpenXiangShan/CoupledL2/pull/392
- https://github.com/OpenXiangShan/CoupledL2/pull/395
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|
| 38136347 | 24-Mar-2025 |
yulightenyu <[email protected]> |
fix(L2Top): connect cpu_halt port to l2 (#4446)
* add wfi state (cpu_halt) port to CoupledL2
* bump CoupledL2 with fix of wfi state checking before exit coherency |
| 42b75a59 | 11-Mar-2025 |
zhanglinjuan <[email protected]> |
submodule(CoupledL2): bump CoupledL2 (#4384)
This pull request includes bug fixes as follows:
- https://github.com/OpenXiangShan/CoupledL2/pull/372
- https://github.com/OpenXiangShan/CoupledL2/pull/
submodule(CoupledL2): bump CoupledL2 (#4384)
This pull request includes bug fixes as follows:
- https://github.com/OpenXiangShan/CoupledL2/pull/372
- https://github.com/OpenXiangShan/CoupledL2/pull/374
- https://github.com/OpenXiangShan/CoupledL2/pull/377
- https://github.com/OpenXiangShan/CoupledL2/pull/375
- https://github.com/OpenXiangShan/CoupledL2/pull/378
- https://github.com/OpenXiangShan/CoupledL2/pull/380
- https://github.com/OpenXiangShan/CoupledL2/pull/376
- https://github.com/OpenXiangShan/CoupledL2/pull/379
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|
| 4c916048 | 06-Mar-2025 |
yulightenyu <[email protected]> |
submodule(CoupledL2): add new feature of flush L2 all (#4362)
To support the power-down functionality of Core+L2,it is necessary to
flush the data in the L2 cache to the downstream memory and exit t
submodule(CoupledL2): add new feature of flush L2 all (#4362)
To support the power-down functionality of Core+L2,it is necessary to
flush the data in the L2 cache to the downstream memory and exit the
coherence network before power-down. Therefore, this feature has been
added in CoupledL2.
show more ...
|
| 0907eaa5 | 27-Feb-2025 |
zhanglinjuan <[email protected]> |
submodule(CoupledL2): bump CoupledL2 (#4325)
This pr fixes the following bugs:
- https://github.com/OpenXiangShan/CoupledL2/pull/368
- https://github.com/OpenXiangShan/CoupledL2/pull/369
- https:
submodule(CoupledL2): bump CoupledL2 (#4325)
This pr fixes the following bugs:
- https://github.com/OpenXiangShan/CoupledL2/pull/368
- https://github.com/OpenXiangShan/CoupledL2/pull/369
- https://github.com/OpenXiangShan/CoupledL2/pull/370
- https://github.com/OpenXiangShan/CoupledL2/pull/371
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|
| 4b2c87ba | 27-Feb-2025 |
梁森 Liang Sen <[email protected]> |
feat(dfx): integerate dfx components (#4312) |
| dda64e0c | 20-Feb-2025 |
Ma-YX <[email protected]> |
submodule(CoupledL2): bump CoupledL2 (#4298) |
| deb28c06 | 20-Feb-2025 |
zhanglinjuan <[email protected]> |
submodule(CoupledL2): bump CoupledL2 (#4291)
Co-authored-by: Kumonda221 <[email protected]> |
| aad61829 | 19-Feb-2025 |
Ma-YX <[email protected]> |
fix(Soc, CoupledL2): correct port width of CHI Issue C (#4290) |
| c41f725a | 11-Feb-2025 |
zhanglinjuan <[email protected]> |
submodule(CoupledL2): bump CoupledL2 (#4250)
This pr includes:
- https://github.com/OpenXiangShan/CoupledL2/pull/344
- https://github.com/OpenXiangShan/CoupledL2/pull/349
- https://github.com/OpenXi
submodule(CoupledL2): bump CoupledL2 (#4250)
This pr includes:
- https://github.com/OpenXiangShan/CoupledL2/pull/344
- https://github.com/OpenXiangShan/CoupledL2/pull/349
- https://github.com/OpenXiangShan/CoupledL2/pull/350
- https://github.com/OpenXiangShan/CoupledL2/pull/342
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|
| 5137113c | 22-Jan-2025 |
zhanglinjuan <[email protected]> |
submodule(CoupledL2): fix assertion of Poison (#4220) |
| 881e32f5 | 22-Jan-2025 |
Zifei Zhang <[email protected]> |
submodule(CoupledL2, OpenLLC): bump L2 and LLC (#4189)
This pull request includes:
- add compilation support for CHI Issue C (but not yet verified)
- enable DataCheck and Poison
- add requirement fo
submodule(CoupledL2, OpenLLC): bump L2 and LLC (#4189)
This pull request includes:
- add compilation support for CHI Issue C (but not yet verified)
- enable DataCheck and Poison
- add requirement for CHI port width check
- add prefetch control by custom csr
- optimize timing in CoupledL2, mainly paths from SRAM to ICG
- add clock gate to each of the splitted SRAMs in CoupledL2
- fix several bugs concerning WriteEvictOrEvict, SnpQuery,
SnpCleanShared, SnpStash*, etc
---------
Co-authored-by: zhanglinjuan <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: Yanqin Li <[email protected]>
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|
| e836c770 | 16-Jan-2025 |
Zhaoyang You <[email protected]> |
feat(TopDown): add TopDown PMU Events (#4122)
This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bo
feat(TopDown): add TopDown PMU Events (#4122)
This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bound.
Level-2: Fetch Latency Bound, Fetch Bandwidth Bound, Branch
Missprediction, machine clears, Core Bound, Memory Bound.
Leval-3: L1 Bound, L2 Bound, L3 Bound, Mem Bound, Store Bound.
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|
| 77733a7b | 07-Jan-2025 |
Yanqin Li <[email protected]> |
submodule(CoupledL2): bump CoupledL2 (#4140)
1. https://github.com/OpenXiangShan/CoupledL2/pull/309
2. https://github.com/OpenXiangShan/CoupledL2/pull/312 |
| ae396931 | 02-Jan-2025 |
Yanqin Li <[email protected]> |
submodule(CoupledL2): bump for bop mem check (#4115) |
| 519244c7 | 25-Dec-2024 |
Yanqin Li <[email protected]> |
submodule(CoupledL2, OpenLLC): support pbmt in CHI scene (#4071)
* L1: deliver the NC and PMA signals of uncacheReq to L2
* L2: [support Svpbmt on CHI
MemAttr](https://github.com/OpenXiangShan/Coupl
submodule(CoupledL2, OpenLLC): support pbmt in CHI scene (#4071)
* L1: deliver the NC and PMA signals of uncacheReq to L2
* L2: [support Svpbmt on CHI
MemAttr](https://github.com/OpenXiangShan/CoupledL2/pull/273)
* LLC: [Non-cache requests are forwarded directly downstream without
entering the slice](https://github.com/OpenXiangShan/OpenLLC/pull/28)
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|
| 94aa21c6 | 24-Dec-2024 |
Yanqin Li <[email protected]> |
submodule(CoupledL2): add vaddr pmp af check for BOP (#4065) |
| 38d0d7c5 | 13-Dec-2024 |
zhanglinjuan <[email protected]> |
submodule(CoupledL2): bump CoupledL2 (#4034)
This commit includes:
- https://github.com/OpenXiangShan/CoupledL2/pull/296
- https://github.com/OpenXiangShan/CoupledL2/pull/297 |
| 991a33f0 | 10-Dec-2024 |
Ding Haonan <[email protected]> |
submodule(CoupledL2): fix bugs in CMO (#4011) |