xref: /XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala (revision 94aa21c6009c2f39c5c5dae9c87260c78887efcc) 
1package xiangshan.backend.decode.isa.bitfield
2
3import chisel3._
4import chisel3.util.BitPat
5
6abstract class RiscvInst(bitWidth: Int) extends Bundle {
7  val inst: UInt = UInt(bitWidth.W)
8}
9
10class Riscv32BitInst extends RiscvInst(32) {
11  def ALL       : UInt  = inst
12  def OPCODE    : UInt  = inst( 6,  0)
13  def RD        : UInt  = inst(11,  7)
14  def FUNCT3    : UInt  = inst(14, 12)
15  def RS1       : UInt  = inst(19, 15)
16  def RS2       : UInt  = inst(24, 20)
17  def FUNCT7    : UInt  = inst(31, 25)
18  def OPCODE5Bit: UInt  = inst( 6,  2)
19  def OPCODE7Bit: UInt  = inst( 6,  0)
20
21  // Not handle illegal instr in this function
22  def isAMOCAS = {
23    this.OPCODE5Bit === xiangshan.backend.decode.isa.bitfield.OPCODE5Bit.AMO &&
24      this.FUNCT7 === BitPat("b00101??")
25  }
26}
27
28trait BitFieldsI { this: Riscv32BitInst =>
29  def IMM12   : UInt  = inst(31, 20)
30  def SHAMT6  : UInt  = inst(25, 20)
31  def SHAMT5  : UInt  = inst(24, 20)
32}
33
34trait BitFieldsS { this: Riscv32BitInst =>
35  def IMM5    : UInt  = inst(11,  7)
36  def IMM7    : UInt  = inst(31, 25)
37}
38
39trait BitFieldsCSR { this: Riscv32BitInst =>
40  def CSRIDX  : UInt  = inst(31, 20)
41  def CSRIMM  : UInt  = inst(19, 15)
42}
43
44trait BitFieldsFp { this: Riscv32BitInst =>
45  def FD      : UInt  = inst(11,  7)
46  def FS1     : UInt  = inst(19, 15)
47  def FS2     : UInt  = inst(24, 20)
48  def FS3     : UInt  = inst(31, 27)
49  def RM      : UInt  = inst(14, 12) // round mode
50  def CONV_SGN: UInt  = inst(24, 20)
51  def FMT     : UInt  = inst(26, 25)
52  def TYP     : UInt  = inst(21, 20)
53}
54
55trait BitFieldsVec { this: Riscv32BitInst =>
56  def VCATEGORY     : UInt  = inst(14, 12)
57  def NF            : UInt  = inst(31, 29)
58  def MEW           : UInt  = inst(28)
59  def MOP           : UInt  = inst(27, 26)
60  def VM            : UInt  = inst(25)
61  def LUMOP         : UInt  = inst(24, 20)
62  def SUMOP         : UInt  = inst(24, 20)
63  def WIDTH         : UInt  = inst(14, 12)
64  def VD            : UInt  = inst(11,  7)
65  def VS1           : UInt  = inst(19, 15)
66  def VS2           : UInt  = inst(24, 20)
67  def VS3           : UInt  = inst(11,  7)
68  def FUNCT6        : UInt  = inst(31 ,26)
69  def ZIMM_VSETVLI  : UInt  = inst(30, 20)
70  def ZIMM_VSETIVLI : UInt  = inst(29, 20)
71  def UIMM_VSETIVLI : UInt  = inst(19, 15)
72  def IMM5_OPIVI    : UInt  = inst(19, 15)
73
74  def getInstVType : InstVType = {
75    val res = Wire(new InstVType)
76    res.vlmul := ZIMM_VSETVLI(2, 0)
77    res.vsew  := ZIMM_VSETVLI(5, 3)
78    res.vta   := ZIMM_VSETVLI(6)
79    res.vma   := ZIMM_VSETVLI(7)
80    res
81  }
82
83  def isVecStore = {
84    this.OPCODE5Bit === xiangshan.backend.decode.isa.bitfield.OPCODE5Bit.STORE_FP &&
85      (this.WIDTH === 0.U || this.WIDTH(2) === 1.B)
86  }
87
88  def isVecLoad = {
89    this.OPCODE5Bit === xiangshan.backend.decode.isa.bitfield.OPCODE5Bit.LOAD_FP &&
90      (this.WIDTH === 0.U || this.WIDTH(2) === 1.B)
91  }
92
93  def isVecArith = {
94    this.OPCODE5Bit === xiangshan.backend.decode.isa.bitfield.OPCODE5Bit.OP_V
95  }
96
97  def isOPIVV = {
98    this.OPCODE === xiangshan.backend.decode.isa.bitfield.OPCODE7Bit.VECTOR_ARITH &&
99      this.FUNCT3 === "b000".U
100  }
101
102  def isOPFVV = {
103    this.OPCODE === xiangshan.backend.decode.isa.bitfield.OPCODE7Bit.VECTOR_ARITH &&
104      this.FUNCT3 === "b001".U
105  }
106
107  def isOPMVV = {
108    this.OPCODE === xiangshan.backend.decode.isa.bitfield.OPCODE7Bit.VECTOR_ARITH &&
109      this.FUNCT3 === "b010".U
110  }
111
112  def isOPIVI= {
113    this.OPCODE === xiangshan.backend.decode.isa.bitfield.OPCODE7Bit.VECTOR_ARITH &&
114      this.FUNCT3 === "b011".U
115  }
116
117  def isOPIVX = {
118    this.OPCODE === xiangshan.backend.decode.isa.bitfield.OPCODE7Bit.VECTOR_ARITH &&
119      this.FUNCT3 === "b100".U
120  }
121
122  def isOPFVF = {
123    this.OPCODE === xiangshan.backend.decode.isa.bitfield.OPCODE7Bit.VECTOR_ARITH &&
124      this.FUNCT3 === "b101".U
125  }
126
127  def isOPMVX = {
128    this.OPCODE === xiangshan.backend.decode.isa.bitfield.OPCODE7Bit.VECTOR_ARITH &&
129      this.FUNCT3 === "b110".U
130  }
131}
132
133trait BitFieldsRVK { this: Riscv32BitInst =>
134  def RNUM          : UInt = inst(23, 20)
135
136  def isRnumIllegal = {
137    this.RNUM > 0xA.U
138  }
139}
140
141class XSInstBitFields extends Riscv32BitInst
142  with BitFieldsI
143  with BitFieldsS
144  with BitFieldsCSR
145  with BitFieldsFp
146  with BitFieldsVec
147  with BitFieldsRVK
148
149class InstVType extends Bundle {
150  val reserved = UInt(3.W)
151  val vma = Bool()
152  val vta = Bool()
153  val vsew = UInt(3.W)
154  val vlmul = UInt(3.W)
155}
156
157object OPCODE5Bit {
158  val LOAD      = "b00_000".U
159  val LOAD_FP   = "b00_001".U
160  val CUSTOM_0  = "b00_010".U
161  val MSIC_MEM  = "b00_011".U
162  val OP_IMM    = "b00_100".U
163  val AUIPC     = "b00_101".U
164  val OP_IMM_32 = "b00_110".U
165  val INST48b_0 = "b00_111".U
166
167  val STORE     = "b01_000".U
168  val STORE_FP  = "b01_001".U
169  val CUSTOM_1  = "b01_010".U
170  val AMO       = "b01_011".U
171  val OP        = "b01_100".U
172  val LUI       = "b01_101".U
173  val OP_32     = "b01_110".U
174  val INST64b   = "b01_111".U
175
176  val MADD      = "b10_000".U
177  val MSUB      = "b10_001".U
178  val NMSUB     = "b10_010".U
179  val NMADD     = "b10_011".U
180  val OP_FP     = "b10_100".U
181  val OP_V      = "b10_101".U
182  val CUSTOM_2  = "b10_110".U
183  val INST48b_1 = "b10_111".U
184
185  val BRANCH     = "b11_000".U
186  val JALR       = "b11_001".U
187  val RESERVED_0 = "b11_010".U
188  val JAL        = "b11_011".U
189  val SYSTEM     = "b11_100".U
190  val RESERVED_1 = "b11_101".U
191  val CUSTOM_3   = "b11_110".U
192  val INSTge80b  = "b11_111".U
193}
194
195object OPCODE7Bit {
196  val VECTOR_ARITH = "b1010111".U
197}
198