xref: /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala (revision 94aa21c6009c2f39c5c5dae9c87260c78887efcc)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15*
16*
17* Acknowledgement
18*
19* This implementation is inspired by several key papers:
20* [1] James E. Smith, and Andrew R. Pleszkun. "[Implementation of precise interrupts in pipelined processors.]
21* (https://dl.acm.org/doi/10.5555/327010.327125)" 12th Annual International Symposium on Computer Architecture (ISCA).
22* 1985.
23***************************************************************************************/
24
25package xiangshan.backend.rob
26
27import org.chipsalliance.cde.config.Parameters
28import chisel3._
29import chisel3.util._
30import chisel3.experimental.BundleLiterals._
31import difftest._
32import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
33import utility._
34import utils._
35import xiangshan._
36import xiangshan.backend.GPAMemEntry
37import xiangshan.backend.{BackendParams, RatToVecExcpMod, RegWriteFromRab, VecExcpInfo}
38import xiangshan.backend.Bundles.{DynInst, ExceptionInfo, ExuOutput}
39import xiangshan.backend.fu.{FuConfig, FuType}
40import xiangshan.frontend.FtqPtr
41import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr}
42import xiangshan.backend.Bundles.{DynInst, ExceptionInfo, ExuOutput}
43import xiangshan.backend.ctrlblock.{DebugLSIO, DebugLsInfo, LsTopdownInfo}
44import xiangshan.backend.fu.vector.Bundles.VType
45import xiangshan.backend.rename.SnapshotGenerator
46import yunsuan.VfaluType
47import xiangshan.backend.rob.RobBundles._
48import xiangshan.backend.trace._
49import chisel3.experimental.BundleLiterals._
50
51class Rob(params: BackendParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
52  override def shouldBeInlined: Boolean = false
53
54  lazy val module = new RobImp(this)(p, params)
55}
56
57class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendParams) extends LazyModuleImp(wrapper)
58  with HasXSParameter with HasCircularQueuePtrHelper with HasPerfEvents with HasCriticalErrors {
59
60  private val LduCnt = params.LduCnt
61  private val StaCnt = params.StaCnt
62  private val HyuCnt = params.HyuCnt
63
64  val io = IO(new Bundle() {
65    val hartId = Input(UInt(hartIdLen.W))
66    val redirect = Input(Valid(new Redirect))
67    val enq = new RobEnqIO
68    val flushOut = ValidIO(new Redirect)
69    val exception = ValidIO(new ExceptionInfo)
70    // exu + brq
71    val writeback: MixedVec[ValidIO[ExuOutput]] = Flipped(params.genWrite2CtrlBundles)
72    val exuWriteback: MixedVec[ValidIO[ExuOutput]] = Flipped(params.genWrite2CtrlBundles)
73    val writebackNums = Flipped(Vec(writeback.size - params.StdCnt, ValidIO(UInt(writeback.size.U.getWidth.W))))
74    val writebackNeedFlush = Input(Vec(params.allExuParams.filter(_.needExceptionGen).length, Bool()))
75    val commits = Output(new RobCommitIO)
76    val trace = new Bundle {
77      val blockCommit = Input(Bool())
78      val traceCommitInfo = new TraceBundle(hasIaddr = false, CommitWidth, IretireWidthInPipe)
79    }
80    val rabCommits = Output(new RabCommitIO)
81    val diffCommits = if (backendParams.basicDebugEn) Some(Output(new DiffCommitIO)) else None
82    val isVsetFlushPipe = Output(Bool())
83    val lsq = new RobLsqIO
84    val robDeqPtr = Output(new RobPtr)
85    val csr = new RobCSRIO
86    val snpt = Input(new SnapshotPort)
87    val robFull = Output(Bool())
88    val headNotReady = Output(Bool())
89    val cpu_halt = Output(Bool())
90    val wfi_enable = Input(Bool())
91    val toDecode = new Bundle {
92      val isResumeVType = Output(Bool())
93      val walkToArchVType = Output(Bool())
94      val walkVType = ValidIO(VType())
95      val commitVType = new Bundle {
96        val vtype = ValidIO(VType())
97        val hasVsetvl = Output(Bool())
98      }
99    }
100    val fromVecExcpMod = Input(new Bundle {
101      val busy = Bool()
102    })
103    val readGPAMemAddr = ValidIO(new Bundle {
104      val ftqPtr = new FtqPtr()
105      val ftqOffset = UInt(log2Up(PredictWidth).W)
106    })
107    val readGPAMemData = Input(new GPAMemEntry)
108    val vstartIsZero = Input(Bool())
109
110    val toVecExcpMod = Output(new Bundle {
111      val logicPhyRegMap = Vec(RabCommitWidth, ValidIO(new RegWriteFromRab))
112      val excpInfo = ValidIO(new VecExcpInfo)
113    })
114    val debug_ls = Flipped(new DebugLSIO)
115    val debugRobHead = Output(new DynInst)
116    val debugEnqLsq = Input(new LsqEnqIO)
117    val debugHeadLsIssue = Input(Bool())
118    val lsTopdownInfo = Vec(LduCnt + HyuCnt, Input(new LsTopdownInfo))
119    val debugTopDown = new Bundle {
120      val toCore = new RobCoreTopDownIO
121      val toDispatch = new RobDispatchTopDownIO
122      val robHeadLqIdx = Valid(new LqPtr)
123    }
124    val debugRolling = new RobDebugRollingIO
125
126    // store event difftest information
127    val storeDebugInfo = Vec(EnsbufferWidth, new Bundle {
128      val robidx = Input(new RobPtr)
129      val pc     = Output(UInt(VAddrBits.W))
130    })
131  })
132
133  val exuWBs: Seq[ValidIO[ExuOutput]] = io.exuWriteback.filter(!_.bits.params.hasStdFu).toSeq
134  val stdWBs: Seq[ValidIO[ExuOutput]] = io.exuWriteback.filter(_.bits.params.hasStdFu).toSeq
135  val fflagsWBs = io.exuWriteback.filter(x => x.bits.fflags.nonEmpty).toSeq
136  val exceptionWBs = io.writeback.filter(x => x.bits.exceptionVec.nonEmpty).toSeq
137  val redirectWBs = io.writeback.filter(x => x.bits.redirect.nonEmpty).toSeq
138  val vxsatWBs = io.exuWriteback.filter(x => x.bits.vxsat.nonEmpty).toSeq
139  val branchWBs = io.exuWriteback.filter(_.bits.params.hasBrhFu).toSeq
140  val csrWBs = io.exuWriteback.filter(x => x.bits.params.hasCSR).toSeq
141
142  val numExuWbPorts = exuWBs.length
143  val numStdWbPorts = stdWBs.length
144  val bankAddrWidth = log2Up(CommitWidth)
145
146  println(s"Rob: size $RobSize, numExuWbPorts: $numExuWbPorts, numStdWbPorts: $numStdWbPorts, commitwidth: $CommitWidth")
147
148  val rab = Module(new RenameBuffer(RabSize))
149  val vtypeBuffer = Module(new VTypeBuffer(VTypeBufferSize))
150  val bankNum = 8
151  assert(RobSize % bankNum == 0, "RobSize % bankNum must be 0")
152  val robEntries = RegInit(VecInit.fill(RobSize)((new RobEntryBundle).Lit(_.valid -> false.B)))
153  // pointers
154  // For enqueue ptr, we don't duplicate it since only enqueue needs it.
155  val enqPtrVec = Wire(Vec(RenameWidth, new RobPtr))
156  val deqPtrVec = Wire(Vec(CommitWidth, new RobPtr))
157  val deqPtrVec_next = Wire(Vec(CommitWidth, Output(new RobPtr)))
158  val walkPtrVec = Reg(Vec(CommitWidth, new RobPtr))
159  val walkPtrTrue = Reg(new RobPtr)
160  val lastWalkPtr = Reg(new RobPtr)
161  val allowEnqueue = RegInit(true.B)
162  val allowEnqueueForDispatch = RegInit(true.B)
163  val vecExcpInfo = RegInit(ValidIO(new VecExcpInfo).Lit(
164    _.valid -> false.B,
165  ))
166
167  /**
168   * Enqueue (from dispatch)
169   */
170  // special cases
171  val hasBlockBackward = RegInit(false.B)
172  val hasWaitForward = RegInit(false.B)
173  val doingSvinval = RegInit(false.B)
174  val enqPtr = enqPtrVec(0)
175  val deqPtr = deqPtrVec(0)
176  val walkPtr = walkPtrVec(0)
177  val allocatePtrVec = VecInit((0 until RenameWidth).map(i => enqPtrVec(PopCount(io.enq.req.take(i).map(req => req.valid && req.bits.firstUop)))))
178  io.enq.canAccept := allowEnqueue && !hasBlockBackward && rab.io.canEnq && vtypeBuffer.io.canEnq && !io.fromVecExcpMod.busy
179  io.enq.canAcceptForDispatch := allowEnqueueForDispatch && !hasBlockBackward && rab.io.canEnqForDispatch && vtypeBuffer.io.canEnqForDispatch && !io.fromVecExcpMod.busy
180  io.enq.resp := allocatePtrVec
181  val canEnqueue = VecInit(io.enq.req.map(req => req.valid && req.bits.firstUop && io.enq.canAccept))
182  val timer = GTimer()
183  // robEntries enqueue
184  for (i <- 0 until RobSize) {
185    val enqOH = VecInit(canEnqueue.zip(allocatePtrVec.map(_.value === i.U)).map(x => x._1 && x._2))
186    assert(PopCount(enqOH) < 2.U, s"robEntries$i enqOH is not one hot")
187    when(enqOH.asUInt.orR && !io.redirect.valid){
188      connectEnq(robEntries(i), Mux1H(enqOH, io.enq.req.map(_.bits)))
189    }
190  }
191  // robBanks0 include robidx : 0 8 16 24 32 ...
192  val robBanks = VecInit((0 until bankNum).map(i => VecInit(robEntries.zipWithIndex.filter(_._2 % bankNum == i).map(_._1))))
193  // each Bank has 20 Entries, read addr is one hot
194  // all banks use same raddr
195  val eachBankEntrieNum = robBanks(0).length
196  val robBanksRaddrThisLine = RegInit(1.U(eachBankEntrieNum.W))
197  val robBanksRaddrNextLine = Wire(UInt(eachBankEntrieNum.W))
198  robBanksRaddrThisLine := robBanksRaddrNextLine
199  val bankNumWidth = log2Up(bankNum)
200  val deqPtrWidth = deqPtr.value.getWidth
201  val robIdxThisLine = VecInit((0 until bankNum).map(i => Cat(deqPtr.value(deqPtrWidth - 1, bankNumWidth), i.U(bankNumWidth.W))))
202  val robIdxNextLine = VecInit((0 until bankNum).map(i => Cat(deqPtr.value(deqPtrWidth - 1, bankNumWidth) + 1.U, i.U(bankNumWidth.W))))
203  // robBanks read
204  val robBanksRdataThisLine = VecInit(robBanks.map{ case bank =>
205    Mux1H(robBanksRaddrThisLine, bank)
206  })
207  val robBanksRdataNextLine = VecInit(robBanks.map{ case bank =>
208    val shiftBank = bank.drop(1) :+ bank(0)
209    Mux1H(robBanksRaddrThisLine, shiftBank)
210  })
211  val robBanksRdataThisLineUpdate = Wire(Vec(CommitWidth, new RobEntryBundle))
212  val robBanksRdataNextLineUpdate = Wire(Vec(CommitWidth, new RobEntryBundle))
213  val commitValidThisLine = Wire(Vec(CommitWidth, Bool()))
214  val hasCommitted = RegInit(VecInit(Seq.fill(CommitWidth)(false.B)))
215  val donotNeedWalk = RegInit(VecInit(Seq.fill(CommitWidth)(false.B)))
216  val allCommitted = Wire(Bool())
217
218  when(allCommitted) {
219    hasCommitted := 0.U.asTypeOf(hasCommitted)
220  }.elsewhen(io.commits.isCommit){
221    for (i <- 0 until CommitWidth){
222      hasCommitted(i) := commitValidThisLine(i) || hasCommitted(i)
223    }
224  }
225  allCommitted := io.commits.isCommit && commitValidThisLine.last
226  val walkPtrHead = Wire(new RobPtr)
227  val changeBankAddrToDeqPtr = (walkPtrVec.head + CommitWidth.U) > lastWalkPtr
228  when(io.redirect.valid){
229    robBanksRaddrNextLine := UIntToOH(walkPtrHead.value(walkPtrHead.value.getWidth-1, bankAddrWidth))
230  }.elsewhen(allCommitted || io.commits.isWalk && !changeBankAddrToDeqPtr){
231    robBanksRaddrNextLine := Mux(robBanksRaddrThisLine.head(1) === 1.U, 1.U, robBanksRaddrThisLine << 1)
232  }.elsewhen(io.commits.isWalk && changeBankAddrToDeqPtr){
233    robBanksRaddrNextLine := UIntToOH(deqPtr.value(deqPtr.value.getWidth-1, bankAddrWidth))
234  }.otherwise(
235    robBanksRaddrNextLine := robBanksRaddrThisLine
236  )
237  val robDeqGroup = Reg(Vec(bankNum, new RobCommitEntryBundle))
238  val rawInfo = VecInit((0 until CommitWidth).map(i => robDeqGroup(deqPtrVec(i).value(bankAddrWidth-1, 0)))).toSeq
239  val commitInfo = VecInit((0 until CommitWidth).map(i => robDeqGroup(deqPtrVec(i).value(bankAddrWidth-1,0)))).toSeq
240  val walkInfo = VecInit((0 until CommitWidth).map(i => robDeqGroup(walkPtrVec(i).value(bankAddrWidth-1, 0)))).toSeq
241  for (i <- 0 until CommitWidth) {
242    connectCommitEntry(robDeqGroup(i), robBanksRdataThisLineUpdate(i))
243    when(allCommitted){
244      connectCommitEntry(robDeqGroup(i), robBanksRdataNextLineUpdate(i))
245    }
246  }
247
248  // In each robentry, the ftqIdx and ftqOffset belong to the first instruction that was compressed,
249  // That is Necessary when exceptions happen.
250  // Update the ftqOffset to correctly notify the frontend which instructions have been committed.
251  // Instructions in multiple Ftq entries compressed to one RobEntry do not occur.
252  for (i <- 0 until CommitWidth) {
253    val lastOffset = (rawInfo(i).traceBlockInPipe.iretire - (1.U << rawInfo(i).traceBlockInPipe.ilastsize.asUInt).asUInt) + rawInfo(i).ftqOffset
254    commitInfo(i).ftqOffset := Mux(CommitType.isFused(rawInfo(i).commitType), rawInfo(i).ftqOffset, lastOffset)
255  }
256
257  // data for debug
258  // Warn: debug_* prefix should not exist in generated verilog.
259  val debug_microOp = DebugMem(RobSize, new DynInst)
260  val debug_exuData = Reg(Vec(RobSize, UInt(XLEN.W))) //for debug
261  val debug_exuDebug = Reg(Vec(RobSize, new DebugBundle)) //for debug
262  val debug_lsInfo = RegInit(VecInit(Seq.fill(RobSize)(DebugLsInfo.init)))
263  val debug_lsTopdownInfo = RegInit(VecInit(Seq.fill(RobSize)(LsTopdownInfo.init)))
264  val debug_lqIdxValid = RegInit(VecInit.fill(RobSize)(false.B))
265  val debug_lsIssued = RegInit(VecInit.fill(RobSize)(false.B))
266
267  val isEmpty = enqPtr === deqPtr
268  val snptEnq = io.enq.canAccept && io.enq.req.map(x => x.valid && x.bits.snapshot).reduce(_ || _)
269  val snapshotPtrVec = Wire(Vec(CommitWidth, new RobPtr))
270  snapshotPtrVec(0) := io.enq.req(0).bits.robIdx
271  for (i <- 1 until CommitWidth) {
272    snapshotPtrVec(i) := snapshotPtrVec(0) + i.U
273  }
274  val snapshots = SnapshotGenerator(snapshotPtrVec, snptEnq, io.snpt.snptDeq, io.redirect.valid, io.snpt.flushVec)
275  val debug_lsIssue = WireDefault(debug_lsIssued)
276  debug_lsIssue(deqPtr.value) := io.debugHeadLsIssue
277
278  /**
279   * states of Rob
280   */
281  val s_idle :: s_walk :: Nil = Enum(2)
282  val state = RegInit(s_idle)
283  val state_next = Wire(chiselTypeOf(state))
284
285  val tip_computing :: tip_stalled :: tip_walk :: tip_drained :: Nil = Enum(4)
286  val tip_state = WireInit(0.U(4.W))
287  when(!isEmpty) {  // One or more inst in ROB
288    when(state === s_walk || io.redirect.valid) {
289      tip_state := tip_walk
290    }.elsewhen(io.commits.isCommit && PopCount(io.commits.commitValid) =/= 0.U) {
291      tip_state := tip_computing
292    }.otherwise {
293      tip_state := tip_stalled
294    }
295  }.otherwise {
296    tip_state := tip_drained
297  }
298  class TipEntry()(implicit p: Parameters) extends XSBundle {
299    val state = UInt(4.W)
300    val commits = new RobCommitIO()      // info of commit
301    val redirect = Valid(new Redirect)   // info of redirect
302    val redirect_pc = UInt(VAddrBits.W)  // PC of the redirect uop
303    val debugLsInfo = new DebugLsInfo()
304  }
305  val tip_table = ChiselDB.createTable("Tip_" + p(XSCoreParamsKey).HartId.toString, new TipEntry)
306  val tip_data = Wire(new TipEntry())
307  tip_data.state := tip_state
308  tip_data.commits := io.commits
309  tip_data.redirect := io.redirect
310  tip_data.redirect_pc := debug_microOp(io.redirect.bits.robIdx.value).pc
311  tip_data.debugLsInfo := debug_lsInfo(io.commits.robIdx(0).value)
312  tip_table.log(tip_data, true.B, "", clock, reset)
313
314  val exceptionGen = Module(new ExceptionGen(params))
315  val exceptionDataRead = exceptionGen.io.state
316  val fflagsDataRead = Wire(Vec(CommitWidth, UInt(5.W)))
317  val vxsatDataRead = Wire(Vec(CommitWidth, Bool()))
318  io.robDeqPtr := deqPtr
319  io.debugRobHead := debug_microOp(deqPtr.value)
320
321  /**
322   * connection of [[rab]]
323   */
324  rab.io.redirect.valid := io.redirect.valid
325
326  rab.io.req.zip(io.enq.req).map { case (dest, src) =>
327    dest.bits := src.bits
328    dest.valid := src.valid && io.enq.canAccept
329  }
330
331  val walkDestSizeDeqGroup = RegInit(VecInit(Seq.fill(CommitWidth)(0.U(log2Up(MaxUopSize + 1).W))))
332  val realDestSizeSeq = VecInit(robDeqGroup.zip(hasCommitted).map{case (r, h) => Mux(h, 0.U, r.realDestSize)})
333  val walkDestSizeSeq = VecInit(robDeqGroup.zip(donotNeedWalk).map{case (r, d) => Mux(d, 0.U, r.realDestSize)})
334  val commitSizeSumSeq = VecInit((0 until CommitWidth).map(i => realDestSizeSeq.take(i + 1).reduce(_ +& _)))
335  val walkSizeSumSeq   = VecInit((0 until CommitWidth).map(i => walkDestSizeSeq.take(i + 1).reduce(_ +& _)))
336  val commitSizeSumCond = VecInit(commitValidThisLine.zip(hasCommitted).map{case (c,h) => (c || h) && io.commits.isCommit})
337  val walkSizeSumCond   = VecInit(io.commits.walkValid.zip(donotNeedWalk).map{case (w,d) => (w || d) && io.commits.isWalk})
338  val commitSizeSum = PriorityMuxDefault(commitSizeSumCond.reverse.zip(commitSizeSumSeq.reverse), 0.U)
339  val walkSizeSum   = PriorityMuxDefault(walkSizeSumCond.reverse.zip(walkSizeSumSeq.reverse), 0.U)
340
341  val deqVlsExceptionNeedCommit = RegInit(false.B)
342  val deqVlsExceptionCommitSize = RegInit(0.U(log2Up(MaxUopSize + 1).W))
343  val deqVlsCanCommit= RegInit(false.B)
344  rab.io.fromRob.commitSize := Mux(deqVlsExceptionNeedCommit, deqVlsExceptionCommitSize, commitSizeSum)
345  rab.io.fromRob.walkSize := walkSizeSum
346  rab.io.fromRob.vecLoadExcp.valid := RegNext(exceptionDataRead.valid && exceptionDataRead.bits.isVecLoad)
347  rab.io.fromRob.vecLoadExcp.bits.isStrided := RegEnable(exceptionDataRead.bits.isStrided, exceptionDataRead.valid)
348  rab.io.fromRob.vecLoadExcp.bits.isVlm := RegEnable(exceptionDataRead.bits.isVlm, exceptionDataRead.valid)
349  rab.io.snpt := io.snpt
350  rab.io.snpt.snptEnq := snptEnq
351
352  // pipe rab commits for better timing and area
353  io.rabCommits := RegNext(rab.io.commits)
354  io.diffCommits.foreach(_ := rab.io.diffCommits.get)
355
356  /**
357   * connection of [[vtypeBuffer]]
358   */
359
360  vtypeBuffer.io.redirect.valid := io.redirect.valid
361
362  vtypeBuffer.io.req.zip(io.enq.req).map { case (sink, source) =>
363    sink.valid := source.valid && io.enq.canAccept
364    sink.bits := source.bits
365  }
366
367  private val commitIsVTypeVec = VecInit(io.commits.commitValid.zip(io.commits.info).map { case (valid, info) => io.commits.isCommit && valid && info.isVset })
368  private val walkIsVTypeVec = VecInit(io.commits.walkValid.zip(walkInfo).map { case (valid, info) => io.commits.isWalk && valid && info.isVset })
369  vtypeBuffer.io.fromRob.commitSize := PopCount(commitIsVTypeVec)
370  vtypeBuffer.io.fromRob.walkSize := PopCount(walkIsVTypeVec)
371  vtypeBuffer.io.snpt := io.snpt
372  vtypeBuffer.io.snpt.snptEnq := snptEnq
373  io.toDecode.isResumeVType := vtypeBuffer.io.toDecode.isResumeVType
374  io.toDecode.walkToArchVType := vtypeBuffer.io.toDecode.walkToArchVType
375  io.toDecode.commitVType := vtypeBuffer.io.toDecode.commitVType
376  io.toDecode.walkVType := vtypeBuffer.io.toDecode.walkVType
377
378  // When blockBackward instruction leaves Rob (commit or walk), hasBlockBackward should be set to false.B
379  // To reduce registers usage, for hasBlockBackward cases, we allow enqueue after ROB is empty.
380  when(isEmpty) {
381    hasBlockBackward := false.B
382  }
383  // When any instruction commits, hasNoSpecExec should be set to false.B
384  when(io.commits.hasWalkInstr || io.commits.hasCommitInstr) {
385    hasWaitForward := false.B
386  }
387
388  // The wait-for-interrupt (WFI) instruction waits in the ROB until an interrupt might need servicing.
389  // io.csr.wfiEvent will be asserted if the WFI can resume execution, and we change the state to s_wfi_idle.
390  // It does not affect how interrupts are serviced. Note that WFI is noSpecExec and it does not trigger interrupts.
391  val hasWFI = RegInit(false.B)
392  io.cpu_halt := hasWFI
393  // WFI Timeout: 2^20 = 1M cycles
394  val wfi_cycles = RegInit(0.U(20.W))
395  when(hasWFI) {
396    wfi_cycles := wfi_cycles + 1.U
397  }.elsewhen(!hasWFI && RegNext(hasWFI)) {
398    wfi_cycles := 0.U
399  }
400  val wfi_timeout = wfi_cycles.andR
401  when(RegNext(RegNext(io.csr.wfiEvent)) || io.flushOut.valid || wfi_timeout) {
402    hasWFI := false.B
403  }
404
405  for (i <- 0 until RenameWidth) {
406    // we don't check whether io.redirect is valid here since redirect has higher priority
407    when(canEnqueue(i)) {
408      val enqUop = io.enq.req(i).bits
409      val enqIndex = allocatePtrVec(i).value
410      // store uop in data module and debug_microOp Vec
411      debug_microOp(enqIndex) := enqUop
412      debug_microOp(enqIndex).debugInfo.dispatchTime := timer
413      debug_microOp(enqIndex).debugInfo.enqRsTime := timer
414      debug_microOp(enqIndex).debugInfo.selectTime := timer
415      debug_microOp(enqIndex).debugInfo.issueTime := timer
416      debug_microOp(enqIndex).debugInfo.writebackTime := timer
417      debug_microOp(enqIndex).debugInfo.tlbFirstReqTime := timer
418      debug_microOp(enqIndex).debugInfo.tlbRespTime := timer
419      debug_lsInfo(enqIndex) := DebugLsInfo.init
420      debug_lsTopdownInfo(enqIndex) := LsTopdownInfo.init
421      debug_lqIdxValid(enqIndex) := false.B
422      debug_lsIssued(enqIndex) := false.B
423      when (enqUop.waitForward) {
424        hasWaitForward := true.B
425      }
426      val enqTriggerActionIsDebugMode = TriggerAction.isDmode(io.enq.req(i).bits.trigger)
427      val enqHasException = ExceptionNO.selectFrontend(enqUop.exceptionVec).asUInt.orR
428      // the begin instruction of Svinval enqs so mark doingSvinval as true to indicate this process
429      when(!enqTriggerActionIsDebugMode && !enqHasException && enqUop.isSvinvalBegin(enqUop.flushPipe)) {
430        doingSvinval := true.B
431      }
432      // the end instruction of Svinval enqs so clear doingSvinval
433      when(!enqTriggerActionIsDebugMode && !enqHasException && enqUop.isSvinvalEnd(enqUop.flushPipe)) {
434        doingSvinval := false.B
435      }
436      // when we are in the process of Svinval software code area , only Svinval.vma and end instruction of Svinval can appear
437      assert(!doingSvinval || (enqUop.isSvinval(enqUop.flushPipe) || enqUop.isSvinvalEnd(enqUop.flushPipe) || enqUop.isNotSvinval))
438      when(enqUop.isWFI && !enqHasException && !enqTriggerActionIsDebugMode) {
439        hasWFI := true.B
440      }
441
442      robEntries(enqIndex).mmio := false.B
443      robEntries(enqIndex).vls := enqUop.vlsInstr
444    }
445  }
446
447  for (i <- 0 until RenameWidth) {
448    val enqUop = io.enq.req(i)
449    when(enqUop.valid && enqUop.bits.blockBackward && io.enq.canAccept) {
450      hasBlockBackward := true.B
451    }
452  }
453
454  val dispatchNum = Mux(io.enq.canAccept, PopCount(io.enq.req.map(req => req.valid && req.bits.firstUop)), 0.U)
455  io.enq.isEmpty := RegNext(isEmpty && !VecInit(io.enq.req.map(_.valid)).asUInt.orR)
456
457  when(!io.wfi_enable) {
458    hasWFI := false.B
459  }
460  // sel vsetvl's flush position
461  val vs_idle :: vs_waitVinstr :: vs_waitFlush :: Nil = Enum(3)
462  val vsetvlState = RegInit(vs_idle)
463
464  val firstVInstrFtqPtr = RegInit(0.U.asTypeOf(new FtqPtr))
465  val firstVInstrFtqOffset = RegInit(0.U.asTypeOf(UInt(log2Up(PredictWidth).W)))
466  val firstVInstrRobIdx = RegInit(0.U.asTypeOf(new RobPtr))
467
468  val enq0 = io.enq.req(0)
469  val enq0IsVset = enq0.bits.isVset && enq0.bits.lastUop && canEnqueue(0)
470  val enq0IsVsetFlush = enq0IsVset && enq0.bits.flushPipe
471  val enqIsVInstrVec = io.enq.req.zip(canEnqueue).map { case (req, fire) => FuType.isVArith(req.bits.fuType) && fire }
472  // for vs_idle
473  val firstVInstrIdle = PriorityMux(enqIsVInstrVec.zip(io.enq.req).drop(1) :+ (true.B, 0.U.asTypeOf(io.enq.req(0).cloneType)))
474  // for vs_waitVinstr
475  val enqIsVInstrOrVset = (enqIsVInstrVec(0) || enq0IsVset) +: enqIsVInstrVec.drop(1)
476  val firstVInstrWait = PriorityMux(enqIsVInstrOrVset, io.enq.req)
477  when(vsetvlState === vs_idle) {
478    firstVInstrFtqPtr := firstVInstrIdle.bits.ftqPtr
479    firstVInstrFtqOffset := firstVInstrIdle.bits.ftqOffset
480    firstVInstrRobIdx := firstVInstrIdle.bits.robIdx
481  }.elsewhen(vsetvlState === vs_waitVinstr) {
482    when(Cat(enqIsVInstrOrVset).orR) {
483      firstVInstrFtqPtr := firstVInstrWait.bits.ftqPtr
484      firstVInstrFtqOffset := firstVInstrWait.bits.ftqOffset
485      firstVInstrRobIdx := firstVInstrWait.bits.robIdx
486    }
487  }
488
489  val hasVInstrAfterI = Cat(enqIsVInstrVec(0)).orR
490  when(vsetvlState === vs_idle && !io.redirect.valid) {
491    when(enq0IsVsetFlush) {
492      vsetvlState := Mux(hasVInstrAfterI, vs_waitFlush, vs_waitVinstr)
493    }
494  }.elsewhen(vsetvlState === vs_waitVinstr) {
495    when(io.redirect.valid) {
496      vsetvlState := vs_idle
497    }.elsewhen(Cat(enqIsVInstrOrVset).orR) {
498      vsetvlState := vs_waitFlush
499    }
500  }.elsewhen(vsetvlState === vs_waitFlush) {
501    when(io.redirect.valid) {
502      vsetvlState := vs_idle
503    }
504  }
505
506  // lqEnq
507  io.debugEnqLsq.needAlloc.map(_(0)).zip(io.debugEnqLsq.req).foreach { case (alloc, req) =>
508    when(io.debugEnqLsq.canAccept && alloc && req.valid) {
509      debug_microOp(req.bits.robIdx.value).lqIdx := req.bits.lqIdx
510      debug_lqIdxValid(req.bits.robIdx.value) := true.B
511    }
512  }
513
514  // lsIssue
515  when(io.debugHeadLsIssue) {
516    debug_lsIssued(deqPtr.value) := true.B
517  }
518
519  /**
520   * Writeback (from execution units)
521   */
522  for (wb <- exuWBs) {
523    val wbIdx = wb.bits.robIdx.value
524    val debug_Uop = debug_microOp(wbIdx)
525    when(wb.valid) {
526      debug_exuData(wbIdx) := wb.bits.data(0)
527      debug_exuDebug(wbIdx) := wb.bits.debug
528      debug_microOp(wbIdx).debugInfo.enqRsTime := wb.bits.debugInfo.enqRsTime
529      debug_microOp(wbIdx).debugInfo.selectTime := wb.bits.debugInfo.selectTime
530      debug_microOp(wbIdx).debugInfo.issueTime := wb.bits.debugInfo.issueTime
531      debug_microOp(wbIdx).debugInfo.writebackTime := wb.bits.debugInfo.writebackTime
532
533      // debug for lqidx and sqidx
534      debug_microOp(wbIdx).lqIdx := wb.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr))
535      debug_microOp(wbIdx).sqIdx := wb.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr))
536    }
537    XSInfo(wb.valid,
538      p"writebacked pc 0x${Hexadecimal(debug_Uop.pc)} wen ${debug_Uop.rfWen} " +
539        p"data 0x${Hexadecimal(wb.bits.data(0))} ldst ${debug_Uop.ldest} pdst ${debug_Uop.pdest} " +
540        p"skip ${wb.bits.debug.isSkipDiff} robIdx: ${wb.bits.robIdx}\n"
541    )
542  }
543
544  val writebackNum = PopCount(exuWBs.map(_.valid))
545  XSInfo(writebackNum =/= 0.U, "writebacked %d insts\n", writebackNum)
546
547  for (i <- 0 until LoadPipelineWidth) {
548    when(RegNext(io.lsq.mmio(i))) {
549      robEntries(RegEnable(io.lsq.uop(i).robIdx, io.lsq.mmio(i)).value).mmio := true.B
550    }
551  }
552
553
554  /**
555   * RedirectOut: Interrupt and Exceptions
556   */
557  val debug_deqUop = debug_microOp(deqPtr.value)
558
559  val deqPtrEntry = rawInfo(0)
560  val deqPtrEntryValid = deqPtrEntry.commit_v
561  val deqHasFlushed = RegInit(false.B)
562  val intrBitSetReg = RegNext(io.csr.intrBitSet)
563  val intrEnable = intrBitSetReg && !hasWaitForward && deqPtrEntry.interrupt_safe && !deqHasFlushed
564  val deqNeedFlush = deqPtrEntry.needFlush && deqPtrEntry.commit_v && deqPtrEntry.commit_w
565  val deqHitExceptionGenState = exceptionDataRead.valid && exceptionDataRead.bits.robIdx === deqPtr
566  val deqNeedFlushAndHitExceptionGenState = deqNeedFlush && deqHitExceptionGenState
567  val exceptionGenStateIsException = exceptionDataRead.bits.exceptionVec.asUInt.orR || exceptionDataRead.bits.singleStep || TriggerAction.isDmode(exceptionDataRead.bits.trigger)
568  val deqHasException = deqNeedFlushAndHitExceptionGenState && exceptionGenStateIsException
569  val deqHasFlushPipe = deqNeedFlushAndHitExceptionGenState && exceptionDataRead.bits.flushPipe && !deqHasException && (!deqPtrEntry.isVls || RegNext(RegNext(deqPtrEntry.commit_w)))
570  val deqHasReplayInst = deqNeedFlushAndHitExceptionGenState && exceptionDataRead.bits.replayInst
571  val deqIsVlsException = deqHasException && deqPtrEntry.isVls && !exceptionDataRead.bits.isEnqExcp
572  // delay 2 cycle wait exceptionGen out
573  // vls exception can be committed only when RAB commit all its reg pairs
574  deqVlsCanCommit := RegNext(RegNext(deqIsVlsException && deqPtrEntry.commit_w)) && rab.io.status.commitEnd
575
576  // lock at assertion of deqVlsExceptionNeedCommit until condition not assert
577  val deqVlsExcpLock = RegInit(false.B)
578  val handleVlsExcp = deqIsVlsException && deqVlsCanCommit && !deqVlsExcpLock && state === s_idle
579  when(handleVlsExcp) {
580    deqVlsExcpLock := true.B
581  }.elsewhen(deqPtrVec.head =/= deqPtrVec_next.head) {
582    deqVlsExcpLock := false.B
583  }
584
585  // Only assert once when deqVlsExcp occurs until condition not assert to avoid multi message passed to RAB
586  when (deqVlsExceptionNeedCommit) {
587    deqVlsExceptionNeedCommit := false.B
588  }.elsewhen(handleVlsExcp){
589    deqVlsExceptionCommitSize := deqPtrEntry.realDestSize
590    deqVlsExceptionNeedCommit := true.B
591  }
592
593  XSDebug(deqHasException && exceptionDataRead.bits.singleStep, "Debug Mode: Deq has singlestep exception\n")
594  XSDebug(deqHasException && TriggerAction.isDmode(exceptionDataRead.bits.trigger), "Debug Mode: Deq has trigger entry debug Mode\n")
595
596  val isFlushPipe = deqPtrEntry.commit_w && (deqHasFlushPipe || deqHasReplayInst)
597
598  val isVsetFlushPipe = deqPtrEntry.commit_w && deqHasFlushPipe && exceptionDataRead.bits.isVset
599  //  val needModifyFtqIdxOffset = isVsetFlushPipe && (vsetvlState === vs_waitFlush)
600  val needModifyFtqIdxOffset = false.B
601  io.isVsetFlushPipe := isVsetFlushPipe
602  // io.flushOut will trigger redirect at the next cycle.
603  // Block any redirect or commit at the next cycle.
604  val lastCycleFlush = RegNext(io.flushOut.valid)
605
606  io.flushOut.valid := (state === s_idle) && deqPtrEntryValid && (intrEnable || deqHasException && (!deqIsVlsException || deqVlsCanCommit) || isFlushPipe) && !lastCycleFlush
607  io.flushOut.bits := DontCare
608  io.flushOut.bits.isRVC := deqPtrEntry.isRVC
609  io.flushOut.bits.robIdx := Mux(needModifyFtqIdxOffset, firstVInstrRobIdx, deqPtr)
610  io.flushOut.bits.ftqIdx := Mux(needModifyFtqIdxOffset, firstVInstrFtqPtr, deqPtrEntry.ftqIdx)
611  io.flushOut.bits.ftqOffset := Mux(needModifyFtqIdxOffset, firstVInstrFtqOffset, deqPtrEntry.ftqOffset)
612  io.flushOut.bits.level := Mux(deqHasReplayInst || intrEnable || deqHasException || needModifyFtqIdxOffset, RedirectLevel.flush, RedirectLevel.flushAfter) // TODO use this to implement "exception next"
613  io.flushOut.bits.interrupt := true.B
614  XSPerfAccumulate("interrupt_num", io.flushOut.valid && intrEnable)
615  XSPerfAccumulate("exception_num", io.flushOut.valid && deqHasException)
616  XSPerfAccumulate("flush_pipe_num", io.flushOut.valid && isFlushPipe)
617  XSPerfAccumulate("replay_inst_num", io.flushOut.valid && isFlushPipe && deqHasReplayInst)
618
619  val exceptionHappen = (state === s_idle) && deqPtrEntryValid && (intrEnable || deqHasException && (!deqIsVlsException || deqVlsCanCommit)) && !lastCycleFlush
620  io.exception.valid := RegNext(exceptionHappen)
621  io.exception.bits.pc := RegEnable(debug_deqUop.pc, exceptionHappen)
622  io.exception.bits.gpaddr := io.readGPAMemData.gpaddr
623  io.exception.bits.isForVSnonLeafPTE := io.readGPAMemData.isForVSnonLeafPTE
624  io.exception.bits.instr := RegEnable(debug_deqUop.instr, exceptionHappen)
625  io.exception.bits.commitType := RegEnable(deqPtrEntry.commitType, exceptionHappen)
626  io.exception.bits.exceptionVec := RegEnable(exceptionDataRead.bits.exceptionVec, exceptionHappen)
627  // fetch trigger fire or execute ebreak
628  io.exception.bits.isPcBkpt := RegEnable(
629    exceptionDataRead.bits.exceptionVec(ExceptionNO.EX_BP) && (
630      exceptionDataRead.bits.isEnqExcp ||
631      exceptionDataRead.bits.trigger === TriggerAction.None
632    ),
633    exceptionHappen,
634  )
635  io.exception.bits.isFetchMalAddr := RegEnable(exceptionDataRead.bits.isFetchMalAddr && deqHasException, exceptionHappen)
636  io.exception.bits.singleStep := RegEnable(exceptionDataRead.bits.singleStep, exceptionHappen)
637  io.exception.bits.crossPageIPFFix := RegEnable(exceptionDataRead.bits.crossPageIPFFix, exceptionHappen)
638  io.exception.bits.isInterrupt := RegEnable(intrEnable, exceptionHappen)
639  io.exception.bits.isHls := RegEnable(deqPtrEntry.isHls, exceptionHappen)
640  io.exception.bits.vls := RegEnable(deqPtrEntry.vls, exceptionHappen)
641  io.exception.bits.trigger := RegEnable(exceptionDataRead.bits.trigger, exceptionHappen)
642
643  // data will be one cycle after valid
644  io.readGPAMemAddr.valid := exceptionHappen
645  io.readGPAMemAddr.bits.ftqPtr := exceptionDataRead.bits.ftqPtr
646  io.readGPAMemAddr.bits.ftqOffset := exceptionDataRead.bits.ftqOffset
647
648  XSDebug(io.flushOut.valid,
649    p"generate redirect: pc 0x${Hexadecimal(io.exception.bits.pc)} intr $intrEnable " +
650      p"excp $deqHasException flushPipe $isFlushPipe " +
651      p"Trap_target 0x${Hexadecimal(io.csr.trapTarget.pc)} exceptionVec ${Binary(exceptionDataRead.bits.exceptionVec.asUInt)}\n")
652
653
654  /**
655   * Commits (and walk)
656   * They share the same width.
657   */
658  // T redirect.valid, T+1 use walkPtrVec read robEntries, T+2 start walk, shouldWalkVec used in T+2
659  val shouldWalkVec = Wire(Vec(CommitWidth,Bool()))
660  val walkingPtrVec = RegNext(walkPtrVec)
661  when(io.redirect.valid){
662    shouldWalkVec := 0.U.asTypeOf(shouldWalkVec)
663  }.elsewhen(RegNext(io.redirect.valid)){
664    shouldWalkVec := 0.U.asTypeOf(shouldWalkVec)
665  }.elsewhen(state === s_walk){
666    shouldWalkVec := VecInit(walkingPtrVec.map(_ <= lastWalkPtr).zip(donotNeedWalk).map(x => x._1 && !x._2))
667  }.otherwise(
668    shouldWalkVec := 0.U.asTypeOf(shouldWalkVec)
669  )
670  val walkFinished = walkPtrTrue > lastWalkPtr
671  rab.io.fromRob.walkEnd := state === s_walk && walkFinished
672  vtypeBuffer.io.fromRob.walkEnd := state === s_walk && walkFinished
673
674  require(RenameWidth <= CommitWidth)
675
676  // wiring to csr
677  val (wflags, dirtyFs) = (0 until CommitWidth).map(i => {
678    val v = io.commits.commitValid(i)
679    val info = io.commits.info(i)
680    (v & info.wflags, v & info.dirtyFs)
681  }).unzip
682  val fflags = Wire(Valid(UInt(5.W)))
683  fflags.valid := io.commits.isCommit && VecInit(wflags).asUInt.orR
684  fflags.bits := wflags.zip(fflagsDataRead).map({
685    case (w, f) => Mux(w, f, 0.U)
686  }).reduce(_ | _)
687  val dirtyVs = (0 until CommitWidth).map(i => {
688    val v = io.commits.commitValid(i)
689    val info = io.commits.info(i)
690    v & info.dirtyVs
691  })
692  val dirty_fs = io.commits.isCommit && VecInit(dirtyFs).asUInt.orR
693  val dirty_vs = io.commits.isCommit && VecInit(dirtyVs).asUInt.orR
694
695  val resetVstart = dirty_vs && !io.vstartIsZero
696
697  vecExcpInfo.valid := exceptionHappen && !intrEnable && exceptionDataRead.bits.vstartEn && exceptionDataRead.bits.isVecLoad && !exceptionDataRead.bits.isEnqExcp
698  when (exceptionHappen) {
699    vecExcpInfo.bits.nf := exceptionDataRead.bits.nf
700    vecExcpInfo.bits.vsew := exceptionDataRead.bits.vsew
701    vecExcpInfo.bits.veew := exceptionDataRead.bits.veew
702    vecExcpInfo.bits.vlmul := exceptionDataRead.bits.vlmul
703    vecExcpInfo.bits.isStride := exceptionDataRead.bits.isStrided
704    vecExcpInfo.bits.isIndexed := exceptionDataRead.bits.isIndexed
705    vecExcpInfo.bits.isWhole := exceptionDataRead.bits.isWhole
706    vecExcpInfo.bits.isVlm := exceptionDataRead.bits.isVlm
707    vecExcpInfo.bits.vstart := exceptionDataRead.bits.vstart
708  }
709
710  io.csr.vstart.valid := RegNext(Mux(exceptionHappen && deqHasException, exceptionDataRead.bits.vstartEn, resetVstart))
711  io.csr.vstart.bits := RegNext(Mux(exceptionHappen && deqHasException, exceptionDataRead.bits.vstart, 0.U))
712
713  val vxsat = Wire(Valid(Bool()))
714  vxsat.valid := io.commits.isCommit && vxsat.bits
715  vxsat.bits := io.commits.commitValid.zip(vxsatDataRead).map {
716    case (valid, vxsat) => valid & vxsat
717  }.reduce(_ | _)
718
719  // when mispredict branches writeback, stop commit in the next 2 cycles
720  // TODO: don't check all exu write back
721  val misPredWb = Cat(VecInit(redirectWBs.map(wb =>
722    wb.bits.redirect.get.bits.cfiUpdate.isMisPred && wb.bits.redirect.get.valid && wb.valid
723  ).toSeq)).orR
724  val misPredBlockCounter = Reg(UInt(3.W))
725  misPredBlockCounter := Mux(misPredWb,
726    "b111".U,
727    misPredBlockCounter >> 1.U
728  )
729  val misPredBlock = misPredBlockCounter(0)
730  val deqFlushBlockCounter = Reg(UInt(3.W))
731  val deqFlushBlock = deqFlushBlockCounter(0)
732  val deqHasCommitted = io.commits.isCommit && io.commits.commitValid(0)
733  // TODO *** WARNING ***
734  // Blocking commit. Don't change this before we fully understand the logic.
735  val deqHitRedirectReg = RegNext(io.redirect.valid && io.redirect.bits.robIdx === deqPtr) || RegNext(RegNext(io.redirect.valid && io.redirect.bits.robIdx === deqPtr))
736  val criticalErrorState = io.csr.criticalErrorState
737  when(deqNeedFlush && deqHitRedirectReg){
738    deqFlushBlockCounter := "b111".U
739  }.otherwise{
740    deqFlushBlockCounter := deqFlushBlockCounter >> 1.U
741  }
742  when(deqHasCommitted){
743    deqHasFlushed := false.B
744  }.elsewhen(deqNeedFlush && io.flushOut.valid && !io.flushOut.bits.flushItself()){
745    deqHasFlushed := true.B
746  }
747  val traceBlock = io.trace.blockCommit
748  val blockCommit = misPredBlock || lastCycleFlush || hasWFI || io.redirect.valid ||
749    (deqNeedFlush && !deqHasFlushed) || deqFlushBlock || criticalErrorState || traceBlock
750
751  io.commits.isWalk := state === s_walk
752  io.commits.isCommit := state === s_idle && !blockCommit
753
754  val walk_v = VecInit(walkingPtrVec.map(ptr => robEntries(ptr.value).valid))
755  val commit_vDeqGroup = VecInit(robDeqGroup.map(_.commit_v))
756  val commit_wDeqGroup = VecInit(robDeqGroup.map(_.commit_w))
757  val realCommitLast = deqPtrVec(0).lineHeadPtr + Fill(bankAddrWidth, 1.U)
758  val commit_block = VecInit((0 until CommitWidth).map(i => !commit_wDeqGroup(i) && !hasCommitted(i)))
759  val allowOnlyOneCommit = VecInit(robDeqGroup.map(x => x.commit_v && x.needFlush)).asUInt.orR || intrBitSetReg
760  // for instructions that may block others, we don't allow them to commit
761  io.commits.commitValid := PriorityMux(commitValidThisLine, (0 until CommitWidth).map(i => (commitValidThisLine.asUInt >> i).asUInt.asTypeOf(io.commits.commitValid)))
762
763  for (i <- 0 until CommitWidth) {
764    // defaults: state === s_idle and instructions commit
765    // when intrBitSetReg, allow only one instruction to commit at each clock cycle
766    val isBlocked = intrEnable || (deqNeedFlush && !deqHasFlushed && !deqHasFlushPipe)
767    val isBlockedByOlder = if (i != 0) commit_block.asUInt(i, 0).orR || allowOnlyOneCommit && !hasCommitted.asUInt(i - 1, 0).andR else false.B
768    commitValidThisLine(i) := commit_vDeqGroup(i) && commit_wDeqGroup(i) && !isBlocked && !isBlockedByOlder && !hasCommitted(i)
769    io.commits.info(i) := commitInfo(i)
770    io.commits.robIdx(i) := deqPtrVec(i)
771
772    io.commits.walkValid(i) := shouldWalkVec(i)
773    XSError(
774      state === s_walk &&
775      io.commits.isWalk && state === s_walk && shouldWalkVec(i) &&
776      !walk_v(i),
777      s"The walking entry($i) should be valid\n")
778
779    XSInfo(io.commits.isCommit && io.commits.commitValid(i),
780      "retired pc %x wen %d ldest %d pdest %x data %x fflags: %b vxsat: %b\n",
781      debug_microOp(deqPtrVec(i).value).pc,
782      io.commits.info(i).rfWen,
783      io.commits.info(i).debug_ldest.getOrElse(0.U),
784      io.commits.info(i).debug_pdest.getOrElse(0.U),
785      debug_exuData(deqPtrVec(i).value),
786      fflagsDataRead(i),
787      vxsatDataRead(i)
788    )
789    XSInfo(state === s_walk && io.commits.walkValid(i), "walked pc %x wen %d ldst %d data %x\n",
790      debug_microOp(walkPtrVec(i).value).pc,
791      io.commits.info(i).rfWen,
792      io.commits.info(i).debug_ldest.getOrElse(0.U),
793      debug_exuData(walkPtrVec(i).value)
794    )
795  }
796
797  // sync fflags/dirty_fs/vxsat to csr
798  io.csr.fflags   := RegNextWithEnable(fflags)
799  io.csr.dirty_fs := GatedValidRegNext(dirty_fs)
800  io.csr.dirty_vs := GatedValidRegNext(dirty_vs)
801  io.csr.vxsat    := RegNextWithEnable(vxsat)
802
803  // commit load/store to lsq
804  val ldCommitVec = VecInit((0 until CommitWidth).map(i => io.commits.commitValid(i) && io.commits.info(i).commitType === CommitType.LOAD))
805  // TODO: Check if meet the require that only set scommit when commit scala store uop
806  val stCommitVec = VecInit((0 until CommitWidth).map(i => io.commits.commitValid(i) && io.commits.info(i).commitType === CommitType.STORE && !robEntries(deqPtrVec(i).value).vls ))
807  io.lsq.lcommit := RegNext(Mux(io.commits.isCommit, PopCount(ldCommitVec), 0.U))
808  io.lsq.scommit := RegNext(Mux(io.commits.isCommit, PopCount(stCommitVec), 0.U))
809  // indicate a pending load or store
810  io.lsq.pendingMMIOld := RegNext(io.commits.isCommit && io.commits.info(0).commitType === CommitType.LOAD && deqPtrEntryValid && deqPtrEntry.mmio)
811  io.lsq.pendingld := RegNext(io.commits.isCommit && io.commits.info(0).commitType === CommitType.LOAD && deqPtrEntryValid)
812  // TODO: Check if need deassert pendingst when it is vst
813  io.lsq.pendingst := RegNext(io.commits.isCommit && io.commits.info(0).commitType === CommitType.STORE && deqPtrEntryValid)
814  // TODO: Check if set correctly when vector store is at the head of ROB
815  io.lsq.pendingVst := RegNext(io.commits.isCommit && io.commits.info(0).commitType === CommitType.STORE && deqPtrEntryValid && deqPtrEntry.vls)
816  io.lsq.commit := RegNext(io.commits.isCommit && io.commits.commitValid(0))
817  io.lsq.pendingPtr := RegNext(deqPtr)
818  io.lsq.pendingPtrNext := RegNext(deqPtrVec_next.head)
819
820  /**
821   * state changes
822   * (1) redirect: switch to s_walk
823   * (2) walk: when walking comes to the end, switch to s_idle
824   */
825  state_next := Mux(
826    io.redirect.valid || RegNext(io.redirect.valid), s_walk,
827    Mux(
828      state === s_walk && walkFinished && rab.io.status.walkEnd && vtypeBuffer.io.status.walkEnd, s_idle,
829      state
830    )
831  )
832  XSPerfAccumulate("s_idle_to_idle", state === s_idle && state_next === s_idle)
833  XSPerfAccumulate("s_idle_to_walk", state === s_idle && state_next === s_walk)
834  XSPerfAccumulate("s_walk_to_idle", state === s_walk && state_next === s_idle)
835  XSPerfAccumulate("s_walk_to_walk", state === s_walk && state_next === s_walk)
836  state := state_next
837
838  /**
839   * pointers and counters
840   */
841  val deqPtrGenModule = Module(new NewRobDeqPtrWrapper)
842  deqPtrGenModule.io.state := state
843  deqPtrGenModule.io.deq_v := commit_vDeqGroup
844  deqPtrGenModule.io.deq_w := commit_wDeqGroup
845  deqPtrGenModule.io.exception_state := exceptionDataRead
846  deqPtrGenModule.io.intrBitSetReg := intrBitSetReg
847  deqPtrGenModule.io.hasNoSpecExec := hasWaitForward
848  deqPtrGenModule.io.allowOnlyOneCommit := allowOnlyOneCommit
849  deqPtrGenModule.io.interrupt_safe := robDeqGroup(deqPtr.value(bankAddrWidth-1,0)).interrupt_safe
850  deqPtrGenModule.io.blockCommit := blockCommit
851  deqPtrGenModule.io.hasCommitted := hasCommitted
852  deqPtrGenModule.io.allCommitted := allCommitted
853  deqPtrVec := deqPtrGenModule.io.out
854  deqPtrVec_next := deqPtrGenModule.io.next_out
855
856  val enqPtrGenModule = Module(new RobEnqPtrWrapper)
857  enqPtrGenModule.io.redirect := io.redirect
858  enqPtrGenModule.io.allowEnqueue := allowEnqueue && rab.io.canEnq && !io.fromVecExcpMod.busy
859  enqPtrGenModule.io.hasBlockBackward := hasBlockBackward
860  enqPtrGenModule.io.enq := VecInit(io.enq.req.map(req => req.valid && req.bits.firstUop))
861  enqPtrVec := enqPtrGenModule.io.out
862
863  // next walkPtrVec:
864  // (1) redirect occurs: update according to state
865  // (2) walk: move forwards
866  val deqPtrReadBank = deqPtrVec_next(0).lineHeadPtr
867  val deqPtrVecForWalk = VecInit((0 until CommitWidth).map(i => deqPtrReadBank + i.U))
868  val snapPtrReadBank = snapshots(io.snpt.snptSelect)(0).lineHeadPtr
869  val snapPtrVecForWalk = VecInit((0 until CommitWidth).map(i => snapPtrReadBank + i.U))
870  val walkPtrVec_next: Vec[RobPtr] = Mux(io.redirect.valid,
871    Mux(io.snpt.useSnpt, snapPtrVecForWalk, deqPtrVecForWalk),
872    Mux((state === s_walk) && !walkFinished, VecInit(walkPtrVec.map(_ + CommitWidth.U)), walkPtrVec)
873  )
874  val walkPtrTrue_next: RobPtr = Mux(io.redirect.valid,
875    Mux(io.snpt.useSnpt, snapshots(io.snpt.snptSelect)(0), deqPtrVec_next(0)),
876    Mux((state === s_walk) && !walkFinished, walkPtrVec_next.head, walkPtrTrue)
877  )
878  walkPtrHead := walkPtrVec_next.head
879  walkPtrVec := walkPtrVec_next
880  walkPtrTrue := walkPtrTrue_next
881  // T io.redirect.valid, T+1 walkPtrLowBits update, T+2 donotNeedWalk update
882  val walkPtrLowBits = Reg(UInt(bankAddrWidth.W))
883  when(io.redirect.valid){
884    walkPtrLowBits := Mux(io.snpt.useSnpt, snapshots(io.snpt.snptSelect)(0).value(bankAddrWidth-1, 0), deqPtrVec_next(0).value(bankAddrWidth-1, 0))
885  }
886  when(io.redirect.valid) {
887    donotNeedWalk := Fill(donotNeedWalk.length, true.B).asTypeOf(donotNeedWalk)
888  }.elsewhen(RegNext(io.redirect.valid)){
889    donotNeedWalk := (0 until CommitWidth).map(i => (i.U < walkPtrLowBits))
890  }.otherwise{
891    donotNeedWalk := 0.U.asTypeOf(donotNeedWalk)
892  }
893  walkDestSizeDeqGroup.zip(walkPtrVec_next).map {
894    case (reg, ptrNext) => reg := deqPtrEntry.realDestSize
895  }
896  val numValidEntries = distanceBetween(enqPtr, deqPtr)
897  val commitCnt = PopCount(io.commits.commitValid)
898
899  allowEnqueue := numValidEntries + dispatchNum <= (RobSize - RenameWidth).U
900  allowEnqueueForDispatch := numValidEntries + dispatchNum <= (RobSize - 2 * RenameWidth).U
901
902  val redirectWalkDistance = distanceBetween(io.redirect.bits.robIdx, deqPtrVec_next(0))
903  when(io.redirect.valid) {
904    lastWalkPtr := Mux(io.redirect.bits.flushItself(), io.redirect.bits.robIdx - 1.U, io.redirect.bits.robIdx)
905  }
906
907
908  /**
909   * States
910   * We put all the stage bits changes here.
911   *
912   * All events: (1) enqueue (dispatch); (2) writeback; (3) cancel; (4) dequeue (commit);
913   * All states: (1) valid; (2) writebacked; (3) flagBkup
914   */
915
916  val deqPtrGroup = Wire(Vec(2 * CommitWidth, new RobPtr))
917  deqPtrGroup.zipWithIndex.map { case (deq, i) => deq := deqPtrVec(0) + i.U }
918  val commitReadAddr = Mux(state === s_idle, VecInit(deqPtrVec.map(_.value)), VecInit(walkPtrVec.map(_.value)))
919
920  val redirectValidReg = RegNext(io.redirect.valid)
921  val redirectBegin = Reg(UInt(log2Up(RobSize).W))
922  val redirectEnd = Reg(UInt(log2Up(RobSize).W))
923  val redirectAll = RegInit(false.B)
924  when(io.redirect.valid){
925    redirectBegin := Mux(io.redirect.bits.flushItself(), io.redirect.bits.robIdx.value - 1.U, io.redirect.bits.robIdx.value)
926    redirectEnd := enqPtr.value
927    redirectAll := io.redirect.bits.flushItself() && (io.redirect.bits.robIdx.value === enqPtr.value) && (io.redirect.bits.robIdx.flag ^ enqPtr.flag)
928  }
929
930  // update robEntries valid
931  for (i <- 0 until RobSize) {
932    val enqOH = VecInit(canEnqueue.zip(allocatePtrVec.map(_.value === i.U)).map(x => x._1 && x._2))
933    val commitCond = io.commits.isCommit && io.commits.commitValid.zip(deqPtrVec.map(_.value === i.U)).map(x => x._1 && x._2).reduce(_ || _)
934    assert(PopCount(enqOH) < 2.U, s"robEntries$i enqOH is not one hot")
935    val needFlush = redirectValidReg && Mux(
936      (redirectEnd > redirectBegin) && !redirectAll,
937      (i.U > redirectBegin) && (i.U < redirectEnd),
938      (i.U > redirectBegin) || (i.U < redirectEnd)
939    )
940    when(commitCond) {
941      robEntries(i).valid := false.B
942    }.elsewhen(enqOH.asUInt.orR && !io.redirect.valid) {
943      robEntries(i).valid := true.B
944    }.elsewhen(needFlush){
945      robEntries(i).valid := false.B
946    }
947  }
948
949  // debug_inst update
950  for (i <- 0 until (LduCnt + StaCnt)) {
951    debug_lsInfo(io.debug_ls.debugLsInfo(i).s1_robIdx).s1SignalEnable(io.debug_ls.debugLsInfo(i))
952    debug_lsInfo(io.debug_ls.debugLsInfo(i).s2_robIdx).s2SignalEnable(io.debug_ls.debugLsInfo(i))
953    debug_lsInfo(io.debug_ls.debugLsInfo(i).s3_robIdx).s3SignalEnable(io.debug_ls.debugLsInfo(i))
954  }
955  for (i <- 0 until LduCnt) {
956    debug_lsTopdownInfo(io.lsTopdownInfo(i).s1.robIdx).s1SignalEnable(io.lsTopdownInfo(i))
957    debug_lsTopdownInfo(io.lsTopdownInfo(i).s2.robIdx).s2SignalEnable(io.lsTopdownInfo(i))
958  }
959
960  // status field: writebacked
961  // enqueue logic set 6 writebacked to false
962
963  // writeback logic set numWbPorts writebacked to true
964
965  // if the first uop of an instruction is valid , write writebackedCounter
966  val uopEnqValidSeq = io.enq.req.map(req => io.enq.canAccept && req.valid)
967  val instEnqValidSeq = io.enq.req.map(req => io.enq.canAccept && req.valid && req.bits.firstUop)
968  val enqNeedWriteRFSeq = io.enq.req.map(_.bits.needWriteRf)
969  val enqHasExcpSeq = io.enq.req.map(_.bits.hasException)
970  val enqRobIdxSeq = io.enq.req.map(req => req.bits.robIdx.value)
971  val enqUopNumVec = VecInit(io.enq.req.map(req => req.bits.numUops))
972  val enqWBNumVec = VecInit(io.enq.req.map(req => req.bits.numWB))
973
974  private val enqWriteStdVec: Vec[Bool] = VecInit(io.enq.req.map {
975    req => FuType.isStore(req.bits.fuType)
976  })
977  val fflags_wb = fflagsWBs
978  val vxsat_wb = vxsatWBs
979  for (i <- 0 until RobSize) {
980
981    val robIdxMatchSeq = io.enq.req.map(_.bits.robIdx.value === i.U)
982    val uopCanEnqSeq = uopEnqValidSeq.zip(robIdxMatchSeq).map { case (valid, isMatch) => valid && isMatch }
983    val instCanEnqSeq = instEnqValidSeq.zip(robIdxMatchSeq).map { case (valid, isMatch) => valid && isMatch }
984    val instCanEnqFlag = Cat(instCanEnqSeq).orR
985    val hasExcpSeq = enqHasExcpSeq.lazyZip(robIdxMatchSeq).lazyZip(uopEnqValidSeq).map { case (excp, isMatch, valid) => excp && isMatch && valid }
986    val hasExcpFlag = Cat(hasExcpSeq).orR
987    val isFirstEnq = !robEntries(i).valid && instCanEnqFlag
988    val realDestEnqNum = PopCount(enqNeedWriteRFSeq.zip(uopCanEnqSeq).map { case (writeFlag, valid) => writeFlag && valid })
989    when(isFirstEnq){
990      robEntries(i).realDestSize := realDestEnqNum //Mux(hasExcpFlag, 0.U, realDestEnqNum)
991    }.elsewhen(robEntries(i).valid && Cat(uopCanEnqSeq).orR){
992      robEntries(i).realDestSize := robEntries(i).realDestSize + realDestEnqNum
993    }
994    val enqUopNum = PriorityMux(instCanEnqSeq, enqUopNumVec)
995    val enqWBNum = PriorityMux(instCanEnqSeq, enqWBNumVec)
996    val enqWriteStd = PriorityMux(instCanEnqSeq, enqWriteStdVec)
997
998    val canWbSeq = exuWBs.map(writeback => writeback.valid && writeback.bits.robIdx.value === i.U)
999    val canStdWbSeq = VecInit(stdWBs.map(writeback => writeback.valid && writeback.bits.robIdx.value === i.U))
1000    val wbCnt = Mux1H(canWbSeq, io.writebackNums.map(_.bits))
1001
1002    val canWbExceptionSeq = exceptionWBs.map(writeback => writeback.valid && writeback.bits.robIdx.value === i.U)
1003    val needFlush = robEntries(i).needFlush
1004    val needFlushWriteBack = Wire(Bool())
1005    needFlushWriteBack := Mux1H(canWbExceptionSeq, io.writebackNeedFlush)
1006    when(robEntries(i).valid){
1007      needFlush := needFlush || needFlushWriteBack
1008    }
1009
1010    when(robEntries(i).valid && (needFlush || needFlushWriteBack)) {
1011      // exception flush
1012      robEntries(i).uopNum := robEntries(i).uopNum - wbCnt
1013      robEntries(i).stdWritebacked := true.B
1014    }.elsewhen(!robEntries(i).valid && instCanEnqFlag) {
1015      // enq set num of uops
1016      robEntries(i).uopNum := enqWBNum
1017      robEntries(i).stdWritebacked := Mux(enqWriteStd, false.B, true.B)
1018    }.elsewhen(robEntries(i).valid) {
1019      // update by writing back
1020      robEntries(i).uopNum := robEntries(i).uopNum - wbCnt
1021      assert(!(robEntries(i).uopNum - wbCnt > robEntries(i).uopNum), s"robEntries $i uopNum is overflow!")
1022      when(canStdWbSeq.asUInt.orR) {
1023        robEntries(i).stdWritebacked := true.B
1024      }
1025    }
1026
1027    val fflagsCanWbSeq = fflags_wb.map(writeback => writeback.valid && writeback.bits.robIdx.value === i.U && writeback.bits.wflags.getOrElse(false.B))
1028    val fflagsRes = fflagsCanWbSeq.zip(fflags_wb).map { case (canWb, wb) => Mux(canWb, wb.bits.fflags.get, 0.U) }.fold(false.B)(_ | _)
1029    when(isFirstEnq) {
1030      robEntries(i).fflags := 0.U
1031    }.elsewhen(fflagsRes.orR) {
1032      robEntries(i).fflags := robEntries(i).fflags | fflagsRes
1033    }
1034
1035    val vxsatCanWbSeq = vxsat_wb.map(writeback => writeback.valid && writeback.bits.robIdx.value === i.U)
1036    val vxsatRes = vxsatCanWbSeq.zip(vxsat_wb).map { case (canWb, wb) => Mux(canWb, wb.bits.vxsat.get, 0.U) }.fold(false.B)(_ | _)
1037    when(isFirstEnq) {
1038      robEntries(i).vxsat := 0.U
1039    }.elsewhen(vxsatRes.orR) {
1040      robEntries(i).vxsat := robEntries(i).vxsat | vxsatRes
1041    }
1042
1043    // trace
1044    val taken = branchWBs.map(writeback => writeback.valid && writeback.bits.robIdx.value === i.U && writeback.bits.redirect.get.bits.cfiUpdate.taken).reduce(_ || _)
1045    when(robEntries(i).valid && Itype.isBranchType(robEntries(i).traceBlockInPipe.itype) && taken){
1046      // BranchType code(notaken itype = 4) must be correctly replaced!
1047      robEntries(i).traceBlockInPipe.itype := Itype.Taken
1048    }
1049  }
1050
1051  // begin update robBanksRdata
1052  val robBanksRdata = VecInit(robBanksRdataThisLine ++ robBanksRdataNextLine)
1053  val needUpdate = Wire(Vec(2 * CommitWidth, new RobEntryBundle))
1054  needUpdate := VecInit(robBanksRdataThisLine ++ robBanksRdataNextLine)
1055  val needUpdateRobIdx = robIdxThisLine ++ robIdxNextLine
1056  for (i <- 0 until 2 * CommitWidth) {
1057    val robIdxMatchSeq = io.enq.req.map(_.bits.robIdx.value === needUpdateRobIdx(i))
1058    val uopCanEnqSeq = uopEnqValidSeq.zip(robIdxMatchSeq).map { case (valid, isMatch) => valid && isMatch }
1059    val instCanEnqSeq = instEnqValidSeq.zip(robIdxMatchSeq).map { case (valid, isMatch) => valid && isMatch }
1060    val instCanEnqFlag = Cat(instCanEnqSeq).orR
1061    val realDestEnqNum = PopCount(enqNeedWriteRFSeq.zip(uopCanEnqSeq).map { case (writeFlag, valid) => writeFlag && valid })
1062    when(!needUpdate(i).valid && instCanEnqFlag) {
1063      needUpdate(i).realDestSize := realDestEnqNum
1064    }.elsewhen(needUpdate(i).valid && instCanEnqFlag) {
1065      needUpdate(i).realDestSize := robBanksRdata(i).realDestSize + realDestEnqNum
1066    }
1067    val enqUopNum = PriorityMux(instCanEnqSeq, enqUopNumVec)
1068    val enqWBNum = PriorityMux(instCanEnqSeq, enqWBNumVec)
1069    val enqWriteStd = PriorityMux(instCanEnqSeq, enqWriteStdVec)
1070
1071    val canWbSeq = exuWBs.map(writeback => writeback.valid && writeback.bits.robIdx.value === needUpdateRobIdx(i))
1072    val canStdWbSeq = VecInit(stdWBs.map(writeback => writeback.valid && writeback.bits.robIdx.value === needUpdateRobIdx(i)))
1073    val wbCnt = Mux1H(canWbSeq, io.writebackNums.map(_.bits))
1074
1075    val canWbExceptionSeq = exceptionWBs.map(writeback => writeback.valid && (writeback.bits.robIdx.value === needUpdateRobIdx(i)))
1076    val needFlush = robBanksRdata(i).needFlush
1077    val needFlushWriteBack = Wire(Bool())
1078    needFlushWriteBack := Mux1H(canWbExceptionSeq, io.writebackNeedFlush)
1079    when(needUpdate(i).valid) {
1080      needUpdate(i).needFlush := needFlush || needFlushWriteBack
1081    }
1082
1083    when(needUpdate(i).valid && (needFlush || needFlushWriteBack)) {
1084      // exception flush
1085      needUpdate(i).uopNum := robBanksRdata(i).uopNum - wbCnt
1086      needUpdate(i).stdWritebacked := true.B
1087    }.elsewhen(!needUpdate(i).valid && instCanEnqFlag) {
1088      // enq set num of uops
1089      needUpdate(i).uopNum := enqWBNum
1090      needUpdate(i).stdWritebacked := Mux(enqWriteStd, false.B, true.B)
1091    }.elsewhen(needUpdate(i).valid) {
1092      // update by writing back
1093      needUpdate(i).uopNum := robBanksRdata(i).uopNum - wbCnt
1094      when(canStdWbSeq.asUInt.orR) {
1095        needUpdate(i).stdWritebacked := true.B
1096      }
1097    }
1098
1099    val fflagsCanWbSeq = fflags_wb.map(writeback => writeback.valid && writeback.bits.robIdx.value === needUpdateRobIdx(i) && writeback.bits.wflags.getOrElse(false.B))
1100    val fflagsRes = fflagsCanWbSeq.zip(fflags_wb).map { case (canWb, wb) => Mux(canWb, wb.bits.fflags.get, 0.U) }.fold(false.B)(_ | _)
1101    needUpdate(i).fflags := Mux(!robBanksRdata(i).valid && instCanEnqFlag, 0.U, robBanksRdata(i).fflags | fflagsRes)
1102
1103    val vxsatCanWbSeq = vxsat_wb.map(writeback => writeback.valid && writeback.bits.robIdx.value === needUpdateRobIdx(i))
1104    val vxsatRes = vxsatCanWbSeq.zip(vxsat_wb).map { case (canWb, wb) => Mux(canWb, wb.bits.vxsat.get, 0.U) }.fold(false.B)(_ | _)
1105    needUpdate(i).vxsat := Mux(!robBanksRdata(i).valid && instCanEnqFlag, 0.U, robBanksRdata(i).vxsat | vxsatRes)
1106
1107    // trace
1108    val taken = branchWBs.map(writeback => writeback.valid && writeback.bits.robIdx.value === needUpdateRobIdx(i) && writeback.bits.redirect.get.bits.cfiUpdate.taken).reduce(_ || _)
1109    when(robBanksRdata(i).valid && Itype.isBranchType(robBanksRdata(i).traceBlockInPipe.itype) && taken){
1110      // BranchType code(notaken itype = 4) must be correctly replaced!
1111      needUpdate(i).traceBlockInPipe.itype := Itype.Taken
1112    }
1113  }
1114  robBanksRdataThisLineUpdate := VecInit(needUpdate.take(8))
1115  robBanksRdataNextLineUpdate := VecInit(needUpdate.drop(8))
1116  // end update robBanksRdata
1117
1118  // interrupt_safe
1119  for (i <- 0 until RenameWidth) {
1120    when(canEnqueue(i)) {
1121      // For now, we allow non-load-store instructions to trigger interrupts
1122      // For MMIO instructions, they should not trigger interrupts since they may
1123      // be sent to lower level before it writes back.
1124      // However, we cannot determine whether a load/store instruction is MMIO.
1125      // Thus, we don't allow load/store instructions to trigger an interrupt.
1126      // TODO: support non-MMIO load-store instructions to trigger interrupts
1127      val allow_interrupts = !CommitType.isLoadStore(io.enq.req(i).bits.commitType) && !FuType.isFence(io.enq.req(i).bits.fuType) && !FuType.isCsr(io.enq.req(i).bits.fuType) && !FuType.isVset(io.enq.req(i).bits.fuType)
1128      robEntries(allocatePtrVec(i).value).interrupt_safe := allow_interrupts
1129    }
1130  }
1131
1132  /**
1133   * read and write of data modules
1134   */
1135  val commitReadAddr_next = Mux(state_next === s_idle,
1136    VecInit(deqPtrVec_next.map(_.value)),
1137    VecInit(walkPtrVec_next.map(_.value))
1138  )
1139
1140  exceptionGen.io.redirect <> io.redirect
1141  exceptionGen.io.flush := io.flushOut.valid
1142
1143  val canEnqueueEG = VecInit(io.enq.req.map(req => req.valid && io.enq.canAccept))
1144  for (i <- 0 until RenameWidth) {
1145    exceptionGen.io.enq(i).valid := canEnqueueEG(i)
1146    exceptionGen.io.enq(i).bits.robIdx := io.enq.req(i).bits.robIdx
1147    exceptionGen.io.enq(i).bits.ftqPtr := io.enq.req(i).bits.ftqPtr
1148    exceptionGen.io.enq(i).bits.ftqOffset := io.enq.req(i).bits.ftqOffset
1149    exceptionGen.io.enq(i).bits.exceptionVec := ExceptionNO.selectFrontend(io.enq.req(i).bits.exceptionVec)
1150    exceptionGen.io.enq(i).bits.hasException := io.enq.req(i).bits.hasException
1151    exceptionGen.io.enq(i).bits.isEnqExcp := io.enq.req(i).bits.hasException
1152    exceptionGen.io.enq(i).bits.isFetchMalAddr := io.enq.req(i).bits.isFetchMalAddr
1153    exceptionGen.io.enq(i).bits.flushPipe := io.enq.req(i).bits.flushPipe
1154    exceptionGen.io.enq(i).bits.isVset := io.enq.req(i).bits.isVset
1155    exceptionGen.io.enq(i).bits.replayInst := false.B
1156    XSError(canEnqueue(i) && io.enq.req(i).bits.replayInst, "enq should not set replayInst")
1157    exceptionGen.io.enq(i).bits.singleStep := io.enq.req(i).bits.singleStep
1158    exceptionGen.io.enq(i).bits.crossPageIPFFix := io.enq.req(i).bits.crossPageIPFFix
1159    exceptionGen.io.enq(i).bits.trigger := io.enq.req(i).bits.trigger
1160    exceptionGen.io.enq(i).bits.vstartEn := false.B //DontCare
1161    exceptionGen.io.enq(i).bits.vstart := 0.U //DontCare
1162    exceptionGen.io.enq(i).bits.vuopIdx := 0.U
1163    exceptionGen.io.enq(i).bits.isVecLoad := false.B
1164    exceptionGen.io.enq(i).bits.isVlm := false.B
1165    exceptionGen.io.enq(i).bits.isStrided := false.B
1166    exceptionGen.io.enq(i).bits.isIndexed := false.B
1167    exceptionGen.io.enq(i).bits.isWhole := false.B
1168    exceptionGen.io.enq(i).bits.nf := 0.U
1169    exceptionGen.io.enq(i).bits.vsew := 0.U
1170    exceptionGen.io.enq(i).bits.veew := 0.U
1171    exceptionGen.io.enq(i).bits.vlmul := 0.U
1172  }
1173
1174  println(s"ExceptionGen:")
1175  println(s"num of exceptions: ${params.numException}")
1176  require(exceptionWBs.length == exceptionGen.io.wb.length,
1177    f"exceptionWBs.length: ${exceptionWBs.length}, " +
1178      f"exceptionGen.io.wb.length: ${exceptionGen.io.wb.length}")
1179  for (((wb, exc_wb), i) <- exceptionWBs.zip(exceptionGen.io.wb).zipWithIndex) {
1180    exc_wb.valid       := wb.valid
1181    exc_wb.bits.robIdx := wb.bits.robIdx
1182    // only enq inst use ftqPtr to read gpa
1183    exc_wb.bits.ftqPtr          := 0.U.asTypeOf(exc_wb.bits.ftqPtr)
1184    exc_wb.bits.ftqOffset       := 0.U.asTypeOf(exc_wb.bits.ftqOffset)
1185    exc_wb.bits.exceptionVec    := wb.bits.exceptionVec.get
1186    exc_wb.bits.hasException    := wb.bits.exceptionVec.get.asUInt.orR // Todo: use io.writebackNeedFlush(i) instead
1187    exc_wb.bits.isEnqExcp       := false.B
1188    exc_wb.bits.isFetchMalAddr  := false.B
1189    exc_wb.bits.flushPipe       := wb.bits.flushPipe.getOrElse(false.B)
1190    exc_wb.bits.isVset          := false.B
1191    exc_wb.bits.replayInst      := wb.bits.replay.getOrElse(false.B)
1192    exc_wb.bits.singleStep      := false.B
1193    exc_wb.bits.crossPageIPFFix := false.B
1194    val trigger = wb.bits.trigger.getOrElse(TriggerAction.None).asTypeOf(exc_wb.bits.trigger)
1195    exc_wb.bits.trigger := trigger
1196    exc_wb.bits.vstartEn := (if (wb.bits.vls.nonEmpty) wb.bits.exceptionVec.get.asUInt.orR || TriggerAction.isDmode(trigger) else 0.U)
1197    exc_wb.bits.vstart := (if (wb.bits.vls.nonEmpty) wb.bits.vls.get.vpu.vstart else 0.U)
1198    exc_wb.bits.vuopIdx := (if (wb.bits.vls.nonEmpty) wb.bits.vls.get.vpu.vuopIdx else 0.U)
1199    exc_wb.bits.isVecLoad := wb.bits.vls.map(_.isVecLoad).getOrElse(false.B)
1200    exc_wb.bits.isVlm := wb.bits.vls.map(_.isVlm).getOrElse(false.B)
1201    exc_wb.bits.isStrided := wb.bits.vls.map(_.isStrided).getOrElse(false.B) // strided need two mode tmp vreg
1202    exc_wb.bits.isIndexed := wb.bits.vls.map(_.isIndexed).getOrElse(false.B) // indexed and nf=0 need non-sequential uopidx -> vdidx
1203    exc_wb.bits.isWhole := wb.bits.vls.map(_.isWhole).getOrElse(false.B) // indexed and nf=0 need non-sequential uopidx -> vdidx
1204    exc_wb.bits.nf := wb.bits.vls.map(_.vpu.nf).getOrElse(0.U)
1205    exc_wb.bits.vsew := wb.bits.vls.map(_.vpu.vsew).getOrElse(0.U)
1206    exc_wb.bits.veew := wb.bits.vls.map(_.vpu.veew).getOrElse(0.U)
1207    exc_wb.bits.vlmul := wb.bits.vls.map(_.vpu.vlmul).getOrElse(0.U)
1208  }
1209
1210  fflagsDataRead := (0 until CommitWidth).map(i => robEntries(deqPtrVec(i).value).fflags)
1211  vxsatDataRead := (0 until CommitWidth).map(i => robEntries(deqPtrVec(i).value).vxsat)
1212
1213  val isCommit = io.commits.isCommit
1214  val isCommitReg = GatedValidRegNext(io.commits.isCommit)
1215  val instrCntReg = RegInit(0.U(64.W))
1216  val fuseCommitCnt = PopCount(io.commits.commitValid.zip(io.commits.info).map { case (v, i) => RegEnable(v && CommitType.isFused(i.commitType), isCommit) })
1217  val trueCommitCnt = RegEnable(io.commits.commitValid.zip(io.commits.info).map { case (v, i) => Mux(v, i.instrSize, 0.U) }.reduce(_ +& _), isCommit) +& fuseCommitCnt
1218  val retireCounter = Mux(isCommitReg, trueCommitCnt, 0.U)
1219  val instrCnt = instrCntReg + retireCounter
1220  when(isCommitReg){
1221    instrCntReg := instrCnt
1222  }
1223  io.csr.perfinfo.retiredInstr := retireCounter
1224  io.robFull := !allowEnqueue
1225  io.headNotReady := commit_vDeqGroup(deqPtr.value(bankNumWidth-1, 0)) && !commit_wDeqGroup(deqPtr.value(bankNumWidth-1, 0))
1226
1227  io.toVecExcpMod.logicPhyRegMap := rab.io.toVecExcpMod.logicPhyRegMap
1228  io.toVecExcpMod.excpInfo := vecExcpInfo
1229
1230  /**
1231   * trace
1232   */
1233
1234  // trace output
1235  val traceValids = io.trace.traceCommitInfo.blocks.map(_.valid)
1236  val traceBlocks = io.trace.traceCommitInfo.blocks
1237  val traceBlockInPipe = io.trace.traceCommitInfo.blocks.map(_.bits.tracePipe)
1238
1239  // The reg 'isTraceXret' only for trace xret instructions. xret only occur in block(0).
1240  val isTraceXret = RegInit(false.B)
1241  when(io.csr.isXRet){
1242    isTraceXret := true.B
1243  }.elsewhen(isTraceXret && io.commits.isCommit && io.commits.commitValid(0)){
1244    isTraceXret := false.B
1245  }
1246
1247  for (i <- 0 until CommitWidth) {
1248    traceBlocks(i).bits.ftqIdx.foreach(_ := rawInfo(i).ftqIdx)
1249    traceBlocks(i).bits.ftqOffset.foreach(_ := rawInfo(i).ftqOffset)
1250    traceBlockInPipe(i).itype := rawInfo(i).traceBlockInPipe.itype
1251    traceBlockInPipe(i).iretire := rawInfo(i).traceBlockInPipe.iretire
1252    traceBlockInPipe(i).ilastsize := rawInfo(i).traceBlockInPipe.ilastsize
1253    traceValids(i) := io.commits.isCommit && io.commits.commitValid(i)
1254    // exception/xret only occur in block(0).
1255    if(i == 0) {
1256      when(isTraceXret && io.commits.isCommit && io.commits.commitValid(0)){ // trace xret
1257        traceBlocks(i).bits.tracePipe.itype := Itype.ExpIntReturn
1258      }.elsewhen(io.exception.valid){ // trace exception
1259        traceBlocks(i).bits.tracePipe.itype := Mux(io.exception.bits.isInterrupt,
1260          Itype.Interrupt,
1261          Itype.Exception
1262        )
1263        traceValids(i) := true.B
1264        traceBlockInPipe(i).iretire := 0.U
1265      }
1266    }
1267  }
1268
1269  /**
1270   * debug info
1271   */
1272  XSDebug(p"enqPtr ${enqPtr} deqPtr ${deqPtr}\n")
1273  XSDebug("")
1274  XSError(isBefore(enqPtr, deqPtr) && !isFull(enqPtr, deqPtr), "\ndeqPtr is older than enqPtr!\n")
1275  for (i <- 0 until RobSize) {
1276    XSDebug(false, !robEntries(i).valid, "-")
1277    XSDebug(false, robEntries(i).valid && robEntries(i).isWritebacked, "w")
1278    XSDebug(false, robEntries(i).valid && !robEntries(i).isWritebacked, "v")
1279  }
1280  XSDebug(false, true.B, "\n")
1281
1282  for (i <- 0 until RobSize) {
1283    if (i % 4 == 0) XSDebug("")
1284    XSDebug(false, true.B, "%x ", debug_microOp(i).pc)
1285    XSDebug(false, !robEntries(i).valid, "- ")
1286    XSDebug(false, robEntries(i).valid && robEntries(i).isWritebacked, "w ")
1287    XSDebug(false, robEntries(i).valid && !robEntries(i).isWritebacked, "v ")
1288    if (i % 4 == 3) XSDebug(false, true.B, "\n")
1289  }
1290
1291  def ifCommit(counter: UInt): UInt = Mux(isCommit, counter, 0.U)
1292
1293  def ifCommitReg(counter: UInt): UInt = Mux(isCommitReg, counter, 0.U)
1294
1295  val commitDebugUop = deqPtrVec.map(_.value).map(debug_microOp(_))
1296  XSPerfAccumulate("clock_cycle", 1.U)
1297  QueuePerf(RobSize, numValidEntries, numValidEntries === RobSize.U)
1298  XSPerfAccumulate("commitUop", ifCommit(commitCnt))
1299  XSPerfAccumulate("commitInstr", ifCommitReg(trueCommitCnt))
1300  XSPerfRolling("ipc", ifCommitReg(trueCommitCnt), 1000, clock, reset)
1301  XSPerfRolling("cpi", perfCnt = 1.U /*Cycle*/ , eventTrigger = ifCommitReg(trueCommitCnt), granularity = 1000, clock, reset)
1302  XSPerfAccumulate("commitInstrFused", ifCommitReg(fuseCommitCnt))
1303  val commitIsLoad = io.commits.info.map(_.commitType).map(_ === CommitType.LOAD)
1304  val commitLoadValid = io.commits.commitValid.zip(commitIsLoad).map { case (v, t) => v && t }
1305  XSPerfAccumulate("commitInstrLoad", ifCommit(PopCount(commitLoadValid)))
1306  val commitIsBranch = io.commits.info.map(_.commitType).map(_ === CommitType.BRANCH)
1307  val commitBranchValid = io.commits.commitValid.zip(commitIsBranch).map { case (v, t) => v && t }
1308  XSPerfAccumulate("commitInstrBranch", ifCommit(PopCount(commitBranchValid)))
1309  val commitIsStore = io.commits.info.map(_.commitType).map(_ === CommitType.STORE)
1310  XSPerfAccumulate("commitInstrStore", ifCommit(PopCount(io.commits.commitValid.zip(commitIsStore).map { case (v, t) => v && t })))
1311  XSPerfAccumulate("writeback", PopCount((0 until RobSize).map(i => robEntries(i).valid && robEntries(i).isWritebacked)))
1312  // XSPerfAccumulate("enqInstr", PopCount(io.dp1Req.map(_.fire)))
1313  // XSPerfAccumulate("d2rVnR", PopCount(io.dp1Req.map(p => p.valid && !p.ready)))
1314  XSPerfAccumulate("walkInstr", Mux(io.commits.isWalk, PopCount(io.commits.walkValid), 0.U))
1315  XSPerfAccumulate("walkCycleTotal", state === s_walk)
1316  XSPerfAccumulate("waitRabWalkEnd", state === s_walk && walkFinished && !rab.io.status.walkEnd)
1317  private val walkCycle = RegInit(0.U(8.W))
1318  private val waitRabWalkCycle = RegInit(0.U(8.W))
1319  walkCycle := Mux(io.redirect.valid, 0.U, Mux(state === s_walk, walkCycle + 1.U, 0.U))
1320  waitRabWalkCycle := Mux(state === s_walk && walkFinished, 0.U, Mux(state === s_walk, walkCycle + 1.U, 0.U))
1321
1322  XSPerfHistogram("walkRobCycleHist", walkCycle, state === s_walk && walkFinished, 0, 32)
1323  XSPerfHistogram("walkRabExtraCycleHist", waitRabWalkCycle, state === s_walk && walkFinished && rab.io.status.walkEnd, 0, 32)
1324  XSPerfHistogram("walkTotalCycleHist", walkCycle, state === s_walk && state_next === s_idle, 0, 32)
1325
1326  private val deqNotWritebacked = robEntries(deqPtr.value).valid && !robEntries(deqPtr.value).isWritebacked
1327  private val deqStdNotWritebacked = robEntries(deqPtr.value).valid && !robEntries(deqPtr.value).stdWritebacked
1328  private val deqUopNotWritebacked = robEntries(deqPtr.value).valid && !robEntries(deqPtr.value).isUopWritebacked
1329  private val deqHeadInfo = debug_microOp(deqPtr.value)
1330  val deqUopCommitType = debug_microOp(deqPtr.value).commitType
1331
1332  XSPerfAccumulate("waitAluCycle", deqNotWritebacked && deqHeadInfo.fuType === FuType.alu.U)
1333  XSPerfAccumulate("waitMulCycle", deqNotWritebacked && deqHeadInfo.fuType === FuType.mul.U)
1334  XSPerfAccumulate("waitDivCycle", deqNotWritebacked && deqHeadInfo.fuType === FuType.div.U)
1335  XSPerfAccumulate("waitBrhCycle", deqNotWritebacked && deqHeadInfo.fuType === FuType.brh.U)
1336  XSPerfAccumulate("waitJmpCycle", deqNotWritebacked && deqHeadInfo.fuType === FuType.jmp.U)
1337  XSPerfAccumulate("waitCsrCycle", deqNotWritebacked && deqHeadInfo.fuType === FuType.csr.U)
1338  XSPerfAccumulate("waitFenCycle", deqNotWritebacked && deqHeadInfo.fuType === FuType.fence.U)
1339  XSPerfAccumulate("waitBkuCycle", deqNotWritebacked && deqHeadInfo.fuType === FuType.bku.U)
1340  XSPerfAccumulate("waitLduCycle", deqNotWritebacked && deqHeadInfo.fuType === FuType.ldu.U)
1341  XSPerfAccumulate("waitStuCycle", deqNotWritebacked && deqHeadInfo.fuType === FuType.stu.U)
1342  XSPerfAccumulate("waitStaCycle", deqUopNotWritebacked && deqHeadInfo.fuType === FuType.stu.U)
1343  XSPerfAccumulate("waitStdCycle", deqStdNotWritebacked && deqHeadInfo.fuType === FuType.stu.U)
1344  XSPerfAccumulate("waitAtmCycle", deqStdNotWritebacked && deqHeadInfo.fuType === FuType.mou.U)
1345
1346  XSPerfAccumulate("waitVfaluCycle", deqStdNotWritebacked && deqHeadInfo.fuType === FuType.vfalu.U)
1347  XSPerfAccumulate("waitVfmaCycle", deqStdNotWritebacked && deqHeadInfo.fuType === FuType.vfma.U)
1348  XSPerfAccumulate("waitVfdivCycle", deqStdNotWritebacked && deqHeadInfo.fuType === FuType.vfdiv.U)
1349
1350  val vfalufuop = Seq(VfaluType.vfadd, VfaluType.vfwadd, VfaluType.vfwadd_w, VfaluType.vfsub, VfaluType.vfwsub, VfaluType.vfwsub_w, VfaluType.vfmin, VfaluType.vfmax,
1351    VfaluType.vfmerge, VfaluType.vfmv, VfaluType.vfsgnj, VfaluType.vfsgnjn, VfaluType.vfsgnjx, VfaluType.vfeq, VfaluType.vfne, VfaluType.vflt, VfaluType.vfle, VfaluType.vfgt,
1352    VfaluType.vfge, VfaluType.vfclass, VfaluType.vfmv_f_s, VfaluType.vfmv_s_f, VfaluType.vfredusum, VfaluType.vfredmax, VfaluType.vfredmin, VfaluType.vfredosum, VfaluType.vfwredosum)
1353
1354  vfalufuop.zipWithIndex.map{
1355    case(fuoptype,i) =>  XSPerfAccumulate(s"waitVfalu_${i}Cycle", deqStdNotWritebacked && deqHeadInfo.fuOpType === fuoptype && deqHeadInfo.fuType === FuType.vfalu.U)
1356  }
1357
1358
1359
1360  XSPerfAccumulate("waitNormalCycle", deqNotWritebacked && deqUopCommitType === CommitType.NORMAL)
1361  XSPerfAccumulate("waitBranchCycle", deqNotWritebacked && deqUopCommitType === CommitType.BRANCH)
1362  XSPerfAccumulate("waitLoadCycle", deqNotWritebacked && deqUopCommitType === CommitType.LOAD)
1363  XSPerfAccumulate("waitStoreCycle", deqNotWritebacked && deqUopCommitType === CommitType.STORE)
1364  XSPerfAccumulate("robHeadPC", io.commits.info(0).debug_pc.getOrElse(0.U))
1365  XSPerfAccumulate("commitCompressCntAll", PopCount(io.commits.commitValid.zip(io.commits.info).map { case (valid, info) => io.commits.isCommit && valid && info.instrSize > 1.U }))
1366  (2 to RenameWidth).foreach(i =>
1367    XSPerfAccumulate(s"commitCompressCnt${i}", PopCount(io.commits.commitValid.zip(io.commits.info).map { case (valid, info) => io.commits.isCommit && valid && info.instrSize === i.U }))
1368  )
1369  XSPerfAccumulate("compressSize", io.commits.commitValid.zip(io.commits.info).map { case (valid, info) => Mux(io.commits.isCommit && valid && info.instrSize > 1.U, info.instrSize, 0.U) }.reduce(_ +& _))
1370  val dispatchLatency = commitDebugUop.map(uop => uop.debugInfo.dispatchTime - uop.debugInfo.renameTime)
1371  val enqRsLatency = commitDebugUop.map(uop => uop.debugInfo.enqRsTime - uop.debugInfo.dispatchTime)
1372  val selectLatency = commitDebugUop.map(uop => uop.debugInfo.selectTime - uop.debugInfo.enqRsTime)
1373  val issueLatency = commitDebugUop.map(uop => uop.debugInfo.issueTime - uop.debugInfo.selectTime)
1374  val executeLatency = commitDebugUop.map(uop => uop.debugInfo.writebackTime - uop.debugInfo.issueTime)
1375  val rsFuLatency = commitDebugUop.map(uop => uop.debugInfo.writebackTime - uop.debugInfo.enqRsTime)
1376  val commitLatency = commitDebugUop.map(uop => timer - uop.debugInfo.writebackTime)
1377
1378  def latencySum(cond: Seq[Bool], latency: Seq[UInt]): UInt = {
1379    cond.zip(latency).map(x => Mux(x._1, x._2, 0.U)).reduce(_ +& _)
1380  }
1381
1382  for (fuType <- FuType.functionNameMap.keys) {
1383    val fuName = FuType.functionNameMap(fuType)
1384    val commitIsFuType = io.commits.commitValid.zip(commitDebugUop).map(x => x._1 && x._2.fuType === fuType.U)
1385    XSPerfRolling(s"ipc_futype_${fuName}", ifCommit(PopCount(commitIsFuType)), 1000, clock, reset)
1386    XSPerfAccumulate(s"${fuName}_instr_cnt", ifCommit(PopCount(commitIsFuType)))
1387    XSPerfAccumulate(s"${fuName}_latency_dispatch", ifCommit(latencySum(commitIsFuType, dispatchLatency)))
1388    XSPerfAccumulate(s"${fuName}_latency_enq_rs", ifCommit(latencySum(commitIsFuType, enqRsLatency)))
1389    XSPerfAccumulate(s"${fuName}_latency_select", ifCommit(latencySum(commitIsFuType, selectLatency)))
1390    XSPerfAccumulate(s"${fuName}_latency_issue", ifCommit(latencySum(commitIsFuType, issueLatency)))
1391    XSPerfAccumulate(s"${fuName}_latency_execute", ifCommit(latencySum(commitIsFuType, executeLatency)))
1392    XSPerfAccumulate(s"${fuName}_latency_enq_rs_execute", ifCommit(latencySum(commitIsFuType, rsFuLatency)))
1393    XSPerfAccumulate(s"${fuName}_latency_commit", ifCommit(latencySum(commitIsFuType, commitLatency)))
1394  }
1395  XSPerfAccumulate(s"redirect_use_snapshot", io.redirect.valid && io.snpt.useSnpt)
1396
1397  // top-down info
1398  io.debugTopDown.toCore.robHeadVaddr.valid := debug_lsTopdownInfo(deqPtr.value).s1.vaddr_valid
1399  io.debugTopDown.toCore.robHeadVaddr.bits := debug_lsTopdownInfo(deqPtr.value).s1.vaddr_bits
1400  io.debugTopDown.toCore.robHeadPaddr.valid := debug_lsTopdownInfo(deqPtr.value).s2.paddr_valid
1401  io.debugTopDown.toCore.robHeadPaddr.bits := debug_lsTopdownInfo(deqPtr.value).s2.paddr_bits
1402  io.debugTopDown.toDispatch.robTrueCommit := ifCommitReg(trueCommitCnt)
1403  io.debugTopDown.toDispatch.robHeadLsIssue := debug_lsIssue(deqPtr.value)
1404  io.debugTopDown.robHeadLqIdx.valid := debug_lqIdxValid(deqPtr.value)
1405  io.debugTopDown.robHeadLqIdx.bits := debug_microOp(deqPtr.value).lqIdx
1406
1407  // rolling
1408  io.debugRolling.robTrueCommit := ifCommitReg(trueCommitCnt)
1409
1410  /**
1411   * DataBase info:
1412   * log trigger is at writeback valid
1413   * */
1414  if (!env.FPGAPlatform) {
1415    val instTableName = "InstTable" + p(XSCoreParamsKey).HartId.toString
1416    val instSiteName = "Rob" + p(XSCoreParamsKey).HartId.toString
1417    val debug_instTable = ChiselDB.createTable(instTableName, new InstInfoEntry)
1418    for (wb <- exuWBs) {
1419      when(wb.valid) {
1420        val debug_instData = Wire(new InstInfoEntry)
1421        val idx = wb.bits.robIdx.value
1422        debug_instData.robIdx := idx
1423        debug_instData.dvaddr := wb.bits.debug.vaddr
1424        debug_instData.dpaddr := wb.bits.debug.paddr
1425        debug_instData.issueTime := wb.bits.debugInfo.issueTime
1426        debug_instData.writebackTime := wb.bits.debugInfo.writebackTime
1427        debug_instData.dispatchLatency := wb.bits.debugInfo.dispatchTime - wb.bits.debugInfo.renameTime
1428        debug_instData.enqRsLatency := wb.bits.debugInfo.enqRsTime - wb.bits.debugInfo.dispatchTime
1429        debug_instData.selectLatency := wb.bits.debugInfo.selectTime - wb.bits.debugInfo.enqRsTime
1430        debug_instData.issueLatency := wb.bits.debugInfo.issueTime - wb.bits.debugInfo.selectTime
1431        debug_instData.executeLatency := wb.bits.debugInfo.writebackTime - wb.bits.debugInfo.issueTime
1432        debug_instData.rsFuLatency := wb.bits.debugInfo.writebackTime - wb.bits.debugInfo.enqRsTime
1433        debug_instData.tlbLatency := wb.bits.debugInfo.tlbRespTime - wb.bits.debugInfo.tlbFirstReqTime
1434        debug_instData.exceptType := Cat(wb.bits.exceptionVec.getOrElse(ExceptionVec(false.B)))
1435        debug_instData.lsInfo := debug_lsInfo(idx)
1436        // debug_instData.globalID := wb.bits.uop.ctrl.debug_globalID
1437        // debug_instData.instType := wb.bits.uop.ctrl.fuType
1438        // debug_instData.ivaddr := wb.bits.uop.cf.pc
1439        // debug_instData.mdpInfo.ssid := wb.bits.uop.cf.ssid
1440        // debug_instData.mdpInfo.waitAllStore := wb.bits.uop.cf.loadWaitStrict && wb.bits.uop.cf.loadWaitBit
1441        debug_instTable.log(
1442          data = debug_instData,
1443          en = wb.valid,
1444          site = instSiteName,
1445          clock = clock,
1446          reset = reset
1447        )
1448      }
1449    }
1450  }
1451
1452
1453  //difftest signals
1454  val firstValidCommit = (deqPtr + PriorityMux(io.commits.commitValid, VecInit(List.tabulate(CommitWidth)(_.U(log2Up(CommitWidth).W))))).value
1455
1456  val wdata = Wire(Vec(CommitWidth, UInt(XLEN.W)))
1457  val wpc = Wire(Vec(CommitWidth, UInt(XLEN.W)))
1458
1459  for (i <- 0 until CommitWidth) {
1460    val idx = deqPtrVec(i).value
1461    wdata(i) := debug_exuData(idx)
1462    wpc(i) := SignExt(commitDebugUop(i).pc, XLEN)
1463  }
1464
1465  if (env.EnableDifftest || env.AlwaysBasicDiff) {
1466    // These are the structures used by difftest only and should be optimized after synthesis.
1467    val dt_eliminatedMove = Mem(RobSize, Bool())
1468    val dt_isRVC = Mem(RobSize, Bool())
1469    val dt_exuDebug = Reg(Vec(RobSize, new DebugBundle))
1470    for (i <- 0 until RenameWidth) {
1471      when(canEnqueue(i)) {
1472        dt_eliminatedMove(allocatePtrVec(i).value) := io.enq.req(i).bits.eliminatedMove
1473        dt_isRVC(allocatePtrVec(i).value) := io.enq.req(i).bits.preDecodeInfo.isRVC
1474      }
1475    }
1476    for (wb <- exuWBs) {
1477      when(wb.valid) {
1478        val wbIdx = wb.bits.robIdx.value
1479        dt_exuDebug(wbIdx) := wb.bits.debug
1480      }
1481    }
1482    // Always instantiate basic difftest modules.
1483    for (i <- 0 until CommitWidth) {
1484      val uop = commitDebugUop(i)
1485      val commitInfo = io.commits.info(i)
1486      val ptr = deqPtrVec(i).value
1487      val exuOut = dt_exuDebug(ptr)
1488      val eliminatedMove = dt_eliminatedMove(ptr)
1489      val isRVC = dt_isRVC(ptr)
1490
1491      val difftest = DifftestModule(new DiffInstrCommit(MaxPhyRegs), delay = 3, dontCare = true)
1492      val dt_skip = Mux(eliminatedMove, false.B, exuOut.isSkipDiff)
1493      difftest.coreid := io.hartId
1494      difftest.index := i.U
1495      difftest.valid := io.commits.commitValid(i) && io.commits.isCommit
1496      difftest.skip := dt_skip
1497      difftest.isRVC := isRVC
1498      difftest.rfwen := io.commits.commitValid(i) && commitInfo.rfWen && commitInfo.debug_ldest.get =/= 0.U
1499      difftest.fpwen := io.commits.commitValid(i) && uop.fpWen
1500      difftest.wpdest := commitInfo.debug_pdest.get
1501      difftest.wdest := commitInfo.debug_ldest.get
1502      difftest.nFused := CommitType.isFused(commitInfo.commitType).asUInt + commitInfo.instrSize - 1.U
1503      when(difftest.valid) {
1504        assert(CommitType.isFused(commitInfo.commitType).asUInt + commitInfo.instrSize >= 1.U)
1505      }
1506      if (env.EnableDifftest) {
1507        val uop = commitDebugUop(i)
1508        difftest.pc := SignExt(uop.pc, XLEN)
1509        difftest.instr := uop.instr
1510        difftest.robIdx := ZeroExt(ptr, 10)
1511        difftest.lqIdx := ZeroExt(uop.lqIdx.value, 7)
1512        difftest.sqIdx := ZeroExt(uop.sqIdx.value, 7)
1513        difftest.isLoad := io.commits.info(i).commitType === CommitType.LOAD
1514        difftest.isStore := io.commits.info(i).commitType === CommitType.STORE
1515        // Check LoadEvent only when isAmo or isLoad and skip MMIO
1516        val difftestLoadEvent = DifftestModule(new DiffLoadEvent, delay = 3)
1517        difftestLoadEvent.coreid := io.hartId
1518        difftestLoadEvent.index := i.U
1519        val loadCheck = (FuType.isAMO(uop.fuType) || FuType.isLoad(uop.fuType)) && !dt_skip
1520        difftestLoadEvent.valid    := io.commits.commitValid(i) && io.commits.isCommit && loadCheck
1521        difftestLoadEvent.paddr    := exuOut.paddr
1522        difftestLoadEvent.opType   := uop.fuOpType
1523        difftestLoadEvent.isAtomic := FuType.isAMO(uop.fuType)
1524        difftestLoadEvent.isLoad   := FuType.isLoad(uop.fuType)
1525      }
1526    }
1527  }
1528
1529  if (env.EnableDifftest || env.AlwaysBasicDiff) {
1530    val dt_isXSTrap = Mem(RobSize, Bool())
1531    for (i <- 0 until RenameWidth) {
1532      when(canEnqueue(i)) {
1533        dt_isXSTrap(allocatePtrVec(i).value) := io.enq.req(i).bits.isXSTrap
1534      }
1535    }
1536    val trapVec = io.commits.commitValid.zip(deqPtrVec).map { case (v, d) =>
1537      io.commits.isCommit && v && dt_isXSTrap(d.value)
1538    }
1539    val hitTrap = trapVec.reduce(_ || _)
1540    val difftest = DifftestModule(new DiffTrapEvent, dontCare = true)
1541    difftest.coreid := io.hartId
1542    difftest.hasTrap := hitTrap
1543    difftest.cycleCnt := timer
1544    difftest.instrCnt := instrCnt
1545    difftest.hasWFI := hasWFI
1546
1547    if (env.EnableDifftest) {
1548      val trapCode = PriorityMux(wdata.zip(trapVec).map(x => x._2 -> x._1))
1549      val trapPC = SignExt(PriorityMux(wpc.zip(trapVec).map(x => x._2 -> x._1)), XLEN)
1550      difftest.code := trapCode
1551      difftest.pc := trapPC
1552    }
1553  }
1554
1555  //store evetn difftest information
1556  io.storeDebugInfo := DontCare
1557  if (env.EnableDifftest) {
1558    io.storeDebugInfo.map{port =>
1559      port.pc := debug_microOp(port.robidx.value).pc
1560    }
1561  }
1562
1563  val commitLoadVec = VecInit(commitLoadValid)
1564  val commitBranchVec = VecInit(commitBranchValid)
1565  val commitStoreVec = VecInit(io.commits.commitValid.zip(commitIsStore).map { case (v, t) => v && t })
1566  val perfEvents = Seq(
1567    ("rob_interrupt_num      ", io.flushOut.valid && intrEnable),
1568    ("rob_exception_num      ", io.flushOut.valid && deqHasException),
1569    ("rob_flush_pipe_num     ", io.flushOut.valid && isFlushPipe),
1570    ("rob_replay_inst_num    ", io.flushOut.valid && isFlushPipe && deqHasReplayInst),
1571    ("rob_commitUop          ", ifCommit(commitCnt)),
1572    ("rob_commitInstr        ", ifCommitReg(trueCommitCnt)),
1573    ("rob_commitInstrFused   ", ifCommitReg(fuseCommitCnt)),
1574    ("rob_commitInstrLoad    ", ifCommitReg(PopCount(RegEnable(commitLoadVec, isCommit)))),
1575    ("rob_commitInstrBranch  ", ifCommitReg(PopCount(RegEnable(commitBranchVec, isCommit)))),
1576    ("rob_commitInstrStore   ", ifCommitReg(PopCount(RegEnable(commitStoreVec, isCommit)))),
1577    ("rob_walkInstr          ", Mux(io.commits.isWalk, PopCount(io.commits.walkValid), 0.U)),
1578    ("rob_walkCycle          ", (state === s_walk)),
1579    ("rob_1_4_valid          ", numValidEntries <= (RobSize / 4).U),
1580    ("rob_2_4_valid          ", numValidEntries > (RobSize / 4).U && numValidEntries <= (RobSize / 2).U),
1581    ("rob_3_4_valid          ", numValidEntries > (RobSize / 2).U && numValidEntries <= (RobSize * 3 / 4).U),
1582    ("rob_4_4_valid          ", numValidEntries > (RobSize * 3 / 4).U),
1583  )
1584  generatePerfEvent()
1585
1586  // max commit-stuck cycle
1587  val deqismmio = Mux(robEntries(deqPtr.value).valid, robEntries(deqPtr.value).mmio, false.B)
1588  val commitStuck = (!io.commits.commitValid.reduce(_ || _) || !io.commits.isCommit) && !deqismmio
1589  val commitStuckCycle = RegInit(0.U(log2Up(maxCommitStuck).W))
1590  when(commitStuck) {
1591    commitStuckCycle := commitStuckCycle + 1.U
1592  }.elsewhen(!commitStuck && RegNext(commitStuck)) {
1593    commitStuckCycle := 0.U
1594  }
1595  // check if stuck > 2^maxCommitStuckCycle
1596  val commitStuck_overflow = commitStuckCycle.andR
1597  val criticalErrors = Seq(
1598    ("rob_commit_stuck  ", commitStuck_overflow),
1599  )
1600  generateCriticalErrors()
1601
1602
1603  // dontTouch for debug
1604  if (backendParams.debugEn) {
1605    dontTouch(enqPtrVec)
1606    dontTouch(deqPtrVec)
1607    dontTouch(robEntries)
1608    dontTouch(robDeqGroup)
1609    dontTouch(robBanks)
1610    dontTouch(robBanksRaddrThisLine)
1611    dontTouch(robBanksRaddrNextLine)
1612    dontTouch(robBanksRdataThisLine)
1613    dontTouch(robBanksRdataNextLine)
1614    dontTouch(robBanksRdataThisLineUpdate)
1615    dontTouch(robBanksRdataNextLineUpdate)
1616    dontTouch(needUpdate)
1617    val exceptionWBsVec = MixedVecInit(exceptionWBs)
1618    dontTouch(exceptionWBsVec)
1619    dontTouch(commit_wDeqGroup)
1620    dontTouch(commit_vDeqGroup)
1621    dontTouch(commitSizeSumSeq)
1622    dontTouch(walkSizeSumSeq)
1623    dontTouch(commitSizeSumCond)
1624    dontTouch(walkSizeSumCond)
1625    dontTouch(commitSizeSum)
1626    dontTouch(walkSizeSum)
1627    dontTouch(realDestSizeSeq)
1628    dontTouch(walkDestSizeSeq)
1629    dontTouch(io.commits)
1630    dontTouch(commitIsVTypeVec)
1631    dontTouch(walkIsVTypeVec)
1632    dontTouch(commitValidThisLine)
1633    dontTouch(commitReadAddr_next)
1634    dontTouch(donotNeedWalk)
1635    dontTouch(walkPtrVec_next)
1636    dontTouch(walkPtrVec)
1637    dontTouch(deqPtrVec_next)
1638    dontTouch(deqPtrVecForWalk)
1639    dontTouch(snapPtrReadBank)
1640    dontTouch(snapPtrVecForWalk)
1641    dontTouch(shouldWalkVec)
1642    dontTouch(walkFinished)
1643    dontTouch(changeBankAddrToDeqPtr)
1644  }
1645  if (env.EnableDifftest) {
1646    io.commits.info.map(info => dontTouch(info.debug_pc.get))
1647  }
1648}
1649