fix(criticalError): Stop counting `wfi_cycles` when disable `wfiResume` (#4623)

* The precondition for `commitStuck_overflow` to trigger a critical
error is that `WFI` resumes after 1M(2^20) cycles.

fix(decode): block the vector decode until vsetvl has committed (#4535)

timing(StoreMisalignBuffer): fix misalign buffer enq timing (#4493)

* a misalign store will enqueue misalign buffer at s1, and revoke if it
needs at s2

fix(Svinval): remove assert related to Svinval extension in ROB (#4519)

The RISC-V manual says that:
> In typical usage, software will invalidate a range of virtual
> addresses in the addresstransla

fix(Svinval): remove assert related to Svinval extension in ROB (#4519)

The RISC-V manual says that:
> In typical usage, software will invalidate a range of virtual
> addresses in the addresstranslation caches by executing an
> SFENCE.W.INVAL instruction, executing a series of SINVAL.VMA,
> HINVAL.VVMA, or HINVAL.GVMA instructions to the addresses (and
> optionally ASIDs or VMIDs) in question, and then executing an
> SFENCE.INVAL.IR instruction.

Some additional information was obtained through
https://github.com/riscv/riscv-isa-manual/issues/1936

However, other instructions may still appear between SFENCE.W.INVAL and
SFENCE.INVAL.IR.
> Translation of any memory accesses during that sequence are subject to
> the usual uncertainty as to which translation (among old and new ones)
> is used.

Moreover, these memory accesses are not entirely unpredictable either.
> Each subsequent memory access will unpredictably use either the old
> translation or the new translation. Other behaviors can't occur.

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feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument
2. Run with "--dump-db --dump-select-db lifetime", then get the database
3. Instruction lifetime visualize run "python3 scripts/perfcct.py
"the-db-file-path" -p 1 -v | less"
4. Analysis script now is in XS-GEM5 repo, see
https://github.com/OpenXiangShan/GEM5/blob/xs-dev/util/ClockAnalysis.py

How it works:
1. Allocate one unique tag "seqNum" like GEM5 for each instruction at
fetch stage
2. Passing the "seqNum" in each pipeline
3. Recording perf data through the DPIC interface

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feat(backend): make wfi timeout configurable (#4491)

feat: mark topdown, cycle and instr as critical perf counters (#4431)

feat(Difftest): add multi-core vector load check (#4361)

Currently, we implement the multi core vector load check in difftest.
We modified difftest and NEMU and added related content in XiangShan.

feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bo

feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bound.
Level-2: Fetch Latency Bound, Fetch Bandwidth Bound, Branch
Missprediction, machine clears, Core Bound, Memory Bound.
Leval-3: L1 Bound, L2 Bound, L3 Bound, Mem Bound, Store Bound.

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fix(rob): fix needflush when rob has redirect (#4153)

* This PR fix the boundary case where rob has redirect.
* The `needflush` signal should be `true` when rob flushes all entries.

Co-authored-by:

fix(rob): fix needflush when rob has redirect (#4153)

* This PR fix the boundary case where rob has redirect.
* The `needflush` signal should be `true` when rob flushes all entries.

Co-authored-by: xiaofeibao-xjtu <[email protected]>

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fix(rob): when deq is vls exception, wait 2 cycle for execeptionGen out

timing(rob): remove bolck logic deqHasFlushPipe because deqNeedFlush includes deqHasFlushPipe

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
Wh

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
WhenContext. For example, when(cond1){XSDebug(cond2, pable)} to
XSDebug(cond1 && cond2, pable)

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timing(Rob): modify selection from robentries to robDeqGroup (#4067)

fix(rob): fix bug of redirect when all robEntries need flush

fix(rob): fix bug of canAcceptForDispatch

timing(rob): enqRob pipe for better timing

timing(backend): pipe robCommits for better timing and area

feat(backend): NewDispatch

fix(CSR, Trace): remove reg `isXRetFlag` in CSR

* remove useless reg `isXRetFlag` in CSR.scala
* fix update of itype for xret instruction

fix(trace): remove traceTrap & tracePriv from trace pipeline

fix(trace): fix `tracePipe` in pipeline

* fix itype for branch after writeback
* update itype to DeqGroup when branch instruction commit at next cycle after writeback.
* fix ftqoffset in commitIn

fix(trace): fix `tracePipe` in pipeline

* fix itype for branch after writeback
* update itype to DeqGroup when branch instruction commit at next cycle after writeback.
* fix ftqoffset in commitInfo for fuse instruction
* fix `iretire` in rename

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feat(trace): add TraceCoreInterface in top.

feat(trace): add trace buffer.

feat(Backend): add support for Zacas extension

misc: remove assert temporarily