1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, SchedulerType} 19import xiangshan.backend.issue.EntryBundles._ 20import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 21import xiangshan.backend.rob.RobPtr 22import xiangshan.frontend._ 23import xiangshan.mem.{LqPtr, SqPtr} 24import yunsuan.vector.VIFuParam 25import xiangshan.backend.trace._ 26import utility._ 27 28object Bundles { 29 /** 30 * Connect Same Name Port like bundleSource := bundleSinkBudle. 31 * 32 * There is no limit to the number of ports on both sides. 33 * 34 * Don't forget to connect the remaining ports! 35 */ 36 def connectSamePort (bundleSource: Bundle, bundleSink: Bundle):Unit = { 37 bundleSource.elements.foreach { case (name, data) => 38 if (bundleSink.elements.contains(name)) 39 data := bundleSink.elements(name) 40 } 41 } 42 // frontend -> backend 43 class StaticInst(implicit p: Parameters) extends XSBundle { 44 val instr = UInt(32.W) 45 val pc = UInt(VAddrBits.W) 46 val foldpc = UInt(MemPredPCWidth.W) 47 val exceptionVec = ExceptionVec() 48 val isFetchMalAddr = Bool() 49 val trigger = TriggerAction() 50 val preDecodeInfo = new PreDecodeInfo 51 val pred_taken = Bool() 52 val crossPageIPFFix = Bool() 53 val ftqPtr = new FtqPtr 54 val ftqOffset = UInt(log2Up(PredictWidth).W) 55 val isLastInFtqEntry = Bool() 56 57 def connectCtrlFlow(source: CtrlFlow): Unit = { 58 this.instr := source.instr 59 this.pc := source.pc 60 this.foldpc := source.foldpc 61 this.exceptionVec := source.exceptionVec 62 this.isFetchMalAddr := source.backendException 63 this.trigger := source.trigger 64 this.preDecodeInfo := source.pd 65 this.pred_taken := source.pred_taken 66 this.crossPageIPFFix := source.crossPageIPFFix 67 this.ftqPtr := source.ftqPtr 68 this.ftqOffset := source.ftqOffset 69 this.isLastInFtqEntry := source.isLastInFtqEntry 70 } 71 } 72 73 // StaticInst --[Decode]--> DecodedInst 74 class DecodedInst(implicit p: Parameters) extends XSBundle { 75 def numSrc = backendParams.numSrc 76 // passed from StaticInst 77 val instr = UInt(32.W) 78 val pc = UInt(VAddrBits.W) 79 val foldpc = UInt(MemPredPCWidth.W) 80 val exceptionVec = ExceptionVec() 81 val isFetchMalAddr = Bool() 82 val trigger = TriggerAction() 83 val preDecodeInfo = new PreDecodeInfo 84 val pred_taken = Bool() 85 val crossPageIPFFix = Bool() 86 val ftqPtr = new FtqPtr 87 val ftqOffset = UInt(log2Up(PredictWidth).W) 88 // decoded 89 val srcType = Vec(numSrc, SrcType()) 90 val lsrc = Vec(numSrc, UInt(LogicRegsWidth.W)) 91 val ldest = UInt(LogicRegsWidth.W) 92 val fuType = FuType() 93 val fuOpType = FuOpType() 94 val rfWen = Bool() 95 val fpWen = Bool() 96 val vecWen = Bool() 97 val v0Wen = Bool() 98 val vlWen = Bool() 99 val isXSTrap = Bool() 100 val waitForward = Bool() // no speculate execution 101 val blockBackward = Bool() 102 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 103 val canRobCompress = Bool() 104 val selImm = SelImm() 105 val imm = UInt(ImmUnion.maxLen.W) 106 val fpu = new FPUCtrlSignals 107 val vpu = new VPUCtrlSignals 108 val vlsInstr = Bool() 109 val wfflags = Bool() 110 val isMove = Bool() 111 val uopIdx = UopIdx() 112 val uopSplitType = UopSplitType() 113 val isVset = Bool() 114 val firstUop = Bool() 115 val lastUop = Bool() 116 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 117 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 118 val commitType = CommitType() // Todo: remove it 119 val needFrm = new NeedFrmBundle 120 121 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 122 123 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 124 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 125 126 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 127 val decoder: Seq[UInt] = ListLookup( 128 inst, XDecode.decodeDefault.map(bitPatToUInt), 129 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 130 ) 131 allSignals zip decoder foreach { case (s, d) => s := d } 132 debug_fuType.foreach(_ := fuType) 133 this 134 } 135 136 def isSoftPrefetch: Bool = { 137 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 138 } 139 140 def connectStaticInst(source: StaticInst): Unit = { 141 for ((name, data) <- this.elements) { 142 if (source.elements.contains(name)) { 143 data := source.elements(name) 144 } 145 } 146 } 147 } 148 149 class TrapInstInfo(implicit p: Parameters) extends XSBundle { 150 val instr = UInt(32.W) 151 val ftqPtr = new FtqPtr 152 val ftqOffset = UInt(log2Up(PredictWidth).W) 153 154 def needFlush(ftqPtr: FtqPtr, ftqOffset: UInt): Bool ={ 155 val sameFlush = this.ftqPtr === ftqPtr && this.ftqOffset > ftqOffset 156 sameFlush || isAfter(this.ftqPtr, ftqPtr) 157 } 158 159 def fromDecodedInst(decodedInst: DecodedInst): this.type = { 160 this.instr := decodedInst.instr 161 this.ftqPtr := decodedInst.ftqPtr 162 this.ftqOffset := decodedInst.ftqOffset 163 this 164 } 165 } 166 167 // DecodedInst --[Rename]--> DynInst 168 class DynInst(implicit p: Parameters) extends XSBundle { 169 def numSrc = backendParams.numSrc 170 // passed from StaticInst 171 val instr = UInt(32.W) 172 val pc = UInt(VAddrBits.W) 173 val foldpc = UInt(MemPredPCWidth.W) 174 val exceptionVec = ExceptionVec() 175 val isFetchMalAddr = Bool() 176 val hasException = Bool() 177 val trigger = TriggerAction() 178 val preDecodeInfo = new PreDecodeInfo 179 val pred_taken = Bool() 180 val crossPageIPFFix = Bool() 181 val ftqPtr = new FtqPtr 182 val ftqOffset = UInt(log2Up(PredictWidth).W) 183 // passed from DecodedInst 184 val srcType = Vec(numSrc, SrcType()) 185 val ldest = UInt(LogicRegsWidth.W) 186 val fuType = FuType() 187 val fuOpType = FuOpType() 188 val rfWen = Bool() 189 val fpWen = Bool() 190 val vecWen = Bool() 191 val v0Wen = Bool() 192 val vlWen = Bool() 193 val isXSTrap = Bool() 194 val waitForward = Bool() // no speculate execution 195 val blockBackward = Bool() 196 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 197 val canRobCompress = Bool() 198 val selImm = SelImm() 199 val imm = UInt(32.W) 200 val fpu = new FPUCtrlSignals 201 val vpu = new VPUCtrlSignals 202 val vlsInstr = Bool() 203 val wfflags = Bool() 204 val isMove = Bool() 205 val isDropAmocasSta = Bool() 206 val uopIdx = UopIdx() 207 val isVset = Bool() 208 val firstUop = Bool() 209 val lastUop = Bool() 210 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 211 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 212 val commitType = CommitType() 213 // rename 214 val srcState = Vec(numSrc, SrcState()) 215 val srcLoadDependency = Vec(numSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 216 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 217 val pdest = UInt(PhyRegIdxWidth.W) 218 // reg cache 219 val useRegCache = Vec(backendParams.numIntRegSrc, Bool()) 220 val regCacheIdx = Vec(backendParams.numIntRegSrc, UInt(RegCacheIdxWidth.W)) 221 val robIdx = new RobPtr 222 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 223 val dirtyFs = Bool() 224 val dirtyVs = Bool() 225 val traceBlockInPipe = new TracePipe(IretireWidthInPipe) 226 227 val eliminatedMove = Bool() 228 // Take snapshot at this CFI inst 229 val snapshot = Bool() 230 val debugInfo = new PerfDebugInfo 231 val storeSetHit = Bool() // inst has been allocated an store set 232 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 233 // Load wait is needed 234 // load inst will not be executed until former store (predicted by mdp) addr calcuated 235 val loadWaitBit = Bool() 236 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 237 // load inst will not be executed until ALL former store addr calcuated 238 val loadWaitStrict = Bool() 239 val ssid = UInt(SSIDWidth.W) 240 // Todo 241 val lqIdx = new LqPtr 242 val sqIdx = new SqPtr 243 // debug module 244 val singleStep = Bool() 245 // schedule 246 val replayInst = Bool() 247 248 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 249 250 val numLsElem = NumLsElem() 251 252 def getDebugFuType: UInt = debug_fuType.getOrElse(fuType) 253 254 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 255 def isLUI32: Bool = this.selImm === SelImm.IMM_LUI32 256 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 257 258 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 259 def isSvinval(flush: Bool) = FuType.isFence(fuType) && 260 Cat(Seq(FenceOpType.sfence, FenceOpType.hfence_v, FenceOpType.hfence_g).map(_ === fuOpType)).orR && !flush 261 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 262 def isNotSvinval = !FuType.isFence(fuType) 263 264 def isHls: Bool = { 265 fuType === FuType.ldu.U && LSUOpType.isHlv(fuOpType) || fuType === FuType.stu.U && LSUOpType.isHsv(fuOpType) 266 } 267 268 def isAMOCAS: Bool = FuType.isAMO(fuType) && LSUOpType.isAMOCAS(fuOpType) 269 270 def srcIsReady: Vec[Bool] = { 271 VecInit(this.srcType.zip(this.srcState).map { 272 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 273 }) 274 } 275 276 def clearExceptions( 277 exceptionBits: Seq[Int] = Seq(), 278 flushPipe : Boolean = false, 279 replayInst : Boolean = false 280 ): DynInst = { 281 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 282 if (!flushPipe) { this.flushPipe := false.B } 283 if (!replayInst) { this.replayInst := false.B } 284 this 285 } 286 287 def needWriteRf: Bool = rfWen || fpWen || vecWen || v0Wen || vlWen 288 } 289 290 trait BundleSource { 291 var wakeupSource = "undefined" 292 var idx = 0 293 } 294 295 /** 296 * 297 * @param pregIdxWidth index width of preg 298 * @param exuIndices exu indices of wakeup bundle 299 */ 300 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int])(implicit p: Parameters) extends XSBundle { 301 val rfWen = Bool() 302 val fpWen = Bool() 303 val vecWen = Bool() 304 val v0Wen = Bool() 305 val vlWen = Bool() 306 val pdest = UInt(pregIdxWidth.W) 307 308 /** 309 * @param successor Seq[(psrc, srcType)] 310 * @return Seq[if wakeup psrc] 311 */ 312 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 313 successor.map { case (thatPsrc, srcType) => 314 val pdestMatch = pdest === thatPsrc 315 pdestMatch && ( 316 SrcType.isFp(srcType) && this.fpWen || 317 SrcType.isXp(srcType) && this.rfWen || 318 SrcType.isVp(srcType) && this.vecWen 319 ) && valid 320 } 321 } 322 def wakeUpV0(successor: (UInt, UInt), valid: Bool): Bool = { 323 val (thatPsrc, srcType) = successor 324 val pdestMatch = pdest === thatPsrc 325 pdestMatch && ( 326 SrcType.isV0(srcType) && this.v0Wen 327 ) && valid 328 } 329 def wakeUpVl(successor: (UInt, UInt), valid: Bool): Bool = { 330 val (thatPsrc, srcType) = successor 331 val pdestMatch = pdest === thatPsrc 332 pdestMatch && ( 333 SrcType.isVp(srcType) && this.vlWen 334 ) && valid 335 } 336 def wakeUpFromIQ(successor: Seq[(UInt, UInt)]): Seq[Bool] = { 337 successor.map { case (thatPsrc, srcType) => 338 val pdestMatch = pdest === thatPsrc 339 pdestMatch && ( 340 SrcType.isFp(srcType) && this.fpWen || 341 SrcType.isXp(srcType) && this.rfWen || 342 SrcType.isVp(srcType) && this.vecWen 343 ) 344 } 345 } 346 def wakeUpV0FromIQ(successor: (UInt, UInt)): Bool = { 347 val (thatPsrc, srcType) = successor 348 val pdestMatch = pdest === thatPsrc 349 pdestMatch && ( 350 SrcType.isV0(srcType) && this.v0Wen 351 ) 352 } 353 def wakeUpVlFromIQ(successor: (UInt, UInt)): Bool = { 354 val (thatPsrc, srcType) = successor 355 val pdestMatch = pdest === thatPsrc 356 pdestMatch && ( 357 SrcType.isVp(srcType) && this.vlWen 358 ) 359 } 360 361 def hasOnlyOneSource: Boolean = exuIndices.size == 1 362 363 def hasMultiSources: Boolean = exuIndices.size > 1 364 365 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 366 367 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 368 369 def exuIdx: Int = { 370 require(hasOnlyOneSource) 371 this.exuIndices.head 372 } 373 } 374 375 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams)(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 376 377 } 378 379 class IssueQueueIQWakeUpBundle( 380 exuIdx: Int, 381 backendParams: BackendParams, 382 copyWakeupOut: Boolean = false, 383 copyNum: Int = 0 384 )(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 385 val loadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 386 val is0Lat = Bool() 387 val params = backendParams.allExuParams.filter(_.exuIdx == exuIdx).head 388 val rcDest = OptionWrapper(params.needWriteRegCache, UInt(RegCacheIdxWidth.W)) 389 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 390 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 391 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 392 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 393 val v0WenCopy = OptionWrapper(copyWakeupOut && params.needV0Wen, Vec(copyNum, Bool())) 394 val vlWenCopy = OptionWrapper(copyWakeupOut && params.needVlWen, Vec(copyNum, Bool())) 395 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 396 397 def fromExuInput(exuInput: ExuInput): Unit = { 398 this.rfWen := exuInput.rfWen.getOrElse(false.B) 399 this.fpWen := exuInput.fpWen.getOrElse(false.B) 400 this.vecWen := exuInput.vecWen.getOrElse(false.B) 401 this.v0Wen := exuInput.v0Wen.getOrElse(false.B) 402 this.vlWen := exuInput.vlWen.getOrElse(false.B) 403 this.pdest := exuInput.pdest 404 } 405 } 406 407 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 408 // vtype 409 val vill = Bool() 410 val vma = Bool() // 1: agnostic, 0: undisturbed 411 val vta = Bool() // 1: agnostic, 0: undisturbed 412 val vsew = VSew() 413 val vlmul = VLmul() // 1/8~8 --> -3~3 414 415 // spec vtype 416 val specVill = Bool() 417 val specVma = Bool() // 1: agnostic, 0: undisturbed 418 val specVta = Bool() // 1: agnostic, 0: undisturbed 419 val specVsew = VSew() 420 val specVlmul = VLmul() // 1/8~8 --> -3~3 421 422 val vm = Bool() // 0: need v0.t 423 val vstart = Vl() 424 425 // float rounding mode 426 val frm = Frm() 427 // scalar float instr and vector float reduction 428 val fpu = Fpu() 429 // vector fix int rounding mode 430 val vxrm = Vxrm() 431 // vector uop index, exclude other non-vector uop 432 val vuopIdx = UopIdx() 433 val lastUop = Bool() 434 // maybe used if data dependancy 435 val vmask = UInt(V0Data().dataWidth.W) 436 val vl = Vl() 437 438 // vector load/store 439 val nf = Nf() 440 val veew = VEew() 441 442 val isReverse = Bool() // vrsub, vrdiv 443 val isExt = Bool() 444 val isNarrow = Bool() 445 val isDstMask = Bool() // vvm, vvvm, mmm 446 val isOpMask = Bool() // vmand, vmnand 447 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 448 449 val isDependOldVd = Bool() // some instruction's computation depends on oldvd 450 val isWritePartVd = Bool() // some instruction's computation writes part of vd, such as vredsum 451 452 val isVleff = Bool() // vleff 453 454 def vtype: VType = { 455 val res = Wire(VType()) 456 res.illegal := this.vill 457 res.vma := this.vma 458 res.vta := this.vta 459 res.vsew := this.vsew 460 res.vlmul := this.vlmul 461 res 462 } 463 464 def specVType: VType = { 465 val res = Wire(VType()) 466 res.illegal := this.specVill 467 res.vma := this.specVma 468 res.vta := this.specVta 469 res.vsew := this.specVsew 470 res.vlmul := this.specVlmul 471 res 472 } 473 474 def vconfig: VConfig = { 475 val res = Wire(VConfig()) 476 res.vtype := this.vtype 477 res.vl := this.vl 478 res 479 } 480 481 def connectVType(source: VType): Unit = { 482 this.vill := source.illegal 483 this.vma := source.vma 484 this.vta := source.vta 485 this.vsew := source.vsew 486 this.vlmul := source.vlmul 487 } 488 } 489 490 class NeedFrmBundle(implicit p: Parameters) extends XSBundle { 491 val scalaNeedFrm = Bool() 492 val vectorNeedFrm = Bool() 493 } 494 495 // DynInst --[IssueQueue]--> DataPath 496 class IssueQueueIssueBundle( 497 iqParams: IssueBlockParams, 498 val exuParams: ExeUnitParams, 499 )(implicit 500 p: Parameters 501 ) extends XSBundle { 502 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 503 504 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 505 rfReadDataCfgSet.map((set: Set[DataConfig]) => 506 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 507 ) 508 )) 509 510 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 511 val rcIdx = OptionWrapper(exuParams.needReadRegCache, Vec(exuParams.numRegSrc, UInt(RegCacheIdxWidth.W))) // used to select regcache data 512 val immType = SelImm() // used to select imm extractor 513 val common = new ExuInput(exuParams) 514 val addrOH = UInt(iqParams.numEntries.W) 515 516 def exuIdx = exuParams.exuIdx 517 def getSource: SchedulerType = exuParams.getWBSource 518 519 def getRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 520 rf.zip(srcType).map { 521 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 522 makeValid(issueValid, rfRd.head) 523 }.toSeq 524 } 525 } 526 527 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 528 val issueQueueParams = this.params 529 val og0resp = Valid(new EntryDeqRespBundle) 530 val og1resp = Valid(new EntryDeqRespBundle) 531 } 532 533 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 534 private val intCertainLat = params.intLatencyCertain 535 private val fpCertainLat = params.fpLatencyCertain 536 private val vfCertainLat = params.vfLatencyCertain 537 private val v0CertainLat = params.v0LatencyCertain 538 private val vlCertainLat = params.vlLatencyCertain 539 private val intLat = params.intLatencyValMax 540 private val fpLat = params.fpLatencyValMax 541 private val vfLat = params.vfLatencyValMax 542 private val v0Lat = params.v0LatencyValMax 543 private val vlLat = params.vlLatencyValMax 544 545 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 546 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 547 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 548 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 549 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 550 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 551 val fpDeqRespSet = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 552 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 553 val v0DeqRespSet = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 554 val vlDeqRespSet = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 555 } 556 557 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 558 private val intCertainLat = params.intLatencyCertain 559 private val fpCertainLat = params.fpLatencyCertain 560 private val vfCertainLat = params.vfLatencyCertain 561 private val v0CertainLat = params.v0LatencyCertain 562 private val vlCertainLat = params.vlLatencyCertain 563 private val intLat = params.intLatencyValMax 564 private val fpLat = params.fpLatencyValMax 565 private val vfLat = params.vfLatencyValMax 566 private val v0Lat = params.v0LatencyValMax 567 private val vlLat = params.vlLatencyValMax 568 569 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 570 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 571 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 572 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 573 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 574 } 575 576 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 577 private val intCertainLat = params.intLatencyCertain 578 private val fpCertainLat = params.fpLatencyCertain 579 private val vfCertainLat = params.vfLatencyCertain 580 private val v0CertainLat = params.v0LatencyCertain 581 private val vlCertainLat = params.vlLatencyCertain 582 583 val intConflict = OptionWrapper(intCertainLat, Bool()) 584 val fpConflict = OptionWrapper(fpCertainLat, Bool()) 585 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 586 val v0Conflict = OptionWrapper(v0CertainLat, Bool()) 587 val vlConflict = OptionWrapper(vlCertainLat, Bool()) 588 } 589 590 class ImmInfo extends Bundle { 591 val imm = UInt(32.W) 592 val immType = SelImm() 593 } 594 595 // DataPath --[ExuInput]--> Exu 596 class ExuInput(val params: ExeUnitParams, copyWakeupOut:Boolean = false, copyNum:Int = 0, hasCopySrc: Boolean = false)(implicit p: Parameters) extends XSBundle { 597 val fuType = FuType() 598 val fuOpType = FuOpType() 599 val src = Vec(params.numRegSrc, UInt(params.srcDataBitsMax.W)) 600 val copySrc = if(hasCopySrc) Some(Vec(params.numCopySrc, Vec(if(params.numRegSrc < 2) 1 else 2, UInt(params.srcDataBitsMax.W)))) else None 601 val imm = UInt(64.W) 602 val nextPcOffset = OptionWrapper(params.hasBrhFu, UInt((log2Up(PredictWidth) + 1).W)) 603 val robIdx = new RobPtr 604 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 605 val isFirstIssue = Bool() // Only used by store yet 606 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 607 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 608 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 609 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 610 val v0WenCopy = OptionWrapper(copyWakeupOut && params.needV0Wen, Vec(copyNum, Bool())) 611 val vlWenCopy = OptionWrapper(copyWakeupOut && params.needVlWen, Vec(copyNum, Bool())) 612 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 613 val pdest = UInt(params.wbPregIdxWidth.W) 614 val rfWen = if (params.needIntWen) Some(Bool()) else None 615 val fpWen = if (params.needFpWen) Some(Bool()) else None 616 val vecWen = if (params.needVecWen) Some(Bool()) else None 617 val v0Wen = if (params.needV0Wen) Some(Bool()) else None 618 val vlWen = if (params.needVlWen) Some(Bool()) else None 619 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 620 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 621 val flushPipe = if (params.flushPipe) Some(Bool()) else None 622 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 623 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 624 val ftqIdx = if (params.needPc || params.replayInst || params.hasStoreAddrFu || params.hasCSR) 625 Some(new FtqPtr) else None 626 val ftqOffset = if (params.needPc || params.replayInst || params.hasStoreAddrFu || params.hasCSR) 627 Some(UInt(log2Up(PredictWidth).W)) else None 628 val predictInfo = if (params.needPdInfo) Some(new Bundle { 629 val target = UInt(VAddrData().dataWidth.W) 630 val taken = Bool() 631 }) else None 632 val loadWaitBit = OptionWrapper(params.hasLoadExu, Bool()) 633 val waitForRobIdx = OptionWrapper(params.hasLoadExu, new RobPtr) // store set predicted previous store robIdx 634 val storeSetHit = OptionWrapper(params.hasLoadExu, Bool()) // inst has been allocated an store set 635 val loadWaitStrict = OptionWrapper(params.hasLoadExu, Bool()) // load inst will not be executed until ALL former store addr calcuated 636 val ssid = OptionWrapper(params.hasLoadExu, UInt(SSIDWidth.W)) 637 // only vector load store need 638 val numLsElem = OptionWrapper(params.hasVecLsFu, NumLsElem()) 639 640 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 641 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 642 val dataSources = Vec(params.numRegSrc, DataSource()) 643 val exuSources = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuSource(params))) 644 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 645 val loadDependency = OptionWrapper(params.needLoadDependency, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 646 647 val perfDebugInfo = new PerfDebugInfo() 648 649 def exuIdx = this.params.exuIdx 650 651 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 652 // src is assigned to rfReadData 653 this.fuType := source.common.fuType 654 this.fuOpType := source.common.fuOpType 655 this.imm := source.common.imm 656 this.robIdx := source.common.robIdx 657 this.pdest := source.common.pdest 658 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 659 this.iqIdx := source.common.iqIdx // Only used by mem feedback 660 this.dataSources := source.common.dataSources 661 this.exuSources .foreach(_ := source.common.exuSources.get) 662 this.rfWen .foreach(_ := source.common.rfWen.get) 663 this.fpWen .foreach(_ := source.common.fpWen.get) 664 this.vecWen .foreach(_ := source.common.vecWen.get) 665 this.v0Wen .foreach(_ := source.common.v0Wen.get) 666 this.vlWen .foreach(_ := source.common.vlWen.get) 667 this.fpu .foreach(_ := source.common.fpu.get) 668 this.vpu .foreach(_ := source.common.vpu.get) 669 this.flushPipe .foreach(_ := source.common.flushPipe.get) 670 this.pc .foreach(_ := source.common.pc.get) 671 this.preDecode .foreach(_ := source.common.preDecode.get) 672 this.nextPcOffset .foreach(_ := source.common.nextPcOffset.get) 673 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 674 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 675 this.predictInfo .foreach(_ := source.common.predictInfo.get) 676 this.loadWaitBit .foreach(_ := source.common.loadWaitBit.get) 677 this.waitForRobIdx .foreach(_ := source.common.waitForRobIdx.get) 678 this.storeSetHit .foreach(_ := source.common.storeSetHit.get) 679 this.loadWaitStrict.foreach(_ := source.common.loadWaitStrict.get) 680 this.ssid .foreach(_ := source.common.ssid.get) 681 this.lqIdx .foreach(_ := source.common.lqIdx.get) 682 this.sqIdx .foreach(_ := source.common.sqIdx.get) 683 this.numLsElem .foreach(_ := source.common.numLsElem.get) 684 this.srcTimer .foreach(_ := source.common.srcTimer.get) 685 this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1)) 686 } 687 } 688 689 // ExuInput --[FuncUnit]--> ExuOutput 690 class ExuOutput( 691 val params: ExeUnitParams, 692 )(implicit 693 val p: Parameters 694 ) extends Bundle with BundleSource with HasXSParameter { 695 val data = Vec(params.wbPathNum, UInt(params.destDataBitsMax.W)) 696 val pdest = UInt(params.wbPregIdxWidth.W) 697 val robIdx = new RobPtr 698 val intWen = if (params.needIntWen) Some(Bool()) else None 699 val fpWen = if (params.needFpWen) Some(Bool()) else None 700 val vecWen = if (params.needVecWen) Some(Bool()) else None 701 val v0Wen = if (params.needV0Wen) Some(Bool()) else None 702 val vlWen = if (params.needVlWen) Some(Bool()) else None 703 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 704 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 705 val wflags = if (params.writeFflags) Some(Bool()) else None 706 val vxsat = if (params.writeVxsat) Some(Bool()) else None 707 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 708 val flushPipe = if (params.flushPipe) Some(Bool()) else None 709 val replay = if (params.replayInst) Some(Bool()) else None 710 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 711 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 712 Some(new SqPtr()) else None 713 val trigger = if (params.trigger) Some(TriggerAction()) else None 714 // uop info 715 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 716 // vldu used only 717 val vls = OptionWrapper(params.hasVLoadFu, new Bundle { 718 val vpu = new VPUCtrlSignals 719 val oldVdPsrc = UInt(PhyRegIdxWidth.W) 720 val vdIdx = UInt(3.W) 721 val vdIdxInField = UInt(3.W) 722 val isIndexed = Bool() 723 val isMasked = Bool() 724 val isStrided = Bool() 725 val isWhole = Bool() 726 val isVecLoad = Bool() 727 val isVlm = Bool() 728 }) 729 val debug = new DebugBundle 730 val debugInfo = new PerfDebugInfo 731 } 732 733 // ExuOutput + DynInst --> WriteBackBundle 734 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 735 val rfWen = Bool() 736 val fpWen = Bool() 737 val vecWen = Bool() 738 val v0Wen = Bool() 739 val vlWen = Bool() 740 val pdest = UInt(params.pregIdxWidth(backendParams).W) 741 val data = UInt(params.dataWidth.W) 742 val robIdx = new RobPtr()(p) 743 val flushPipe = Bool() 744 val replayInst = Bool() 745 val redirect = ValidIO(new Redirect) 746 val fflags = UInt(5.W) 747 val vxsat = Bool() 748 val exceptionVec = ExceptionVec() 749 val debug = new DebugBundle 750 val debugInfo = new PerfDebugInfo 751 752 this.wakeupSource = s"WB(${params.toString})" 753 754 def fromExuOutput(source: ExuOutput, wbType: String) = { 755 val typeMap = Map("int" -> 0, "fp" -> 1, "vf" -> 2, "v0" -> 3, "vl" -> 4) 756 this.rfWen := source.intWen.getOrElse(false.B) 757 this.fpWen := source.fpWen.getOrElse(false.B) 758 this.vecWen := source.vecWen.getOrElse(false.B) 759 this.v0Wen := source.v0Wen.getOrElse(false.B) 760 this.vlWen := source.vlWen.getOrElse(false.B) 761 this.pdest := source.pdest 762 this.data := source.data(source.params.wbIndex(typeMap(wbType))) 763 this.robIdx := source.robIdx 764 this.flushPipe := source.flushPipe.getOrElse(false.B) 765 this.replayInst := source.replay.getOrElse(false.B) 766 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 767 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 768 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 769 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 770 this.debug := source.debug 771 this.debugInfo := source.debugInfo 772 } 773 774 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 775 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 776 rfWrite.wen := this.rfWen && fire 777 rfWrite.addr := this.pdest 778 rfWrite.data := this.data 779 rfWrite.intWen := this.rfWen 780 rfWrite.fpWen := false.B 781 rfWrite.vecWen := false.B 782 rfWrite.v0Wen := false.B 783 rfWrite.vlWen := false.B 784 rfWrite 785 } 786 787 def asFpRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 788 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(FpData()).addrWidth))) 789 rfWrite.wen := this.fpWen && fire 790 rfWrite.addr := this.pdest 791 rfWrite.data := this.data 792 rfWrite.intWen := false.B 793 rfWrite.fpWen := this.fpWen 794 rfWrite.vecWen := false.B 795 rfWrite.v0Wen := false.B 796 rfWrite.vlWen := false.B 797 rfWrite 798 } 799 800 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 801 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 802 rfWrite.wen := this.vecWen && fire 803 rfWrite.addr := this.pdest 804 rfWrite.data := this.data 805 rfWrite.intWen := false.B 806 rfWrite.fpWen := false.B 807 rfWrite.vecWen := this.vecWen 808 rfWrite.v0Wen := false.B 809 rfWrite.vlWen := false.B 810 rfWrite 811 } 812 813 def asV0RfWriteBundle(fire: Bool): RfWritePortWithConfig = { 814 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(V0Data()).addrWidth))) 815 rfWrite.wen := this.v0Wen && fire 816 rfWrite.addr := this.pdest 817 rfWrite.data := this.data 818 rfWrite.intWen := false.B 819 rfWrite.fpWen := false.B 820 rfWrite.vecWen := false.B 821 rfWrite.v0Wen := this.v0Wen 822 rfWrite.vlWen := false.B 823 rfWrite 824 } 825 826 def asVlRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 827 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VlData()).addrWidth))) 828 rfWrite.wen := this.vlWen && fire 829 rfWrite.addr := this.pdest 830 rfWrite.data := this.data 831 rfWrite.intWen := false.B 832 rfWrite.fpWen := false.B 833 rfWrite.vecWen := false.B 834 rfWrite.v0Wen := false.B 835 rfWrite.vlWen := this.vlWen 836 rfWrite 837 } 838 } 839 840 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 841 // / 842 // [IssueQueue]--> ExuInput -- 843 class ExuBypassBundle( 844 val params: ExeUnitParams, 845 )(implicit p: Parameters) extends XSBundle { 846 val intWen = Bool() 847 val data = UInt(params.destDataBitsMax.W) 848 val pdest = UInt(params.wbPregIdxWidth.W) 849 } 850 851 class ExceptionInfo(implicit p: Parameters) extends XSBundle { 852 val pc = UInt(VAddrData().dataWidth.W) 853 val instr = UInt(32.W) 854 val commitType = CommitType() 855 val exceptionVec = ExceptionVec() 856 val isPcBkpt = Bool() 857 val isFetchMalAddr = Bool() 858 val gpaddr = UInt(XLEN.W) 859 val singleStep = Bool() 860 val crossPageIPFFix = Bool() 861 val isInterrupt = Bool() 862 val isHls = Bool() 863 val vls = Bool() 864 val trigger = TriggerAction() 865 val isForVSnonLeafPTE = Bool() 866 } 867 868 object UopIdx { 869 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 870 } 871 872 object FuLatency { 873 def apply(): UInt = UInt(width.W) 874 875 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 876 } 877 878 class ExuSource(exuNum: Int)(implicit p: Parameters) extends XSBundle { 879 val value = UInt(log2Ceil(exuNum + 1).W) 880 881 val allExuNum = p(XSCoreParamsKey).backendParams.numExu 882 883 def toExuOH(num: Int, filter: Seq[Int]): Vec[Bool] = { 884 require(num == filter.size) 885 val encodedExuOH = UIntToOH(this.value)(num, 1) 886 val ext = Module(new UIntExtractor(allExuNum, filter)) 887 ext.io.in := encodedExuOH 888 VecInit(ext.io.out.asBools.zipWithIndex.map{ case(out, idx) => 889 if (filter.contains(idx)) out 890 else false.B 891 }) 892 } 893 894 def toExuOH(exuParams: ExeUnitParams): Vec[Bool] = { 895 toExuOH(exuParams.numWakeupFromIQ, exuParams.iqWakeUpSinkPairs.map(x => x.source.getExuParam(p(XSCoreParamsKey).backendParams.allExuParams).exuIdx)) 896 } 897 898 def toExuOH(iqParams: IssueBlockParams): Vec[Bool] = { 899 toExuOH(iqParams.numWakeupFromIQ, iqParams.wakeUpSourceExuIdx) 900 } 901 902 def fromExuOH(iqParams: IssueBlockParams, exuOH: UInt): UInt = { 903 val comp = Module(new UIntCompressor(allExuNum, iqParams.wakeUpSourceExuIdx)) 904 comp.io.in := exuOH 905 OHToUInt(Cat(comp.io.out, 0.U(1.W))) 906 } 907 } 908 909 object ExuSource { 910 def apply(exuNum: Int)(implicit p: Parameters) = new ExuSource(exuNum) 911 912 def apply(params: ExeUnitParams)(implicit p: Parameters) = new ExuSource(params.numWakeupFromIQ) 913 914 def apply()(implicit p: Parameters, params: IssueBlockParams) = new ExuSource(params.numWakeupFromIQ) 915 } 916 917 object ExuVec { 918 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 919 920 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 921 922 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 923 } 924 925 class CancelSignal(implicit p: Parameters) extends XSBundle { 926 val rfWen = Bool() 927 val fpWen = Bool() 928 val vecWen = Bool() 929 val v0Wen = Bool() 930 val vlWen = Bool() 931 val pdest = UInt(PhyRegIdxWidth.W) 932 } 933 934 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 935 val uop = new DynInst 936 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 937 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 938 val isFirstIssue = Bool() 939 val flowNum = OptionWrapper(isVector, NumLsElem()) 940 941 def src_rs1 = src(0) 942 def src_rs2 = src(1) 943 def src_stride = src(1) 944 def src_vs3 = src(2) 945 def src_mask = if (isVector) src(3) else 0.U 946 def src_vl = if (isVector) src(4) else 0.U 947 } 948 949 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 950 val uop = new DynInst 951 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 952 val mask = if (isVector) Some(UInt(VLEN.W)) else None 953 val vdIdx = if (isVector) Some(UInt(3.W)) else None // TODO: parameterize width 954 val vdIdxInField = if (isVector) Some(UInt(3.W)) else None 955 val isFromLoadUnit = Bool() 956 val debug = new DebugBundle 957 958 def isVls = FuType.isVls(uop.fuType) 959 } 960 961 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 962 val uop = new DynInst 963 val flag = UInt(1.W) 964 } 965 966 object LoadShouldCancel { 967 def apply(loadDependency: Option[Seq[UInt]], ldCancel: Seq[LoadCancelIO]): Bool = { 968 val ld1Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld1Cancel)).map { case (dep, cancel) => cancel && dep(0)}.reduce(_ || _)) 969 val ld2Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld2Cancel)).map { case (dep, cancel) => cancel && dep(1)}.reduce(_ || _)) 970 ld1Cancel.map(_ || ld2Cancel.get).getOrElse(false.B) 971 } 972 } 973} 974