1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.fu.FuConfig._ 26import xiangshan.backend.fu.FuType 27import xiangshan.backend.fu.fpu.FPU 28import xiangshan.backend.rob.RobLsqIO 29import xiangshan.cache.mmu.HasTlbConst 30import xiangshan.cache._ 31import xiangshan.frontend.FtqPtr 32import xiangshan.ExceptionNO._ 33import xiangshan.cache.wpu.ReplayCarry 34import xiangshan.backend.rob.RobPtr 35import xiangshan.backend.Bundles.{MemExuOutput, DynInst} 36import xiangshan.backend.fu.FuConfig.LduCfg 37 38class LoadMisalignBuffer(implicit p: Parameters) extends XSModule 39 with HasCircularQueuePtrHelper 40 with HasLoadHelper 41 with HasTlbConst 42{ 43 private val enqPortNum = LoadPipelineWidth 44 private val maxSplitNum = 2 45 46 require(maxSplitNum == 2) 47 48 private val LB = "b00".U(2.W) 49 private val LH = "b01".U(2.W) 50 private val LW = "b10".U(2.W) 51 private val LD = "b11".U(2.W) 52 53 // encode of how many bytes to shift or truncate 54 private val BYTE0 = "b000".U(3.W) 55 private val BYTE1 = "b001".U(3.W) 56 private val BYTE2 = "b010".U(3.W) 57 private val BYTE3 = "b011".U(3.W) 58 private val BYTE4 = "b100".U(3.W) 59 private val BYTE5 = "b101".U(3.W) 60 private val BYTE6 = "b110".U(3.W) 61 private val BYTE7 = "b111".U(3.W) 62 63 def getMask(sizeEncode: UInt) = LookupTree(sizeEncode, List( 64 LB -> 0x1.U, // lb 65 LH -> 0x3.U, // lh 66 LW -> 0xf.U, // lw 67 LD -> 0xff.U // ld 68 )) 69 70 def getShiftAndTruncateData(shiftEncode: UInt, truncateEncode: UInt, data: UInt) = { 71 val shiftData = LookupTree(shiftEncode, List( 72 BYTE0 -> data(63, 0), 73 BYTE1 -> data(63, 8), 74 BYTE2 -> data(63, 16), 75 BYTE3 -> data(63, 24), 76 BYTE4 -> data(63, 32), 77 BYTE5 -> data(63, 40), 78 BYTE6 -> data(63, 48), 79 BYTE7 -> data(63, 56) 80 )) 81 val truncateData = LookupTree(truncateEncode, List( 82 BYTE0 -> 0.U(XLEN.W), // can not truncate with 0 byte width 83 BYTE1 -> shiftData(7, 0), 84 BYTE2 -> shiftData(15, 0), 85 BYTE3 -> shiftData(23, 0), 86 BYTE4 -> shiftData(31, 0), 87 BYTE5 -> shiftData(39, 0), 88 BYTE6 -> shiftData(47, 0), 89 BYTE7 -> shiftData(55, 0) 90 )) 91 truncateData(XLEN - 1, 0) 92 } 93 94 def selectOldest[T <: LqWriteBundle](valid: Seq[Bool], bits: Seq[T]): (Seq[Bool], Seq[T]) = { 95 assert(valid.length == bits.length) 96 if (valid.length == 0 || valid.length == 1) { 97 (valid, bits) 98 } else if (valid.length == 2) { 99 val res = Seq.fill(2)(Wire(ValidIO(chiselTypeOf(bits(0))))) 100 for (i <- res.indices) { 101 res(i).valid := valid(i) 102 res(i).bits := bits(i) 103 } 104 val oldest = Mux(valid(0) && valid(1), 105 Mux(isAfter(bits(0).uop.robIdx, bits(1).uop.robIdx) || 106 (bits(0).uop.robIdx === bits(1).uop.robIdx && bits(0).uop.uopIdx > bits(1).uop.uopIdx), res(1), res(0)), 107 Mux(valid(0) && !valid(1), res(0), res(1))) 108 (Seq(oldest.valid), Seq(oldest.bits)) 109 } else { 110 val left = selectOldest(valid.take(valid.length / 2), bits.take(bits.length / 2)) 111 val right = selectOldest(valid.takeRight(valid.length - (valid.length / 2)), bits.takeRight(bits.length - (bits.length / 2))) 112 selectOldest(left._1 ++ right._1, left._2 ++ right._2) 113 } 114 } 115 116 val io = IO(new Bundle() { 117 val redirect = Flipped(Valid(new Redirect)) 118 val req = Vec(enqPortNum, Flipped(Decoupled(new LqWriteBundle))) 119 val rob = Flipped(new RobLsqIO) 120 val splitLoadReq = Decoupled(new LsPipelineBundle) 121 val splitLoadResp = Flipped(Valid(new LqWriteBundle)) 122 val writeBack = Decoupled(new MemExuOutput) 123 val vecWriteBack = Decoupled(new VecPipelineFeedbackIO(isVStore = false)) 124 val loadOutValid = Input(Bool()) 125 val loadVecOutValid = Input(Bool()) 126 val overwriteExpBuf = Output(new XSBundle { 127 val valid = Bool() 128 val vaddr = UInt(XLEN.W) 129 val isHyper = Bool() 130 val gpaddr = UInt(XLEN.W) 131 val isForVSnonLeafPTE = Bool() 132 }) 133 val flushLdExpBuff = Output(Bool()) 134 val loadMisalignFull = Output(Bool()) 135 }) 136 137 io.rob.mmio := 0.U.asTypeOf(Vec(LoadPipelineWidth, Bool())) 138 io.rob.uop := 0.U.asTypeOf(Vec(LoadPipelineWidth, new DynInst)) 139 140 val req_valid = RegInit(false.B) 141 val req = Reg(new LqWriteBundle) 142 143 io.loadMisalignFull := req_valid 144 145 (0 until io.req.length).map{i => 146 if (i == 0) { 147 io.req(0).ready := !req_valid && io.req(0).valid 148 } 149 else { 150 io.req(i).ready := !io.req.take(i).map(_.ready).reduce(_ || _) && !req_valid && io.req(i).valid 151 } 152 } 153 154 155 val select_req_bit = ParallelPriorityMux(io.req.map(_.valid), io.req.map(_.bits)) 156 val select_req_valid = io.req.map(_.valid).reduce(_ || _) 157 val canEnqValid = !req_valid && !select_req_bit.uop.robIdx.needFlush(io.redirect) && select_req_valid 158 when(canEnqValid) { 159 req := select_req_bit 160 req_valid := true.B 161 } 162 163 // buffer control: 164 // - s_idle: idle 165 // - s_split: split misalign laod 166 // - s_req: issue a split memory access request 167 // - s_resp: Responds to a split load access request 168 // - s_comb_wakeup_rep: Merge the data and issue a wakeup load 169 // - s_wb: writeback yo rob/vecMergeBuffer 170 val s_idle :: s_split :: s_req :: s_resp :: s_comb_wakeup_rep :: s_wb :: Nil = Enum(6) 171 val bufferState = RegInit(s_idle) 172 val splitLoadReqs = RegInit(VecInit(List.fill(maxSplitNum)(0.U.asTypeOf(new LsPipelineBundle)))) 173 val splitLoadResp = RegInit(VecInit(List.fill(maxSplitNum)(0.U.asTypeOf(new LqWriteBundle)))) 174 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 175 val unSentLoads = RegInit(0.U(maxSplitNum.W)) 176 val curPtr = RegInit(0.U(log2Ceil(maxSplitNum).W)) 177 val needWakeUpReqsWire = Wire(Bool()) 178 val needWakeUpWB = RegInit(false.B) 179 val data_select = RegEnable(genRdataOH(select_req_bit.uop), 0.U(genRdataOH(select_req_bit.uop).getWidth.W), canEnqValid) 180 181 // if there is exception or mmio in split load 182 val globalException = RegInit(false.B) 183 val globalMMIO = RegInit(false.B) 184 185 val hasException = ExceptionNO.selectByFu(io.splitLoadResp.bits.uop.exceptionVec, LduCfg).asUInt.orR 186 val isMMIO = io.splitLoadResp.bits.mmio 187 needWakeUpReqsWire := false.B 188 switch(bufferState) { 189 is (s_idle) { 190 when (req_valid) { 191 bufferState := s_split 192 } 193 } 194 195 is (s_split) { 196 bufferState := s_req 197 } 198 199 is (s_req) { 200 when (io.splitLoadReq.fire) { 201 bufferState := s_resp 202 } 203 } 204 205 is (s_resp) { 206 when (io.splitLoadResp.valid) { 207 val clearOh = UIntToOH(curPtr) 208 when (hasException || isMMIO) { 209 // commit directly when exception ocurs 210 // if any split load reaches mmio space, delegate to software loadAddrMisaligned exception 211 bufferState := s_wb 212 globalException := hasException 213 globalMMIO := isMMIO 214 } .elsewhen(io.splitLoadResp.bits.rep_info.need_rep || (unSentLoads & ~clearOh).orR) { 215 // need replay or still has unsent requests 216 bufferState := s_req 217 } .otherwise { 218 // merge the split load results 219 bufferState := s_comb_wakeup_rep 220 needWakeUpWB := !req.isvec 221 } 222 } 223 } 224 225 is (s_comb_wakeup_rep) { 226 when(!req.isvec) { 227 when(io.splitLoadReq.fire) { 228 bufferState := s_wb 229 }.otherwise { 230 bufferState := s_comb_wakeup_rep 231 } 232 needWakeUpReqsWire := true.B 233 } .otherwise { 234 bufferState := s_wb 235 } 236 237 } 238 239 is (s_wb) { 240 when(req.isvec) { 241 when(io.vecWriteBack.fire) { 242 bufferState := s_idle 243 req_valid := false.B 244 curPtr := 0.U 245 unSentLoads := 0.U 246 globalException := false.B 247 globalMMIO := false.B 248 needWakeUpWB := false.B 249 } 250 251 } .otherwise { 252 when(io.writeBack.fire) { 253 bufferState := s_idle 254 req_valid := false.B 255 curPtr := 0.U 256 unSentLoads := 0.U 257 globalException := false.B 258 globalMMIO := false.B 259 needWakeUpWB := false.B 260 } 261 } 262 263 } 264 } 265 266 val alignedType = Mux(req.isvec, req.alignedType(1,0), req.uop.fuOpType(1, 0)) 267 val highAddress = LookupTree(alignedType, List( 268 LB -> 0.U, 269 LH -> 1.U, 270 LW -> 3.U, 271 LD -> 7.U 272 )) + req.vaddr(4, 0) 273 // to see if (vaddr + opSize - 1) and vaddr are in the same 16 bytes region 274 val cross16BytesBoundary = req_valid && (highAddress(4) =/= req.vaddr(4)) 275 val aligned16BytesAddr = (req.vaddr >> 4) << 4// req.vaddr & ~("b1111".U) 276 val aligned16BytesSel = req.vaddr(3, 0) 277 278 // meta of 128 bit load 279 val new128Load = WireInit(0.U.asTypeOf(new LsPipelineBundle)) 280 // meta of split loads 281 val lowAddrLoad = WireInit(0.U.asTypeOf(new LsPipelineBundle)) 282 val highAddrLoad = WireInit(0.U.asTypeOf(new LsPipelineBundle)) 283 val lowResultShift = RegInit(0.U(3.W)) // how many bytes should we shift right when got result 284 val lowResultWidth = RegInit(0.U(3.W)) // how many bytes should we take from result 285 val highResultShift = RegInit(0.U(3.W)) 286 val highResultWidth = RegInit(0.U(3.W)) 287 288 when (bufferState === s_split) { 289 when (!cross16BytesBoundary) { 290 assert(false.B, s"There should be no non-aligned access that does not cross 16Byte boundaries.") 291 } .otherwise { 292 // split this unaligned load into `maxSplitNum` aligned loads 293 unSentLoads := Fill(maxSplitNum, 1.U(1.W)) 294 curPtr := 0.U 295 lowAddrLoad.uop := req.uop 296 lowAddrLoad.uop.exceptionVec(loadAddrMisaligned) := false.B 297 lowAddrLoad.fullva := req.fullva 298 highAddrLoad.uop := req.uop 299 highAddrLoad.uop.exceptionVec(loadAddrMisaligned) := false.B 300 highAddrLoad.fullva := req.fullva 301 302 switch (alignedType(1, 0)) { 303 is (LB) { 304 assert(false.B, "lb should not trigger miss align") 305 } 306 307 is (LH) { 308 lowAddrLoad.uop.fuOpType := LB 309 lowAddrLoad.vaddr := req.vaddr 310 lowAddrLoad.mask := 0x1.U << lowAddrLoad.vaddr(3, 0) 311 lowResultShift := BYTE0 312 lowResultWidth := BYTE1 313 314 highAddrLoad.uop.fuOpType := LB 315 highAddrLoad.vaddr := req.vaddr + 1.U 316 highAddrLoad.mask := 0x1.U << highAddrLoad.vaddr(3, 0) 317 highResultShift := BYTE0 318 highResultWidth := BYTE1 319 } 320 321 is (LW) { 322 switch (req.vaddr(1, 0)) { 323 is ("b00".U) { 324 assert(false.B, "should not trigger miss align") 325 } 326 327 is ("b01".U) { 328 lowAddrLoad.uop.fuOpType := LW 329 lowAddrLoad.vaddr := req.vaddr - 1.U 330 lowAddrLoad.mask := 0xf.U << lowAddrLoad.vaddr(3, 0) 331 lowResultShift := BYTE1 332 lowResultWidth := BYTE3 333 334 highAddrLoad.uop.fuOpType := LB 335 highAddrLoad.vaddr := req.vaddr + 3.U 336 highAddrLoad.mask := 0x1.U << highAddrLoad.vaddr(3, 0) 337 highResultShift := BYTE0 338 highResultWidth := BYTE1 339 } 340 341 is ("b10".U) { 342 lowAddrLoad.uop.fuOpType := LH 343 lowAddrLoad.vaddr := req.vaddr 344 lowAddrLoad.mask := 0x3.U << lowAddrLoad.vaddr(3, 0) 345 lowResultShift := BYTE0 346 lowResultWidth := BYTE2 347 348 highAddrLoad.uop.fuOpType := LH 349 highAddrLoad.vaddr := req.vaddr + 2.U 350 highAddrLoad.mask := 0x3.U << highAddrLoad.vaddr(3, 0) 351 highResultShift := BYTE0 352 highResultWidth := BYTE2 353 } 354 355 is ("b11".U) { 356 lowAddrLoad.uop.fuOpType := LB 357 lowAddrLoad.vaddr := req.vaddr 358 lowAddrLoad.mask := 0x1.U << lowAddrLoad.vaddr(3, 0) 359 lowResultShift := BYTE0 360 lowResultWidth := BYTE1 361 362 highAddrLoad.uop.fuOpType := LW 363 highAddrLoad.vaddr := req.vaddr + 1.U 364 highAddrLoad.mask := 0xf.U << highAddrLoad.vaddr(3, 0) 365 highResultShift := BYTE0 366 highResultWidth := BYTE3 367 } 368 } 369 } 370 371 is (LD) { 372 switch (req.vaddr(2, 0)) { 373 is ("b000".U) { 374 assert(false.B, "should not trigger miss align") 375 } 376 377 is ("b001".U) { 378 lowAddrLoad.uop.fuOpType := LD 379 lowAddrLoad.vaddr := req.vaddr - 1.U 380 lowAddrLoad.mask := 0xff.U << lowAddrLoad.vaddr(3, 0) 381 lowResultShift := BYTE1 382 lowResultWidth := BYTE7 383 384 highAddrLoad.uop.fuOpType := LB 385 highAddrLoad.vaddr := req.vaddr + 7.U 386 highAddrLoad.mask := 0x1.U << highAddrLoad.vaddr(3, 0) 387 highResultShift := BYTE0 388 highResultWidth := BYTE1 389 } 390 391 is ("b010".U) { 392 lowAddrLoad.uop.fuOpType := LD 393 lowAddrLoad.vaddr := req.vaddr - 2.U 394 lowAddrLoad.mask := 0xff.U << lowAddrLoad.vaddr(3, 0) 395 lowResultShift := BYTE2 396 lowResultWidth := BYTE6 397 398 highAddrLoad.uop.fuOpType := LH 399 highAddrLoad.vaddr := req.vaddr + 6.U 400 highAddrLoad.mask := 0x3.U << highAddrLoad.vaddr(3, 0) 401 highResultShift := BYTE0 402 highResultWidth := BYTE2 403 } 404 405 is ("b011".U) { 406 lowAddrLoad.uop.fuOpType := LD 407 lowAddrLoad.vaddr := req.vaddr - 3.U 408 lowAddrLoad.mask := 0xff.U << lowAddrLoad.vaddr(3, 0) 409 lowResultShift := BYTE3 410 lowResultWidth := BYTE5 411 412 highAddrLoad.uop.fuOpType := LW 413 highAddrLoad.vaddr := req.vaddr + 5.U 414 highAddrLoad.mask := 0xf.U << highAddrLoad.vaddr(3, 0) 415 highResultShift := BYTE0 416 highResultWidth := BYTE3 417 } 418 419 is ("b100".U) { 420 lowAddrLoad.uop.fuOpType := LW 421 lowAddrLoad.vaddr := req.vaddr 422 lowAddrLoad.mask := 0xf.U << lowAddrLoad.vaddr(3, 0) 423 lowResultShift := BYTE0 424 lowResultWidth := BYTE4 425 426 highAddrLoad.uop.fuOpType := LW 427 highAddrLoad.vaddr := req.vaddr + 4.U 428 highAddrLoad.mask := 0xf.U << highAddrLoad.vaddr(3, 0) 429 highResultShift := BYTE0 430 highResultWidth := BYTE4 431 } 432 433 is ("b101".U) { 434 lowAddrLoad.uop.fuOpType := LW 435 lowAddrLoad.vaddr := req.vaddr - 1.U 436 lowAddrLoad.mask := 0xf.U << lowAddrLoad.vaddr(3, 0) 437 lowResultShift := BYTE1 438 lowResultWidth := BYTE3 439 440 highAddrLoad.uop.fuOpType := LD 441 highAddrLoad.vaddr := req.vaddr + 3.U 442 highAddrLoad.mask := 0xff.U << highAddrLoad.vaddr(3, 0) 443 highResultShift := BYTE0 444 highResultWidth := BYTE5 445 } 446 447 is ("b110".U) { 448 lowAddrLoad.uop.fuOpType := LH 449 lowAddrLoad.vaddr := req.vaddr 450 lowAddrLoad.mask := 0x3.U << lowAddrLoad.vaddr(3, 0) 451 lowResultShift := BYTE0 452 lowResultWidth := BYTE2 453 454 highAddrLoad.uop.fuOpType := LD 455 highAddrLoad.vaddr := req.vaddr + 2.U 456 highAddrLoad.mask := 0xff.U << highAddrLoad.vaddr(3, 0) 457 highResultShift := BYTE0 458 highResultWidth := BYTE6 459 } 460 461 is ("b111".U) { 462 lowAddrLoad.uop.fuOpType := LB 463 lowAddrLoad.vaddr := req.vaddr 464 lowAddrLoad.mask := 0x1.U << lowAddrLoad.vaddr(3, 0) 465 lowResultShift := BYTE0 466 lowResultWidth := BYTE1 467 468 highAddrLoad.uop.fuOpType := LD 469 highAddrLoad.vaddr := req.vaddr + 1.U 470 highAddrLoad.mask := 0xff.U << highAddrLoad.vaddr(3, 0) 471 highResultShift := BYTE0 472 highResultWidth := BYTE7 473 } 474 } 475 } 476 } 477 478 splitLoadReqs(0) := lowAddrLoad 479 splitLoadReqs(1) := highAddrLoad 480 } 481 exceptionVec := 0.U.asTypeOf(exceptionVec.cloneType) 482 } 483 484 io.splitLoadReq.valid := req_valid && (bufferState === s_req || bufferState === s_comb_wakeup_rep && needWakeUpReqsWire && !req.isvec) 485 io.splitLoadReq.bits := splitLoadReqs(curPtr) 486 io.splitLoadReq.bits.isvec := req.isvec 487 io.splitLoadReq.bits.misalignNeedWakeUp := needWakeUpReqsWire 488 io.splitLoadReq.bits.isFinalSplit := curPtr(0) && !needWakeUpReqsWire 489 // Restore the information of H extension load 490 // bit encoding: | hlv 1 | hlvx 1 | is unsigned(1bit) | size(2bit) | 491 val reqIsHlv = LSUOpType.isHlv(req.uop.fuOpType) 492 val reqIsHlvx = LSUOpType.isHlvx(req.uop.fuOpType) 493 io.splitLoadReq.bits.uop.fuOpType := Mux(req.isvec, req.uop.fuOpType, Cat(reqIsHlv, reqIsHlvx, 0.U(1.W), splitLoadReqs(curPtr).uop.fuOpType(1, 0))) 494 io.splitLoadReq.bits.alignedType := Mux(req.isvec, splitLoadReqs(curPtr).uop.fuOpType(1, 0), req.alignedType) 495 496 when (io.splitLoadResp.valid) { 497 val resp = io.splitLoadResp.bits 498 splitLoadResp(curPtr) := io.splitLoadResp.bits 499 when (isMMIO) { 500 unSentLoads := 0.U 501 exceptionVec := ExceptionNO.selectByFu(0.U.asTypeOf(exceptionVec.cloneType), LduCfg) 502 // delegate to software 503 exceptionVec(loadAddrMisaligned) := true.B 504 } .elsewhen (hasException) { 505 unSentLoads := 0.U 506 LduCfg.exceptionOut.map(no => exceptionVec(no) := exceptionVec(no) || resp.uop.exceptionVec(no)) 507 } .elsewhen (!io.splitLoadResp.bits.rep_info.need_rep) { 508 unSentLoads := unSentLoads & ~UIntToOH(curPtr) 509 curPtr := curPtr + 1.U 510 exceptionVec := 0.U.asTypeOf(ExceptionVec()) 511 } 512 } 513 514 val combinedData = RegInit(0.U(XLEN.W)) 515 516 when (bufferState === s_comb_wakeup_rep) { 517 val lowAddrResult = getShiftAndTruncateData(lowResultShift, lowResultWidth, splitLoadResp(0).data) 518 .asTypeOf(Vec(XLEN / 8, UInt(8.W))) 519 val highAddrResult = getShiftAndTruncateData(highResultShift, highResultWidth, splitLoadResp(1).data) 520 .asTypeOf(Vec(XLEN / 8, UInt(8.W))) 521 val catResult = Wire(Vec(XLEN / 8, UInt(8.W))) 522 (0 until XLEN / 8) .map { 523 case i => { 524 when (i.U < lowResultWidth) { 525 catResult(i) := lowAddrResult(i) 526 } .otherwise { 527 catResult(i) := highAddrResult(i.U - lowResultWidth) 528 } 529 } 530 } 531 combinedData := Mux(req.isvec, rdataVecHelper(req.alignedType, (catResult.asUInt)(XLEN - 1, 0)), rdataHelper(req.uop, (catResult.asUInt)(XLEN - 1, 0))) 532 533 } 534 535 io.writeBack.valid := req_valid && (bufferState === s_wb) && (io.splitLoadResp.valid && io.splitLoadResp.bits.misalignNeedWakeUp || globalMMIO || globalException) && !io.loadOutValid && !req.isvec 536 io.writeBack.bits.uop := req.uop 537 io.writeBack.bits.uop.exceptionVec := DontCare 538 LduCfg.exceptionOut.map(no => io.writeBack.bits.uop.exceptionVec(no) := (globalMMIO || globalException) && exceptionVec(no)) 539 io.writeBack.bits.uop.rfWen := !globalException && !globalMMIO && req.uop.rfWen 540 io.writeBack.bits.uop.fuType := FuType.ldu.U 541 io.writeBack.bits.uop.flushPipe := false.B 542 io.writeBack.bits.uop.replayInst := false.B 543 io.writeBack.bits.data := newRdataHelper(data_select, combinedData) 544 io.writeBack.bits.isFromLoadUnit := needWakeUpWB 545 io.writeBack.bits.debug.isMMIO := globalMMIO 546 // FIXME lyq: temporarily set to false 547 io.writeBack.bits.debug.isNC := false.B 548 io.writeBack.bits.debug.isPerfCnt := false.B 549 io.writeBack.bits.debug.paddr := req.paddr 550 io.writeBack.bits.debug.vaddr := req.vaddr 551 552 553 // vector output 554 io.vecWriteBack.valid := req_valid && (bufferState === s_wb) && !io.loadVecOutValid && req.isvec 555 556 io.vecWriteBack.bits.alignedType := req.alignedType 557 io.vecWriteBack.bits.vecFeedback := true.B 558 io.vecWriteBack.bits.vecdata.get := combinedData 559 io.vecWriteBack.bits.isvec := req.isvec 560 io.vecWriteBack.bits.elemIdx := req.elemIdx 561 io.vecWriteBack.bits.elemIdxInsideVd.get := req.elemIdxInsideVd 562 io.vecWriteBack.bits.mask := req.mask 563 io.vecWriteBack.bits.reg_offset.get := 0.U 564 io.vecWriteBack.bits.usSecondInv := req.usSecondInv 565 io.vecWriteBack.bits.mBIndex := req.mbIndex 566 io.vecWriteBack.bits.hit := true.B 567 io.vecWriteBack.bits.sourceType := RSFeedbackType.lrqFull 568 io.vecWriteBack.bits.trigger := TriggerAction.None 569 io.vecWriteBack.bits.flushState := DontCare 570 io.vecWriteBack.bits.exceptionVec := ExceptionNO.selectByFu(exceptionVec, VlduCfg) 571 io.vecWriteBack.bits.vaddr := req.fullva 572 io.vecWriteBack.bits.vaNeedExt := req.vaNeedExt 573 io.vecWriteBack.bits.gpaddr := req.gpaddr 574 io.vecWriteBack.bits.isForVSnonLeafPTE := req.isForVSnonLeafPTE 575 io.vecWriteBack.bits.mmio := DontCare 576 io.vecWriteBack.bits.vstart := req.uop.vpu.vstart 577 io.vecWriteBack.bits.vecTriggerMask := req.vecTriggerMask 578 io.vecWriteBack.bits.nc := false.B 579 580 581 val flush = req_valid && req.uop.robIdx.needFlush(io.redirect) 582 583 when (flush) { 584 bufferState := s_idle 585 req_valid := false.B 586 curPtr := 0.U 587 unSentLoads := 0.U 588 globalException := false.B 589 globalMMIO := false.B 590 } 591 592 // NOTE: spectial case (unaligned load cross page, page fault happens in next page) 593 // if exception happens in the higher page address part, overwrite the loadExceptionBuffer vaddr 594 val shouldOverwrite = req_valid && globalException 595 val overwriteExpBuf = GatedValidRegNext(shouldOverwrite) 596 val overwriteVaddr = RegEnable( 597 Mux( 598 cross16BytesBoundary && (curPtr === 1.U), 599 splitLoadResp(curPtr).vaddr, 600 splitLoadResp(curPtr).fullva), 601 shouldOverwrite) 602 val overwriteGpaddr = RegEnable(splitLoadResp(curPtr).gpaddr, shouldOverwrite) 603 val overwriteIsHyper = RegEnable(splitLoadResp(curPtr).isHyper, shouldOverwrite) 604 val overwriteIsForVSnonLeafPTE = RegEnable(splitLoadResp(curPtr).isForVSnonLeafPTE, shouldOverwrite) 605 606 //TODO In theory, there is no need to overwrite, but for now, the signal is retained in the code in this way. 607 // and the signal will be removed after sufficient verification. 608 io.overwriteExpBuf.valid := false.B 609 io.overwriteExpBuf.vaddr := overwriteVaddr 610 io.overwriteExpBuf.isHyper := overwriteIsHyper 611 io.overwriteExpBuf.gpaddr := overwriteGpaddr 612 io.overwriteExpBuf.isForVSnonLeafPTE := overwriteIsForVSnonLeafPTE 613 614 // when no exception or mmio, flush loadExceptionBuffer at s_wb 615 val flushLdExpBuff = GatedValidRegNext(req_valid && (bufferState === s_wb) && !(globalMMIO || globalException)) 616 io.flushLdExpBuff := flushLdExpBuff 617 618 XSPerfAccumulate("alloc", RegNext(!req_valid) && req_valid) 619 XSPerfAccumulate("flush", flush) 620 XSPerfAccumulate("flush_idle", flush && (bufferState === s_idle)) 621 XSPerfAccumulate("flush_non_idle", flush && (bufferState =/= s_idle)) 622}