fix(LSU): fix exception for misalign access to `nc` space (#4526)

For misaligned accesses, say if the access after the split goes to `nc`
space, then a misaligned exception should also be generated.

fix(LSU): fix exception for misalign access to `nc` space (#4526)

For misaligned accesses, say if the access after the split goes to `nc`
space, then a misaligned exception should also be generated.

Co-authored-by: Yanqin Li <[email protected]>

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timing(StoreMisalignBuffer): fix misalign buffer enq timing (#4493)

* a misalign store will enqueue misalign buffer at s1, and revoke if it
needs at s2

style(Bundles): move bundles to Bundles.scala (#4247)

fix(VLSU): fix vector exception writeback to 'MergeBuffer' logic (#4137)

Fixed the bug of abnormal signal loss when writing back.

Previously, we expected to compare only the ports of the writebacks

fix(VLSU): fix vector exception writeback to 'MergeBuffer' logic (#4137)

Fixed the bug of abnormal signal loss when writing back.

Previously, we expected to compare only the ports of the writebacks that
triggered the exception and pick the oldest.

But amazingly, I just realised that the implementation doesn't match the
annotation. The current implementation can be problematic in that if
the write-back port that did not have an exception is older, the port that
triggered the exception is not elected.

Use s3_exception to try to optimise timing.

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fix(LSU): `rfwen` not be set when `WakeUp` cancelled or not need `WakeUp`

feat(Zicclsm): refactoring misalign and support vector misalign

fix(NC): fix a list of bugs of NC WMO access

* fix(PBMT): skip nc difftest and handle the conflict of nc and normal store

* fix(PBMT): nc st req is changed to a state machine execution

* fix(pbmt)

fix(NC): fix a list of bugs of NC WMO access

* fix(PBMT): skip nc difftest and handle the conflict of nc and normal store

* fix(PBMT): nc st req is changed to a state machine execution

* fix(pbmt): fix typo and control error of nc ld

* fix(pbmt): nc data assignment error

* fix(pbmt): nc should be used to wakeup

* fix(pbmt): remove wrong assert

* fix(pbmt): lots of bugs of nc st ld forward

* fix(pbmt): fix address align error

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area(MemBlock): remove redundant signals to optimise area (#3560)

optimise redundant signals to reduce MemBlock area.
1. optimise 'exceptionVec', selected by LduCfg or StaCfg;
2. optimise 'fuType'

area(MemBlock): remove redundant signals to optimise area (#3560)

optimise redundant signals to reduce MemBlock area.
1. optimise 'exceptionVec', selected by LduCfg or StaCfg;
2. optimise 'fuType', reassign the value when writeback Rob in pipeline,
so no longer saved in LSQ.
3. optimise 'uop.imm', vaddr is computed in StoreMisalignBuffer and
there is no need to store the uop.imm.

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timing(MemBlock): adjust load unit writeback ports

fix(misalign): fix gpaddr of misalign loads when onlyStage2 (#3822)

For onlyStage2 situations, gpaddr is equal to vaddr. Therefore, for
cross-page requests, we need to pass gpaddr out correctly (se

fix(misalign): fix gpaddr of misalign loads when onlyStage2 (#3822)

For onlyStage2 situations, gpaddr is equal to vaddr. Therefore, for
cross-page requests, we need to pass gpaddr out correctly (see comments)
Also, in previous design, we would set gpaddr offset to all zero when
cross-page in loadmisalign buffer. This has been removed and all gpaddrs
are generated in tlb.

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fix(misalign): Should use offset of original vaddr to generate gpaddr

For example, a `ld` instruction on address 0x81000ffb will be splited into two loads:
1. ld 0x81000ff8. vaddr = 0x81000ff8, full

fix(misalign): Should use offset of original vaddr to generate gpaddr

For example, a `ld` instruction on address 0x81000ffb will be splited into two loads:
1. ld 0x81000ff8. vaddr = 0x81000ff8, fullva = 0x80000ffb
2. ld 0x81001000. vaddr = 0x81001000, fullva = 0x80000ffb

When load 1 trigger a guest page fault, we should use offset of original vaddr to generate gpaddr in TLB, and and when load 2 trigger a guest page fault, we should just use offset of after-splitted vaddr(all zero) in misalignbuffer.

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fix(MisalignBuffer): Use RegEnable in datapath to avoid xprop

We should not use GatedRegNext here as `overwrite*` may be X-state when `shouldOverwrite` is false.

area(MemBlock): remove redundant signals to optimize area (#3777)

fix(misalign): fix misaligned HLV and HLVX (#3759)

In the previous design, the H extension information was lost in the
`fuOpType` of the misalignBuffer split instruction, causing the split
instruc

fix(misalign): fix misaligned HLV and HLVX (#3759)

In the previous design, the H extension information was lost in the
`fuOpType` of the misalignBuffer split instruction, causing the split
instruction to not perform two-stage address translation and cause
errors.

This PR fixes the information about H extension in `fuOpType` in
misalignBuffer.

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fix(misalign): fix wrong gpa in misalignBuffer (#3739)

Since misaligned memory access will be separated into aligned memory
access, the actual address of the memory access might be different from

fix(misalign): fix wrong gpa in misalignBuffer (#3739)

Since misaligned memory access will be separated into aligned memory
access, the actual address of the memory access might be different from
the original address.

If a gpa exception occurs, the exception address should be recovered
from the original address using original page offset.

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fix(Backend, Mem): add `isFromLoadUnit` to avoid other units polluting RegCache (#3731)

fix(LoadMisalignBuffer): all exception from misalignbuffer should overwrite (#3699)

In our previous design, we would only overwrite from misalignbuffer for
cross-page requests; misalign requests th

fix(LoadMisalignBuffer): all exception from misalignbuffer should overwrite (#3699)

In our previous design, we would only overwrite from misalignbuffer for
cross-page requests; misalign requests that don't cross pages would
still be written back from exceptionbuffer. However, exception messages
such as gpaddr, which require a TLB hit to return, need to be written
back from the misalignbuffer instead.

This commit writes back all exceptions of misalign requests from the
misalignbuffer.

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fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retain

fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retained. And for exceptions detected after address translation, the
48-bit vaddr needs to be zero-extended or sign-extended according to
different modes(`GenExceptionVa`), and then write to *tval.

Also fix some connection bugs.

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feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault t

feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault traps that meet
both of the following conditions:
- the trap is caused by a G-stage translation which supports VS-stage
translation
- a nonzero value is written to mtval2/htval

"isForVSnonLeafPTE" is used only in exceptional circumstances that gpf
happens in the G-stage translation which supports VS-stage translation,
such as searching the non-leaf pte of VS-stage.

This patch adds support for writing proper value to mtinst/htinst when
specific trap occurs. And bump the nemu.

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fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exc

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exceptions in such cases.

Commit
https://github.com/OpenXiangShan/XiangShan/commit/c1b28b66879239a5b3a44741376f3b002e8ac834
has already fixed high address bits checking of jump target. This commit
fixes lsu part, checking full address in tlb and passing full address
directly to csr.

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fix(exception): Add guest page fault logic of misalign and vlsu (#3537)

In our previous design, we did not consider the handling of gpf of
unaligned & vector load and stores. This commit adds a fix

fix(exception): Add guest page fault logic of misalign and vlsu (#3537)

In our previous design, we did not consider the handling of gpf of
unaligned & vector load and stores. This commit adds a fix to correctly
return the guest paddr when gpf happens in the above instructions.

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fix(Zicclsm, trigger): fix the problem of missing breakpoint exception (#3470)

+ @wissygh Refactored Trigger check code of Memblock.
+ Move Trigger address cmp from load S3 to S1. In addition, the

fix(Zicclsm, trigger): fix the problem of missing breakpoint exception (#3470)

+ @wissygh Refactored Trigger check code of Memblock.
+ Move Trigger address cmp from load S3 to S1. In addition, the
detection of trigger is moved from Memblock to LoadUnit.
- Once the breakpoint exception is detected, enter the exception Buffer
directly to handle the exception (previously, the
load instruction was executed first and then the exception was handled,
which would cause the mmio load to change the
status of the peripheral).
+ If Trigger address matches and the action is to enter debug mode, both
loadUnit and storeUnit will directly write this instruction back without
any execution (by setting this instruction as an exception).
+ Match trigger addresses for vector instructions in LoadUnit.
+ If both a misalign exception and a breakpoint occur, the breakpoint
exception will be processed first.

---------

Co-authored-by: chengguanghui <[email protected]>

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RVA23: Support Zicclsm & Zama16b (Handling Unaligned Load Store by Hardware) (#3320)

This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches

--

RVA23: Support Zicclsm & Zama16b (Handling Unaligned Load Store by Hardware) (#3320)

This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches

---------

Co-authored-by: xiaofeibao <[email protected]>

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