1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.fu.FuConfig._ 26import xiangshan.backend.fu.fpu.FPU 27import xiangshan.backend.rob.RobLsqIO 28import xiangshan.cache._ 29import xiangshan.frontend.FtqPtr 30import xiangshan.ExceptionNO._ 31import xiangshan.cache.wpu.ReplayCarry 32import xiangshan.backend.rob.RobPtr 33import xiangshan.backend.Bundles.{MemExuOutput, DynInst} 34 35class LoadMisalignBuffer(implicit p: Parameters) extends XSModule 36 with HasCircularQueuePtrHelper 37 with HasLoadHelper 38{ 39 private val enqPortNum = LoadPipelineWidth 40 private val maxSplitNum = 2 41 42 require(maxSplitNum == 2) 43 44 private val LB = "b00".U(2.W) 45 private val LH = "b01".U(2.W) 46 private val LW = "b10".U(2.W) 47 private val LD = "b11".U(2.W) 48 49 // encode of how many bytes to shift or truncate 50 private val BYTE0 = "b000".U(3.W) 51 private val BYTE1 = "b001".U(3.W) 52 private val BYTE2 = "b010".U(3.W) 53 private val BYTE3 = "b011".U(3.W) 54 private val BYTE4 = "b100".U(3.W) 55 private val BYTE5 = "b101".U(3.W) 56 private val BYTE6 = "b110".U(3.W) 57 private val BYTE7 = "b111".U(3.W) 58 59 def getMask(sizeEncode: UInt) = LookupTree(sizeEncode, List( 60 LB -> 0x1.U, // lb 61 LH -> 0x3.U, // lh 62 LW -> 0xf.U, // lw 63 LD -> 0xff.U // ld 64 )) 65 66 def getShiftAndTruncateData(shiftEncode: UInt, truncateEncode: UInt, data: UInt) = { 67 val shiftData = LookupTree(shiftEncode, List( 68 BYTE0 -> data(63, 0), 69 BYTE1 -> data(63, 8), 70 BYTE2 -> data(63, 16), 71 BYTE3 -> data(63, 24), 72 BYTE4 -> data(63, 32), 73 BYTE5 -> data(63, 40), 74 BYTE6 -> data(63, 48), 75 BYTE7 -> data(63, 56) 76 )) 77 val truncateData = LookupTree(truncateEncode, List( 78 BYTE0 -> 0.U(XLEN.W), // can not truncate with 0 byte width 79 BYTE1 -> shiftData(7, 0), 80 BYTE2 -> shiftData(15, 0), 81 BYTE3 -> shiftData(23, 0), 82 BYTE4 -> shiftData(31, 0), 83 BYTE5 -> shiftData(39, 0), 84 BYTE6 -> shiftData(47, 0), 85 BYTE7 -> shiftData(55, 0) 86 )) 87 truncateData(XLEN - 1, 0) 88 } 89 90 def selectOldest[T <: LqWriteBundle](valid: Seq[Bool], bits: Seq[T]): (Seq[Bool], Seq[T]) = { 91 assert(valid.length == bits.length) 92 if (valid.length == 0 || valid.length == 1) { 93 (valid, bits) 94 } else if (valid.length == 2) { 95 val res = Seq.fill(2)(Wire(ValidIO(chiselTypeOf(bits(0))))) 96 for (i <- res.indices) { 97 res(i).valid := valid(i) 98 res(i).bits := bits(i) 99 } 100 val oldest = Mux(valid(0) && valid(1), 101 Mux(isAfter(bits(0).uop.robIdx, bits(1).uop.robIdx) || 102 (isNotBefore(bits(0).uop.robIdx, bits(1).uop.robIdx) && bits(0).uop.uopIdx > bits(1).uop.uopIdx), res(1), res(0)), 103 Mux(valid(0) && !valid(1), res(0), res(1))) 104 (Seq(oldest.valid), Seq(oldest.bits)) 105 } else { 106 val left = selectOldest(valid.take(valid.length / 2), bits.take(bits.length / 2)) 107 val right = selectOldest(valid.takeRight(valid.length - (valid.length / 2)), bits.takeRight(bits.length - (bits.length / 2))) 108 selectOldest(left._1 ++ right._1, left._2 ++ right._2) 109 } 110 } 111 112 val io = IO(new Bundle() { 113 val redirect = Flipped(Valid(new Redirect)) 114 val req = Vec(enqPortNum, Flipped(Valid(new LqWriteBundle))) 115 val rob = Flipped(new RobLsqIO) 116 val splitLoadReq = Decoupled(new LsPipelineBundle) 117 val splitLoadResp = Flipped(Valid(new LqWriteBundle)) 118 val writeBack = Decoupled(new MemExuOutput) 119 val overwriteExpBuf = Output(new XSBundle { 120 val valid = Bool() 121 val vaddr = UInt(XLEN.W) 122 val gpaddr = UInt(XLEN.W) 123 val isForVSnonLeafPTE = Bool() 124 }) 125 val flushLdExpBuff = Output(Bool()) 126 }) 127 128 io.rob.mmio := 0.U.asTypeOf(Vec(LoadPipelineWidth, Bool())) 129 io.rob.uop := 0.U.asTypeOf(Vec(LoadPipelineWidth, new DynInst)) 130 131 val req_valid = RegInit(false.B) 132 val req = Reg(new LqWriteBundle) 133 134 // enqueue 135 // s1: 136 val s1_req = VecInit(io.req.map(_.bits)) 137 val s1_valid = VecInit(io.req.map(x => x.valid)) 138 139 // s2: delay 1 cycle 140 val s2_req = RegNext(s1_req) 141 val s2_valid = (0 until enqPortNum).map(i => 142 RegNext(s1_valid(i)) && 143 !s2_req(i).uop.robIdx.needFlush(RegNext(io.redirect)) && 144 !s2_req(i).uop.robIdx.needFlush(io.redirect) 145 ) 146 val s2_miss_aligned = s2_req.map(x => 147 x.uop.exceptionVec(loadAddrMisaligned) && !x.uop.exceptionVec(breakPoint) && !TriggerAction.isDmode(x.uop.trigger) 148 ) 149 150 val s2_enqueue = Wire(Vec(enqPortNum, Bool())) 151 for (w <- 0 until enqPortNum) { 152 s2_enqueue(w) := s2_valid(w) && s2_miss_aligned(w) 153 } 154 155 when (req_valid && req.uop.robIdx.needFlush(io.redirect)) { 156 req_valid := s2_enqueue.asUInt.orR 157 } .elsewhen (s2_enqueue.asUInt.orR) { 158 req_valid := req_valid || true.B 159 } 160 161 val reqSel = selectOldest(s2_enqueue, s2_req) 162 163 when (req_valid) { 164 req := Mux( 165 reqSel._1(0) && (isAfter(req.uop.robIdx, reqSel._2(0).uop.robIdx) || (isNotBefore(req.uop.robIdx, reqSel._2(0).uop.robIdx) && req.uop.uopIdx > reqSel._2(0).uop.uopIdx)), 166 reqSel._2(0), 167 req) 168 } .elsewhen (s2_enqueue.asUInt.orR) { 169 req := reqSel._2(0) 170 } 171 172 val robMatch = req_valid && io.rob.pendingld && (io.rob.pendingPtr === req.uop.robIdx) 173 174 // buffer control: 175 // - split miss-aligned load into aligned loads 176 // - send split load to ldu and get result from ldu 177 // - merge them and write back to rob 178 val s_idle :: s_split :: s_req :: s_resp :: s_comb :: s_wb :: s_wait :: Nil = Enum(7) 179 val bufferState = RegInit(s_idle) 180 val splitLoadReqs = RegInit(VecInit(List.fill(maxSplitNum)(0.U.asTypeOf(new LsPipelineBundle)))) 181 val splitLoadResp = RegInit(VecInit(List.fill(maxSplitNum)(0.U.asTypeOf(new LqWriteBundle)))) 182 val unSentLoads = RegInit(0.U(maxSplitNum.W)) 183 val curPtr = RegInit(0.U(log2Ceil(maxSplitNum).W)) 184 185 // if there is exception or mmio in split load 186 val globalException = RegInit(false.B) 187 val globalMMIO = RegInit(false.B) 188 189 val hasException = ExceptionNO.selectByFu(io.splitLoadResp.bits.uop.exceptionVec, LduCfg).asUInt.orR 190 val isMMIO = io.splitLoadResp.bits.mmio 191 192 switch(bufferState) { 193 is (s_idle) { 194 when (robMatch) { 195 bufferState := s_split 196 } 197 } 198 199 is (s_split) { 200 bufferState := s_req 201 } 202 203 is (s_req) { 204 when (io.splitLoadReq.fire) { 205 bufferState := s_resp 206 } 207 } 208 209 is (s_resp) { 210 when (io.splitLoadResp.valid) { 211 val clearOh = UIntToOH(curPtr) 212 when (hasException || isMMIO) { 213 // commit directly when exception ocurs 214 // if any split load reaches mmio space, delegate to software loadAddrMisaligned exception 215 bufferState := s_wb 216 globalException := hasException 217 globalMMIO := isMMIO 218 } .elsewhen(io.splitLoadResp.bits.rep_info.need_rep || (unSentLoads & ~clearOh).orR) { 219 // need replay or still has unsent requests 220 bufferState := s_req 221 } .otherwise { 222 // merge the split load results 223 bufferState := s_comb 224 } 225 } 226 } 227 228 is (s_comb) { 229 bufferState := s_wb 230 } 231 232 is (s_wb) { 233 when(io.writeBack.fire) { 234 bufferState := s_wait 235 } 236 } 237 238 is (s_wait) { 239 when(io.rob.lcommit =/= 0.U || req.uop.robIdx.needFlush(io.redirect)) { 240 // rob commits the unaligned load or handled the exception, reset all state 241 bufferState := s_idle 242 req_valid := false.B 243 curPtr := 0.U 244 unSentLoads := 0.U 245 globalException := false.B 246 globalMMIO := false.B 247 } 248 } 249 } 250 251 val highAddress = LookupTree(req.uop.fuOpType(1, 0), List( 252 LB -> 0.U, 253 LH -> 1.U, 254 LW -> 3.U, 255 LD -> 7.U 256 )) + req.vaddr(4, 0) 257 // to see if (vaddr + opSize - 1) and vaddr are in the same 16 bytes region 258 val cross16BytesBoundary = req_valid && (highAddress(4) =/= req.vaddr(4)) 259 val aligned16BytesAddr = (req.vaddr >> 4) << 4// req.vaddr & ~("b1111".U) 260 val aligned16BytesSel = req.vaddr(3, 0) 261 262 // meta of 128 bit load 263 val new128Load = WireInit(0.U.asTypeOf(new LsPipelineBundle)) 264 // meta of split loads 265 val lowAddrLoad = WireInit(0.U.asTypeOf(new LsPipelineBundle)) 266 val highAddrLoad = WireInit(0.U.asTypeOf(new LsPipelineBundle)) 267 val lowResultShift = RegInit(0.U(3.W)) // how many bytes should we shift right when got result 268 val lowResultWidth = RegInit(0.U(3.W)) // how many bytes should we take from result 269 val highResultShift = RegInit(0.U(3.W)) 270 val highResultWidth = RegInit(0.U(3.W)) 271 272 when (bufferState === s_split) { 273 when (!cross16BytesBoundary) { 274 // change this unaligned load into a 128 bits load 275 unSentLoads := 1.U 276 curPtr := 0.U 277 new128Load.vaddr := aligned16BytesAddr 278 // new128Load.mask := (getMask(req.uop.fuOpType(1, 0)) << aligned16BytesSel).asUInt 279 new128Load.mask := 0xffff.U 280 new128Load.uop := req.uop 281 new128Load.uop.exceptionVec(loadAddrMisaligned) := false.B 282 new128Load.is128bit := true.B 283 splitLoadReqs(0) := new128Load 284 } .otherwise { 285 // split this unaligned load into `maxSplitNum` aligned loads 286 unSentLoads := Fill(maxSplitNum, 1.U(1.W)) 287 curPtr := 0.U 288 lowAddrLoad.uop := req.uop 289 lowAddrLoad.uop.exceptionVec(loadAddrMisaligned) := false.B 290 highAddrLoad.uop := req.uop 291 highAddrLoad.uop.exceptionVec(loadAddrMisaligned) := false.B 292 293 switch (req.uop.fuOpType(1, 0)) { 294 is (LB) { 295 assert(false.B, "lb should not trigger miss align") 296 } 297 298 is (LH) { 299 lowAddrLoad.uop.fuOpType := LB 300 lowAddrLoad.vaddr := req.vaddr 301 lowAddrLoad.mask := 0x1.U << lowAddrLoad.vaddr(3, 0) 302 lowResultShift := BYTE0 303 lowResultWidth := BYTE1 304 305 highAddrLoad.uop.fuOpType := LB 306 highAddrLoad.vaddr := req.vaddr + 1.U 307 highAddrLoad.mask := 0x1.U << highAddrLoad.vaddr(3, 0) 308 highResultShift := BYTE0 309 highResultWidth := BYTE1 310 } 311 312 is (LW) { 313 switch (req.vaddr(1, 0)) { 314 is ("b00".U) { 315 assert(false.B, "should not trigger miss align") 316 } 317 318 is ("b01".U) { 319 lowAddrLoad.uop.fuOpType := LW 320 lowAddrLoad.vaddr := req.vaddr - 1.U 321 lowAddrLoad.mask := 0xf.U << lowAddrLoad.vaddr(3, 0) 322 lowResultShift := BYTE1 323 lowResultWidth := BYTE3 324 325 highAddrLoad.uop.fuOpType := LB 326 highAddrLoad.vaddr := req.vaddr + 3.U 327 highAddrLoad.mask := 0x1.U << highAddrLoad.vaddr(3, 0) 328 highResultShift := BYTE0 329 highResultWidth := BYTE1 330 } 331 332 is ("b10".U) { 333 lowAddrLoad.uop.fuOpType := LH 334 lowAddrLoad.vaddr := req.vaddr 335 lowAddrLoad.mask := 0x3.U << lowAddrLoad.vaddr(3, 0) 336 lowResultShift := BYTE0 337 lowResultWidth := BYTE2 338 339 highAddrLoad.uop.fuOpType := LH 340 highAddrLoad.vaddr := req.vaddr + 2.U 341 highAddrLoad.mask := 0x3.U << highAddrLoad.vaddr(3, 0) 342 highResultShift := BYTE0 343 highResultWidth := BYTE2 344 } 345 346 is ("b11".U) { 347 lowAddrLoad.uop.fuOpType := LB 348 lowAddrLoad.vaddr := req.vaddr 349 lowAddrLoad.mask := 0x1.U << lowAddrLoad.vaddr(3, 0) 350 lowResultShift := BYTE0 351 lowResultWidth := BYTE1 352 353 highAddrLoad.uop.fuOpType := LW 354 highAddrLoad.vaddr := req.vaddr + 1.U 355 highAddrLoad.mask := 0xf.U << highAddrLoad.vaddr(3, 0) 356 highResultShift := BYTE0 357 highResultWidth := BYTE3 358 } 359 } 360 } 361 362 is (LD) { 363 switch (req.vaddr(2, 0)) { 364 is ("b000".U) { 365 assert(false.B, "should not trigger miss align") 366 } 367 368 is ("b001".U) { 369 lowAddrLoad.uop.fuOpType := LD 370 lowAddrLoad.vaddr := req.vaddr - 1.U 371 lowAddrLoad.mask := 0xff.U << lowAddrLoad.vaddr(3, 0) 372 lowResultShift := BYTE1 373 lowResultWidth := BYTE7 374 375 highAddrLoad.uop.fuOpType := LB 376 highAddrLoad.vaddr := req.vaddr + 7.U 377 highAddrLoad.mask := 0x1.U << highAddrLoad.vaddr(3, 0) 378 highResultShift := BYTE0 379 highResultWidth := BYTE1 380 } 381 382 is ("b010".U) { 383 lowAddrLoad.uop.fuOpType := LD 384 lowAddrLoad.vaddr := req.vaddr - 2.U 385 lowAddrLoad.mask := 0xff.U << lowAddrLoad.vaddr(3, 0) 386 lowResultShift := BYTE2 387 lowResultWidth := BYTE6 388 389 highAddrLoad.uop.fuOpType := LH 390 highAddrLoad.vaddr := req.vaddr + 6.U 391 highAddrLoad.mask := 0x3.U << highAddrLoad.vaddr(3, 0) 392 highResultShift := BYTE0 393 highResultWidth := BYTE2 394 } 395 396 is ("b011".U) { 397 lowAddrLoad.uop.fuOpType := LD 398 lowAddrLoad.vaddr := req.vaddr - 3.U 399 lowAddrLoad.mask := 0xff.U << lowAddrLoad.vaddr(3, 0) 400 lowResultShift := BYTE3 401 lowResultWidth := BYTE5 402 403 highAddrLoad.uop.fuOpType := LW 404 highAddrLoad.vaddr := req.vaddr + 5.U 405 highAddrLoad.mask := 0xf.U << highAddrLoad.vaddr(3, 0) 406 highResultShift := BYTE0 407 highResultWidth := BYTE3 408 } 409 410 is ("b100".U) { 411 lowAddrLoad.uop.fuOpType := LW 412 lowAddrLoad.vaddr := req.vaddr 413 lowAddrLoad.mask := 0xf.U << lowAddrLoad.vaddr(3, 0) 414 lowResultShift := BYTE0 415 lowResultWidth := BYTE4 416 417 highAddrLoad.uop.fuOpType := LW 418 highAddrLoad.vaddr := req.vaddr + 4.U 419 highAddrLoad.mask := 0xf.U << highAddrLoad.vaddr(3, 0) 420 highResultShift := BYTE0 421 highResultWidth := BYTE4 422 } 423 424 is ("b101".U) { 425 lowAddrLoad.uop.fuOpType := LW 426 lowAddrLoad.vaddr := req.vaddr - 1.U 427 lowAddrLoad.mask := 0xf.U << lowAddrLoad.vaddr(3, 0) 428 lowResultShift := BYTE1 429 lowResultWidth := BYTE3 430 431 highAddrLoad.uop.fuOpType := LD 432 highAddrLoad.vaddr := req.vaddr + 3.U 433 highAddrLoad.mask := 0xff.U << highAddrLoad.vaddr(3, 0) 434 highResultShift := BYTE0 435 highResultWidth := BYTE5 436 } 437 438 is ("b110".U) { 439 lowAddrLoad.uop.fuOpType := LH 440 lowAddrLoad.vaddr := req.vaddr 441 lowAddrLoad.mask := 0x3.U << lowAddrLoad.vaddr(3, 0) 442 lowResultShift := BYTE0 443 lowResultWidth := BYTE2 444 445 highAddrLoad.uop.fuOpType := LD 446 highAddrLoad.vaddr := req.vaddr + 2.U 447 highAddrLoad.mask := 0xff.U << highAddrLoad.vaddr(3, 0) 448 highResultShift := BYTE0 449 highResultWidth := BYTE6 450 } 451 452 is ("b111".U) { 453 lowAddrLoad.uop.fuOpType := LB 454 lowAddrLoad.vaddr := req.vaddr 455 lowAddrLoad.mask := 0x1.U << lowAddrLoad.vaddr(3, 0) 456 lowResultShift := BYTE0 457 lowResultWidth := BYTE1 458 459 highAddrLoad.uop.fuOpType := LD 460 highAddrLoad.vaddr := req.vaddr + 1.U 461 highAddrLoad.mask := 0xff.U << highAddrLoad.vaddr(3, 0) 462 highResultShift := BYTE0 463 highResultWidth := BYTE7 464 } 465 } 466 } 467 } 468 469 splitLoadReqs(0) := lowAddrLoad 470 splitLoadReqs(1) := highAddrLoad 471 } 472 } 473 474 io.splitLoadReq.valid := req_valid && (bufferState === s_req) 475 io.splitLoadReq.bits := splitLoadReqs(curPtr) 476 477 when (io.splitLoadResp.valid) { 478 splitLoadResp(curPtr) := io.splitLoadResp.bits 479 when (isMMIO) { 480 unSentLoads := 0.U 481 splitLoadResp(curPtr).uop.exceptionVec := 0.U.asTypeOf(ExceptionVec()) 482 // delegate to software 483 splitLoadResp(curPtr).uop.exceptionVec(loadAddrMisaligned) := true.B 484 } .elsewhen (hasException) { 485 unSentLoads := 0.U 486 } .elsewhen (!io.splitLoadResp.bits.rep_info.need_rep) { 487 unSentLoads := unSentLoads & ~UIntToOH(curPtr) 488 curPtr := curPtr + 1.U 489 } 490 } 491 492 val combinedData = RegInit(0.U(XLEN.W)) 493 494 when (bufferState === s_comb) { 495 when (!cross16BytesBoundary) { 496 val shiftData = LookupTree(aligned16BytesSel, List( 497 "b0000".U -> splitLoadResp(0).data(63, 0), 498 "b0001".U -> splitLoadResp(0).data(71, 8), 499 "b0010".U -> splitLoadResp(0).data(79, 16), 500 "b0011".U -> splitLoadResp(0).data(87, 24), 501 "b0100".U -> splitLoadResp(0).data(95, 32), 502 "b0101".U -> splitLoadResp(0).data(103, 40), 503 "b0110".U -> splitLoadResp(0).data(111, 48), 504 "b0111".U -> splitLoadResp(0).data(119, 56), 505 "b1000".U -> splitLoadResp(0).data(127, 64), 506 "b1001".U -> splitLoadResp(0).data(127, 72), 507 "b1010".U -> splitLoadResp(0).data(127, 80), 508 "b1011".U -> splitLoadResp(0).data(127, 88), 509 "b1100".U -> splitLoadResp(0).data(127, 96), 510 "b1101".U -> splitLoadResp(0).data(127, 104), 511 "b1110".U -> splitLoadResp(0).data(127, 112), 512 "b1111".U -> splitLoadResp(0).data(127, 120) 513 )) 514 val truncateData = LookupTree(req.uop.fuOpType(1, 0), List( 515 LB -> shiftData(7, 0), // lb 516 LH -> shiftData(15, 0), // lh 517 LW -> shiftData(31, 0), // lw 518 LD -> shiftData(63, 0) // ld 519 )) 520 combinedData := rdataHelper(req.uop, truncateData(XLEN - 1, 0)) 521 } .otherwise { 522 val lowAddrResult = getShiftAndTruncateData(lowResultShift, lowResultWidth, splitLoadResp(0).data) 523 .asTypeOf(Vec(XLEN / 8, UInt(8.W))) 524 val highAddrResult = getShiftAndTruncateData(highResultShift, highResultWidth, splitLoadResp(1).data) 525 .asTypeOf(Vec(XLEN / 8, UInt(8.W))) 526 val catResult = Wire(Vec(XLEN / 8, UInt(8.W))) 527 (0 until XLEN / 8) .map { 528 case i => { 529 when (i.U < lowResultWidth) { 530 catResult(i) := lowAddrResult(i) 531 } .otherwise { 532 catResult(i) := highAddrResult(i.U - lowResultWidth) 533 } 534 } 535 } 536 combinedData := rdataHelper(req.uop, (catResult.asUInt)(XLEN - 1, 0)) 537 } 538 } 539 540 io.writeBack.valid := req_valid && (bufferState === s_wb) 541 io.writeBack.bits.uop := req.uop 542 io.writeBack.bits.uop.exceptionVec := Mux( 543 globalMMIO || globalException, 544 splitLoadResp(curPtr).uop.exceptionVec, 545 0.U.asTypeOf(ExceptionVec()) // TODO: is this ok? 546 ) 547 io.writeBack.bits.uop.flushPipe := Mux(globalMMIO || globalException, false.B, true.B) 548 io.writeBack.bits.uop.replayInst := false.B 549 io.writeBack.bits.data := combinedData 550 io.writeBack.bits.debug.isMMIO := globalMMIO 551 io.writeBack.bits.debug.isPerfCnt := false.B 552 io.writeBack.bits.debug.paddr := req.paddr 553 io.writeBack.bits.debug.vaddr := req.vaddr 554 555 val flush = req_valid && req.uop.robIdx.needFlush(io.redirect) 556 557 when (flush && (bufferState =/= s_idle)) { 558 bufferState := s_idle 559 req_valid := false.B 560 curPtr := 0.U 561 unSentLoads := 0.U 562 globalException := false.B 563 globalMMIO := false.B 564 } 565 566 // NOTE: spectial case (unaligned load cross page, page fault happens in next page) 567 // if exception happens in the higher page address part, overwrite the loadExceptionBuffer vaddr 568 val overwriteExpBuf = GatedValidRegNext(req_valid && cross16BytesBoundary && globalException && (curPtr === 1.U)) 569 val overwriteVaddr = GatedRegNext(splitLoadResp(curPtr).vaddr) 570 val overwriteGpaddr = GatedRegNext(splitLoadResp(curPtr).gpaddr) 571 val overwriteIsForVSnonLeafPTE = GatedRegNext(splitLoadResp(curPtr).isForVSnonLeafPTE) 572 573 io.overwriteExpBuf.valid := overwriteExpBuf 574 io.overwriteExpBuf.vaddr := overwriteVaddr 575 io.overwriteExpBuf.gpaddr := overwriteGpaddr 576 io.overwriteExpBuf.isForVSnonLeafPTE := overwriteIsForVSnonLeafPTE 577 578 // when no exception or mmio, flush loadExceptionBuffer at s_wb 579 val flushLdExpBuff = GatedValidRegNext(req_valid && (bufferState === s_wb) && !(globalMMIO || globalException)) 580 io.flushLdExpBuff := flushLdExpBuff 581 582 XSPerfAccumulate("alloc", RegNext(!req_valid) && req_valid) 583 XSPerfAccumulate("flush", flush) 584 XSPerfAccumulate("flush_idle", flush && (bufferState === s_idle)) 585 XSPerfAccumulate("flush_non_idle", flush && (bufferState =/= s_idle)) 586}