1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.ExceptionNO._ 26import xiangshan.frontend.FtqPtr 27import xiangshan.backend.fu.FuConfig._ 28import xiangshan.backend.fu.FuType 29import xiangshan.backend.fu.fpu.FPU 30import xiangshan.backend.rob.RobLsqIO 31import xiangshan.mem.Bundles._ 32import xiangshan.backend.rob.RobPtr 33import xiangshan.backend.Bundles.{MemExuOutput, DynInst} 34import xiangshan.backend.fu.FuConfig.LduCfg 35import xiangshan.cache.mmu.HasTlbConst 36import xiangshan.cache._ 37import xiangshan.cache.wpu.ReplayCarry 38 39class LoadMisalignBuffer(implicit p: Parameters) extends XSModule 40 with HasCircularQueuePtrHelper 41 with HasLoadHelper 42 with HasTlbConst 43{ 44 private val enqPortNum = LoadPipelineWidth 45 private val maxSplitNum = 2 46 47 require(maxSplitNum == 2) 48 49 private val LB = "b00".U(2.W) 50 private val LH = "b01".U(2.W) 51 private val LW = "b10".U(2.W) 52 private val LD = "b11".U(2.W) 53 54 // encode of how many bytes to shift or truncate 55 private val BYTE0 = "b000".U(3.W) 56 private val BYTE1 = "b001".U(3.W) 57 private val BYTE2 = "b010".U(3.W) 58 private val BYTE3 = "b011".U(3.W) 59 private val BYTE4 = "b100".U(3.W) 60 private val BYTE5 = "b101".U(3.W) 61 private val BYTE6 = "b110".U(3.W) 62 private val BYTE7 = "b111".U(3.W) 63 64 def getMask(sizeEncode: UInt) = LookupTree(sizeEncode, List( 65 LB -> 0x1.U, // lb 66 LH -> 0x3.U, // lh 67 LW -> 0xf.U, // lw 68 LD -> 0xff.U // ld 69 )) 70 71 def getShiftAndTruncateData(shiftEncode: UInt, truncateEncode: UInt, data: UInt) = { 72 val shiftData = LookupTree(shiftEncode, List( 73 BYTE0 -> data(63, 0), 74 BYTE1 -> data(63, 8), 75 BYTE2 -> data(63, 16), 76 BYTE3 -> data(63, 24), 77 BYTE4 -> data(63, 32), 78 BYTE5 -> data(63, 40), 79 BYTE6 -> data(63, 48), 80 BYTE7 -> data(63, 56) 81 )) 82 val truncateData = LookupTree(truncateEncode, List( 83 BYTE0 -> 0.U(XLEN.W), // can not truncate with 0 byte width 84 BYTE1 -> shiftData(7, 0), 85 BYTE2 -> shiftData(15, 0), 86 BYTE3 -> shiftData(23, 0), 87 BYTE4 -> shiftData(31, 0), 88 BYTE5 -> shiftData(39, 0), 89 BYTE6 -> shiftData(47, 0), 90 BYTE7 -> shiftData(55, 0) 91 )) 92 truncateData(XLEN - 1, 0) 93 } 94 95 def selectOldest[T <: LqWriteBundle](valid: Seq[Bool], bits: Seq[T]): (Seq[Bool], Seq[T]) = { 96 assert(valid.length == bits.length) 97 if (valid.length == 0 || valid.length == 1) { 98 (valid, bits) 99 } else if (valid.length == 2) { 100 val res = Seq.fill(2)(Wire(ValidIO(chiselTypeOf(bits(0))))) 101 for (i <- res.indices) { 102 res(i).valid := valid(i) 103 res(i).bits := bits(i) 104 } 105 val oldest = Mux(valid(0) && valid(1), 106 Mux(isAfter(bits(0).uop.robIdx, bits(1).uop.robIdx) || 107 (bits(0).uop.robIdx === bits(1).uop.robIdx && bits(0).uop.uopIdx > bits(1).uop.uopIdx), res(1), res(0)), 108 Mux(valid(0) && !valid(1), res(0), res(1))) 109 (Seq(oldest.valid), Seq(oldest.bits)) 110 } else { 111 val left = selectOldest(valid.take(valid.length / 2), bits.take(bits.length / 2)) 112 val right = selectOldest(valid.takeRight(valid.length - (valid.length / 2)), bits.takeRight(bits.length - (bits.length / 2))) 113 selectOldest(left._1 ++ right._1, left._2 ++ right._2) 114 } 115 } 116 117 val io = IO(new Bundle() { 118 val redirect = Flipped(Valid(new Redirect)) 119 val req = Vec(enqPortNum, Flipped(Decoupled(new LqWriteBundle))) 120 val rob = Flipped(new RobLsqIO) 121 val splitLoadReq = Decoupled(new LsPipelineBundle) 122 val splitLoadResp = Flipped(Valid(new LqWriteBundle)) 123 val writeBack = Decoupled(new MemExuOutput) 124 val vecWriteBack = Decoupled(new VecPipelineFeedbackIO(isVStore = false)) 125 val loadOutValid = Input(Bool()) 126 val loadVecOutValid = Input(Bool()) 127 val overwriteExpBuf = Output(new XSBundle { 128 val valid = Bool() 129 val vaddr = UInt(XLEN.W) 130 val isHyper = Bool() 131 val gpaddr = UInt(XLEN.W) 132 val isForVSnonLeafPTE = Bool() 133 }) 134 val flushLdExpBuff = Output(Bool()) 135 val loadMisalignFull = Output(Bool()) 136 }) 137 138 io.rob.mmio := 0.U.asTypeOf(Vec(LoadPipelineWidth, Bool())) 139 io.rob.uop := 0.U.asTypeOf(Vec(LoadPipelineWidth, new DynInst)) 140 141 val req_valid = RegInit(false.B) 142 val req = Reg(new LqWriteBundle) 143 144 io.loadMisalignFull := req_valid 145 146 (0 until io.req.length).map{i => 147 if (i == 0) { 148 io.req(0).ready := !req_valid && io.req(0).valid 149 } 150 else { 151 io.req(i).ready := !io.req.take(i).map(_.ready).reduce(_ || _) && !req_valid && io.req(i).valid 152 } 153 } 154 155 156 val select_req_bit = ParallelPriorityMux(io.req.map(_.valid), io.req.map(_.bits)) 157 val select_req_valid = io.req.map(_.valid).reduce(_ || _) 158 val canEnqValid = !req_valid && !select_req_bit.uop.robIdx.needFlush(io.redirect) && select_req_valid 159 when(canEnqValid) { 160 req := select_req_bit 161 req_valid := true.B 162 } 163 164 // buffer control: 165 // - s_idle: idle 166 // - s_split: split misalign laod 167 // - s_req: issue a split memory access request 168 // - s_resp: Responds to a split load access request 169 // - s_comb_wakeup_rep: Merge the data and issue a wakeup load 170 // - s_wb: writeback yo rob/vecMergeBuffer 171 val s_idle :: s_split :: s_req :: s_resp :: s_comb_wakeup_rep :: s_wb :: Nil = Enum(6) 172 val bufferState = RegInit(s_idle) 173 val splitLoadReqs = RegInit(VecInit(List.fill(maxSplitNum)(0.U.asTypeOf(new LsPipelineBundle)))) 174 val splitLoadResp = RegInit(VecInit(List.fill(maxSplitNum)(0.U.asTypeOf(new LqWriteBundle)))) 175 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 176 val unSentLoads = RegInit(0.U(maxSplitNum.W)) 177 val curPtr = RegInit(0.U(log2Ceil(maxSplitNum).W)) 178 val needWakeUpReqsWire = Wire(Bool()) 179 val needWakeUpWB = RegInit(false.B) 180 val data_select = RegEnable(genRdataOH(select_req_bit.uop), 0.U(genRdataOH(select_req_bit.uop).getWidth.W), canEnqValid) 181 182 // if there is exception or mmio in split load 183 val globalException = RegInit(false.B) 184 val globalMMIO = RegInit(false.B) 185 186 val hasException = io.splitLoadResp.bits.vecActive && 187 ExceptionNO.selectByFu(io.splitLoadResp.bits.uop.exceptionVec, LduCfg).asUInt.orR || TriggerAction.isDmode(io.splitLoadResp.bits.uop.trigger) 188 val isMMIO = io.splitLoadResp.bits.mmio 189 needWakeUpReqsWire := false.B 190 switch(bufferState) { 191 is (s_idle) { 192 when (req_valid) { 193 bufferState := s_split 194 } 195 } 196 197 is (s_split) { 198 bufferState := s_req 199 } 200 201 is (s_req) { 202 when (io.splitLoadReq.fire) { 203 bufferState := s_resp 204 } 205 } 206 207 is (s_resp) { 208 when (io.splitLoadResp.valid) { 209 val clearOh = UIntToOH(curPtr) 210 when (hasException || isMMIO) { 211 // commit directly when exception ocurs 212 // if any split load reaches mmio space, delegate to software loadAddrMisaligned exception 213 bufferState := s_wb 214 globalException := hasException 215 globalMMIO := isMMIO 216 } .elsewhen(io.splitLoadResp.bits.rep_info.need_rep || (unSentLoads & ~clearOh).orR) { 217 // need replay or still has unsent requests 218 bufferState := s_req 219 } .otherwise { 220 // merge the split load results 221 bufferState := s_comb_wakeup_rep 222 needWakeUpWB := !req.isvec 223 } 224 } 225 } 226 227 is (s_comb_wakeup_rep) { 228 when(!req.isvec) { 229 when(io.splitLoadReq.fire) { 230 bufferState := s_wb 231 }.otherwise { 232 bufferState := s_comb_wakeup_rep 233 } 234 needWakeUpReqsWire := true.B 235 } .otherwise { 236 bufferState := s_wb 237 } 238 239 } 240 241 is (s_wb) { 242 when(req.isvec) { 243 when(io.vecWriteBack.fire) { 244 bufferState := s_idle 245 req_valid := false.B 246 curPtr := 0.U 247 unSentLoads := 0.U 248 globalException := false.B 249 globalMMIO := false.B 250 needWakeUpWB := false.B 251 } 252 253 } .otherwise { 254 when(io.writeBack.fire) { 255 bufferState := s_idle 256 req_valid := false.B 257 curPtr := 0.U 258 unSentLoads := 0.U 259 globalException := false.B 260 globalMMIO := false.B 261 needWakeUpWB := false.B 262 } 263 } 264 265 } 266 } 267 268 val alignedType = Mux(req.isvec, req.alignedType(1,0), req.uop.fuOpType(1, 0)) 269 val highAddress = LookupTree(alignedType, List( 270 LB -> 0.U, 271 LH -> 1.U, 272 LW -> 3.U, 273 LD -> 7.U 274 )) + req.vaddr(4, 0) 275 // to see if (vaddr + opSize - 1) and vaddr are in the same 16 bytes region 276 val cross16BytesBoundary = req_valid && (highAddress(4) =/= req.vaddr(4)) 277 val aligned16BytesAddr = (req.vaddr >> 4) << 4// req.vaddr & ~("b1111".U) 278 val aligned16BytesSel = req.vaddr(3, 0) 279 280 // meta of 128 bit load 281 val new128Load = WireInit(0.U.asTypeOf(new LsPipelineBundle)) 282 // meta of split loads 283 val lowAddrLoad = WireInit(0.U.asTypeOf(new LsPipelineBundle)) 284 val highAddrLoad = WireInit(0.U.asTypeOf(new LsPipelineBundle)) 285 val lowResultShift = RegInit(0.U(3.W)) // how many bytes should we shift right when got result 286 val lowResultWidth = RegInit(0.U(3.W)) // how many bytes should we take from result 287 val highResultShift = RegInit(0.U(3.W)) 288 val highResultWidth = RegInit(0.U(3.W)) 289 290 when (bufferState === s_split) { 291 when (!cross16BytesBoundary) { 292 assert(false.B, s"There should be no non-aligned access that does not cross 16Byte boundaries.") 293 } .otherwise { 294 // split this unaligned load into `maxSplitNum` aligned loads 295 unSentLoads := Fill(maxSplitNum, 1.U(1.W)) 296 curPtr := 0.U 297 lowAddrLoad.uop := req.uop 298 lowAddrLoad.uop.exceptionVec(loadAddrMisaligned) := false.B 299 lowAddrLoad.fullva := req.fullva 300 highAddrLoad.uop := req.uop 301 highAddrLoad.uop.exceptionVec(loadAddrMisaligned) := false.B 302 highAddrLoad.fullva := req.fullva 303 304 switch (alignedType(1, 0)) { 305 is (LB) { 306 assert(false.B, "lb should not trigger miss align") 307 } 308 309 is (LH) { 310 lowAddrLoad.uop.fuOpType := LB 311 lowAddrLoad.vaddr := req.vaddr 312 lowAddrLoad.mask := 0x1.U << lowAddrLoad.vaddr(3, 0) 313 lowResultShift := BYTE0 314 lowResultWidth := BYTE1 315 316 highAddrLoad.uop.fuOpType := LB 317 highAddrLoad.vaddr := req.vaddr + 1.U 318 highAddrLoad.mask := 0x1.U << highAddrLoad.vaddr(3, 0) 319 highResultShift := BYTE0 320 highResultWidth := BYTE1 321 } 322 323 is (LW) { 324 switch (req.vaddr(1, 0)) { 325 is ("b00".U) { 326 assert(false.B, "should not trigger miss align") 327 } 328 329 is ("b01".U) { 330 lowAddrLoad.uop.fuOpType := LW 331 lowAddrLoad.vaddr := req.vaddr - 1.U 332 lowAddrLoad.mask := 0xf.U << lowAddrLoad.vaddr(3, 0) 333 lowResultShift := BYTE1 334 lowResultWidth := BYTE3 335 336 highAddrLoad.uop.fuOpType := LB 337 highAddrLoad.vaddr := req.vaddr + 3.U 338 highAddrLoad.mask := 0x1.U << highAddrLoad.vaddr(3, 0) 339 highResultShift := BYTE0 340 highResultWidth := BYTE1 341 } 342 343 is ("b10".U) { 344 lowAddrLoad.uop.fuOpType := LH 345 lowAddrLoad.vaddr := req.vaddr 346 lowAddrLoad.mask := 0x3.U << lowAddrLoad.vaddr(3, 0) 347 lowResultShift := BYTE0 348 lowResultWidth := BYTE2 349 350 highAddrLoad.uop.fuOpType := LH 351 highAddrLoad.vaddr := req.vaddr + 2.U 352 highAddrLoad.mask := 0x3.U << highAddrLoad.vaddr(3, 0) 353 highResultShift := BYTE0 354 highResultWidth := BYTE2 355 } 356 357 is ("b11".U) { 358 lowAddrLoad.uop.fuOpType := LB 359 lowAddrLoad.vaddr := req.vaddr 360 lowAddrLoad.mask := 0x1.U << lowAddrLoad.vaddr(3, 0) 361 lowResultShift := BYTE0 362 lowResultWidth := BYTE1 363 364 highAddrLoad.uop.fuOpType := LW 365 highAddrLoad.vaddr := req.vaddr + 1.U 366 highAddrLoad.mask := 0xf.U << highAddrLoad.vaddr(3, 0) 367 highResultShift := BYTE0 368 highResultWidth := BYTE3 369 } 370 } 371 } 372 373 is (LD) { 374 switch (req.vaddr(2, 0)) { 375 is ("b000".U) { 376 assert(false.B, "should not trigger miss align") 377 } 378 379 is ("b001".U) { 380 lowAddrLoad.uop.fuOpType := LD 381 lowAddrLoad.vaddr := req.vaddr - 1.U 382 lowAddrLoad.mask := 0xff.U << lowAddrLoad.vaddr(3, 0) 383 lowResultShift := BYTE1 384 lowResultWidth := BYTE7 385 386 highAddrLoad.uop.fuOpType := LB 387 highAddrLoad.vaddr := req.vaddr + 7.U 388 highAddrLoad.mask := 0x1.U << highAddrLoad.vaddr(3, 0) 389 highResultShift := BYTE0 390 highResultWidth := BYTE1 391 } 392 393 is ("b010".U) { 394 lowAddrLoad.uop.fuOpType := LD 395 lowAddrLoad.vaddr := req.vaddr - 2.U 396 lowAddrLoad.mask := 0xff.U << lowAddrLoad.vaddr(3, 0) 397 lowResultShift := BYTE2 398 lowResultWidth := BYTE6 399 400 highAddrLoad.uop.fuOpType := LH 401 highAddrLoad.vaddr := req.vaddr + 6.U 402 highAddrLoad.mask := 0x3.U << highAddrLoad.vaddr(3, 0) 403 highResultShift := BYTE0 404 highResultWidth := BYTE2 405 } 406 407 is ("b011".U) { 408 lowAddrLoad.uop.fuOpType := LD 409 lowAddrLoad.vaddr := req.vaddr - 3.U 410 lowAddrLoad.mask := 0xff.U << lowAddrLoad.vaddr(3, 0) 411 lowResultShift := BYTE3 412 lowResultWidth := BYTE5 413 414 highAddrLoad.uop.fuOpType := LW 415 highAddrLoad.vaddr := req.vaddr + 5.U 416 highAddrLoad.mask := 0xf.U << highAddrLoad.vaddr(3, 0) 417 highResultShift := BYTE0 418 highResultWidth := BYTE3 419 } 420 421 is ("b100".U) { 422 lowAddrLoad.uop.fuOpType := LW 423 lowAddrLoad.vaddr := req.vaddr 424 lowAddrLoad.mask := 0xf.U << lowAddrLoad.vaddr(3, 0) 425 lowResultShift := BYTE0 426 lowResultWidth := BYTE4 427 428 highAddrLoad.uop.fuOpType := LW 429 highAddrLoad.vaddr := req.vaddr + 4.U 430 highAddrLoad.mask := 0xf.U << highAddrLoad.vaddr(3, 0) 431 highResultShift := BYTE0 432 highResultWidth := BYTE4 433 } 434 435 is ("b101".U) { 436 lowAddrLoad.uop.fuOpType := LW 437 lowAddrLoad.vaddr := req.vaddr - 1.U 438 lowAddrLoad.mask := 0xf.U << lowAddrLoad.vaddr(3, 0) 439 lowResultShift := BYTE1 440 lowResultWidth := BYTE3 441 442 highAddrLoad.uop.fuOpType := LD 443 highAddrLoad.vaddr := req.vaddr + 3.U 444 highAddrLoad.mask := 0xff.U << highAddrLoad.vaddr(3, 0) 445 highResultShift := BYTE0 446 highResultWidth := BYTE5 447 } 448 449 is ("b110".U) { 450 lowAddrLoad.uop.fuOpType := LH 451 lowAddrLoad.vaddr := req.vaddr 452 lowAddrLoad.mask := 0x3.U << lowAddrLoad.vaddr(3, 0) 453 lowResultShift := BYTE0 454 lowResultWidth := BYTE2 455 456 highAddrLoad.uop.fuOpType := LD 457 highAddrLoad.vaddr := req.vaddr + 2.U 458 highAddrLoad.mask := 0xff.U << highAddrLoad.vaddr(3, 0) 459 highResultShift := BYTE0 460 highResultWidth := BYTE6 461 } 462 463 is ("b111".U) { 464 lowAddrLoad.uop.fuOpType := LB 465 lowAddrLoad.vaddr := req.vaddr 466 lowAddrLoad.mask := 0x1.U << lowAddrLoad.vaddr(3, 0) 467 lowResultShift := BYTE0 468 lowResultWidth := BYTE1 469 470 highAddrLoad.uop.fuOpType := LD 471 highAddrLoad.vaddr := req.vaddr + 1.U 472 highAddrLoad.mask := 0xff.U << highAddrLoad.vaddr(3, 0) 473 highResultShift := BYTE0 474 highResultWidth := BYTE7 475 } 476 } 477 } 478 } 479 480 splitLoadReqs(0) := lowAddrLoad 481 splitLoadReqs(1) := highAddrLoad 482 } 483 exceptionVec := 0.U.asTypeOf(exceptionVec.cloneType) 484 } 485 486 io.splitLoadReq.valid := req_valid && (bufferState === s_req || bufferState === s_comb_wakeup_rep && needWakeUpReqsWire && !req.isvec) 487 io.splitLoadReq.bits := splitLoadReqs(curPtr) 488 io.splitLoadReq.bits.isvec := req.isvec 489 io.splitLoadReq.bits.misalignNeedWakeUp := needWakeUpReqsWire 490 io.splitLoadReq.bits.isFinalSplit := curPtr(0) && !needWakeUpReqsWire 491 // Restore the information of H extension load 492 // bit encoding: | hlv 1 | hlvx 1 | is unsigned(1bit) | size(2bit) | 493 val reqIsHlv = LSUOpType.isHlv(req.uop.fuOpType) 494 val reqIsHlvx = LSUOpType.isHlvx(req.uop.fuOpType) 495 io.splitLoadReq.bits.uop.fuOpType := Mux(req.isvec, req.uop.fuOpType, Cat(reqIsHlv, reqIsHlvx, 0.U(1.W), splitLoadReqs(curPtr).uop.fuOpType(1, 0))) 496 io.splitLoadReq.bits.alignedType := Mux(req.isvec, splitLoadReqs(curPtr).uop.fuOpType(1, 0), req.alignedType) 497 498 when (io.splitLoadResp.valid) { 499 val resp = io.splitLoadResp.bits 500 splitLoadResp(curPtr) := io.splitLoadResp.bits 501 when (isMMIO) { 502 unSentLoads := 0.U 503 exceptionVec := ExceptionNO.selectByFu(0.U.asTypeOf(exceptionVec.cloneType), LduCfg) 504 // delegate to software 505 exceptionVec(loadAddrMisaligned) := true.B 506 } .elsewhen (hasException) { 507 unSentLoads := 0.U 508 LduCfg.exceptionOut.map(no => exceptionVec(no) := exceptionVec(no) || resp.uop.exceptionVec(no)) 509 } .elsewhen (!io.splitLoadResp.bits.rep_info.need_rep) { 510 unSentLoads := unSentLoads & ~UIntToOH(curPtr) 511 curPtr := curPtr + 1.U 512 exceptionVec := 0.U.asTypeOf(ExceptionVec()) 513 } 514 } 515 516 val combinedData = RegInit(0.U(XLEN.W)) 517 518 when (bufferState === s_comb_wakeup_rep) { 519 val lowAddrResult = getShiftAndTruncateData(lowResultShift, lowResultWidth, splitLoadResp(0).data) 520 .asTypeOf(Vec(XLEN / 8, UInt(8.W))) 521 val highAddrResult = getShiftAndTruncateData(highResultShift, highResultWidth, splitLoadResp(1).data) 522 .asTypeOf(Vec(XLEN / 8, UInt(8.W))) 523 val catResult = Wire(Vec(XLEN / 8, UInt(8.W))) 524 (0 until XLEN / 8) .map { 525 case i => { 526 when (i.U < lowResultWidth) { 527 catResult(i) := lowAddrResult(i) 528 } .otherwise { 529 catResult(i) := highAddrResult(i.U - lowResultWidth) 530 } 531 } 532 } 533 combinedData := Mux(req.isvec, rdataVecHelper(req.alignedType, (catResult.asUInt)(XLEN - 1, 0)), rdataHelper(req.uop, (catResult.asUInt)(XLEN - 1, 0))) 534 535 } 536 537 io.writeBack.valid := req_valid && (bufferState === s_wb) && (io.splitLoadResp.valid && io.splitLoadResp.bits.misalignNeedWakeUp || globalMMIO || globalException) && !io.loadOutValid && !req.isvec 538 io.writeBack.bits.uop := req.uop 539 io.writeBack.bits.uop.exceptionVec := DontCare 540 LduCfg.exceptionOut.map(no => io.writeBack.bits.uop.exceptionVec(no) := (globalMMIO || globalException) && exceptionVec(no)) 541 io.writeBack.bits.uop.rfWen := !globalException && !globalMMIO && req.uop.rfWen 542 io.writeBack.bits.uop.fuType := FuType.ldu.U 543 io.writeBack.bits.uop.flushPipe := false.B 544 io.writeBack.bits.uop.replayInst := false.B 545 io.writeBack.bits.data := newRdataHelper(data_select, combinedData) 546 io.writeBack.bits.isFromLoadUnit := needWakeUpWB 547 io.writeBack.bits.debug.isMMIO := globalMMIO 548 // FIXME lyq: temporarily set to false 549 io.writeBack.bits.debug.isNC := false.B 550 io.writeBack.bits.debug.isPerfCnt := false.B 551 io.writeBack.bits.debug.paddr := req.paddr 552 io.writeBack.bits.debug.vaddr := req.vaddr 553 554 555 // vector output 556 io.vecWriteBack.valid := req_valid && (bufferState === s_wb) && !io.loadVecOutValid && req.isvec 557 558 io.vecWriteBack.bits.alignedType := req.alignedType 559 io.vecWriteBack.bits.vecFeedback := true.B 560 io.vecWriteBack.bits.vecdata.get := combinedData 561 io.vecWriteBack.bits.isvec := req.isvec 562 io.vecWriteBack.bits.elemIdx := req.elemIdx 563 io.vecWriteBack.bits.elemIdxInsideVd.get := req.elemIdxInsideVd 564 io.vecWriteBack.bits.mask := req.mask 565 io.vecWriteBack.bits.reg_offset.get := 0.U 566 io.vecWriteBack.bits.usSecondInv := req.usSecondInv 567 io.vecWriteBack.bits.mBIndex := req.mbIndex 568 io.vecWriteBack.bits.hit := true.B 569 io.vecWriteBack.bits.sourceType := RSFeedbackType.lrqFull 570 io.vecWriteBack.bits.trigger := TriggerAction.None 571 io.vecWriteBack.bits.flushState := DontCare 572 io.vecWriteBack.bits.exceptionVec := ExceptionNO.selectByFu(exceptionVec, VlduCfg) 573 io.vecWriteBack.bits.hasException := globalException 574 io.vecWriteBack.bits.vaddr := req.fullva 575 io.vecWriteBack.bits.vaNeedExt := req.vaNeedExt 576 io.vecWriteBack.bits.gpaddr := req.gpaddr 577 io.vecWriteBack.bits.isForVSnonLeafPTE := req.isForVSnonLeafPTE 578 io.vecWriteBack.bits.mmio := DontCare 579 io.vecWriteBack.bits.vstart := req.uop.vpu.vstart 580 io.vecWriteBack.bits.vecTriggerMask := req.vecTriggerMask 581 io.vecWriteBack.bits.nc := false.B 582 583 584 val flush = req_valid && req.uop.robIdx.needFlush(io.redirect) 585 586 when (flush) { 587 bufferState := s_idle 588 req_valid := false.B 589 curPtr := 0.U 590 unSentLoads := 0.U 591 globalException := false.B 592 globalMMIO := false.B 593 } 594 595 // NOTE: spectial case (unaligned load cross page, page fault happens in next page) 596 // if exception happens in the higher page address part, overwrite the loadExceptionBuffer vaddr 597 val shouldOverwrite = req_valid && globalException 598 val overwriteExpBuf = GatedValidRegNext(shouldOverwrite) 599 val overwriteVaddr = RegEnable( 600 Mux( 601 cross16BytesBoundary && (curPtr === 1.U), 602 splitLoadResp(curPtr).vaddr, 603 splitLoadResp(curPtr).fullva), 604 shouldOverwrite) 605 val overwriteGpaddr = RegEnable(splitLoadResp(curPtr).gpaddr, shouldOverwrite) 606 val overwriteIsHyper = RegEnable(splitLoadResp(curPtr).isHyper, shouldOverwrite) 607 val overwriteIsForVSnonLeafPTE = RegEnable(splitLoadResp(curPtr).isForVSnonLeafPTE, shouldOverwrite) 608 609 //TODO In theory, there is no need to overwrite, but for now, the signal is retained in the code in this way. 610 // and the signal will be removed after sufficient verification. 611 io.overwriteExpBuf.valid := false.B 612 io.overwriteExpBuf.vaddr := overwriteVaddr 613 io.overwriteExpBuf.isHyper := overwriteIsHyper 614 io.overwriteExpBuf.gpaddr := overwriteGpaddr 615 io.overwriteExpBuf.isForVSnonLeafPTE := overwriteIsForVSnonLeafPTE 616 617 // when no exception or mmio, flush loadExceptionBuffer at s_wb 618 val flushLdExpBuff = GatedValidRegNext(req_valid && (bufferState === s_wb) && !(globalMMIO || globalException)) 619 io.flushLdExpBuff := flushLdExpBuff 620 621 XSPerfAccumulate("alloc", RegNext(!req_valid) && req_valid) 622 XSPerfAccumulate("flush", flush) 623 XSPerfAccumulate("flush_idle", flush && (bufferState === s_idle)) 624 XSPerfAccumulate("flush_non_idle", flush && (bufferState =/= s_idle)) 625} 626