1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.exu.ExeUnitParams 27import xiangshan.backend.fu.FuConfig._ 28import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 29import xiangshan.backend.regfile._ 30import xiangshan.backend.BackendParams 31import xiangshan.backend.trace._ 32import xiangshan.cache.DCacheParameters 33import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 34import xiangshan.frontend.icache.ICacheParameters 35import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 36import xiangshan.frontend._ 37import xiangshan.frontend.icache.ICacheParameters 38import freechips.rocketchip.diplomacy.AddressSet 39import freechips.rocketchip.tile.MaxHartIdBits 40import system.SoCParamsKey 41import huancun._ 42import huancun.debug._ 43import xiangshan.cache.wpu.WPUParameters 44import coupledL2._ 45import coupledL2.tl2chi._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.{max, min, pow} 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HSXLEN: Int = 64, 63 HasMExtension: Boolean = true, 64 HasCExtension: Boolean = true, 65 HasHExtension: Boolean = true, 66 HasDiv: Boolean = true, 67 HasICache: Boolean = true, 68 HasDCache: Boolean = true, 69 AddrBits: Int = 64, 70 PAddrBitsMax: Int = 56, // The bits of physical address from Sv39/Sv48/Sv57 virtual address translation. 71 VAddrBitsSv39: Int = 39, 72 GPAddrBitsSv39x4: Int = 41, 73 VAddrBitsSv48: Int = 48, 74 GPAddrBitsSv48x4: Int = 50, 75 HasFPU: Boolean = true, 76 HasVPU: Boolean = true, 77 HasCustomCSRCacheOp: Boolean = true, 78 FetchWidth: Int = 8, 79 AsidLength: Int = 16, 80 VmidLength: Int = 14, 81 EnableBPU: Boolean = true, 82 EnableBPD: Boolean = true, 83 EnableRAS: Boolean = true, 84 EnableLB: Boolean = false, 85 EnableLoop: Boolean = true, 86 EnableSC: Boolean = true, 87 EnbaleTlbDebug: Boolean = false, 88 EnableClockGate: Boolean = true, 89 EnableJal: Boolean = false, 90 EnableFauFTB: Boolean = true, 91 EnableSv48: Boolean = true, 92 UbtbGHRLength: Int = 4, 93 // HistoryLength: Int = 512, 94 EnableGHistDiff: Boolean = true, 95 EnableCommitGHistDiff: Boolean = true, 96 UbtbSize: Int = 256, 97 FtbSize: Int = 2048, 98 FtbWays: Int = 4, 99 FtbTagLength: Int = 20, 100 RasSize: Int = 16, 101 RasSpecSize: Int = 32, 102 RasCtrSize: Int = 3, 103 CacheLineSize: Int = 512, 104 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 105 // Sets Hist Tag 106 Seq(( 4096, 8, 8), 107 ( 4096, 13, 8), 108 ( 4096, 32, 8), 109 ( 4096, 119, 8)), 110 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 111 // Sets Hist Tag 112 Seq(( 256, 4, 9), 113 ( 256, 8, 9), 114 ( 512, 13, 9), 115 ( 512, 16, 9), 116 ( 512, 32, 9)), 117 SCNRows: Int = 512, 118 SCNTables: Int = 4, 119 SCCtrBits: Int = 6, 120 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 121 numBr: Int = 2, 122 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 123 (resp_in: BranchPredictionResp, p: Parameters) => { 124 val ftb = Module(new FTB()(p)) 125 val uftb = Module(new FauFTB()(p)) 126 val tage = Module(new Tage_SC()(p)) 127 val ras = Module(new RAS()(p)) 128 val ittage = Module(new ITTage()(p)) 129 val preds = Seq(uftb, tage, ftb, ittage, ras) 130 preds.map(_.io := DontCare) 131 132 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 133 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 134 135 uftb.io.in.bits.resp_in(0) := resp_in 136 tage.io.in.bits.resp_in(0) := uftb.io.out 137 ftb.io.in.bits.resp_in(0) := tage.io.out 138 ittage.io.in.bits.resp_in(0) := ftb.io.out 139 ras.io.in.bits.resp_in(0) := ittage.io.out 140 141 (preds, ras.io.out) 142 }, 143 ICacheForceMetaECCError: Boolean = false, 144 ICacheForceDataECCError: Boolean = false, 145 IBufSize: Int = 48, 146 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 147 DecodeWidth: Int = 6, 148 RenameWidth: Int = 6, 149 CommitWidth: Int = 8, 150 RobCommitWidth: Int = 8, 151 RabCommitWidth: Int = 6, 152 MaxUopSize: Int = 65, 153 EnableRenameSnapshot: Boolean = true, 154 RenameSnapshotNum: Int = 4, 155 FtqSize: Int = 64, 156 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 157 IntLogicRegs: Int = 32, 158 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 159 VecLogicRegs: Int = 32 + 15, // 15: tmp 160 V0LogicRegs: Int = 1, // V0 161 VlLogicRegs: Int = 1, // Vl 162 V0_IDX: Int = 0, 163 Vl_IDX: Int = 0, 164 NRPhyRegs: Int = 192, 165 VirtualLoadQueueSize: Int = 72, 166 LoadQueueRARSize: Int = 72, 167 LoadQueueRAWSize: Int = 32, // NOTE: make sure that LoadQueueRAWSize is power of 2. 168 RollbackGroupSize: Int = 8, 169 LoadQueueReplaySize: Int = 72, 170 LoadUncacheBufferSize: Int = 4, 171 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 172 StoreQueueSize: Int = 56, 173 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 174 StoreQueueForwardWithMask: Boolean = true, 175 VlsQueueSize: Int = 8, 176 RobSize: Int = 160, 177 RabSize: Int = 256, 178 VTypeBufferSize: Int = 64, // used to reorder vtype 179 IssueQueueSize: Int = 24, 180 IssueQueueCompEntrySize: Int = 16, 181 intPreg: PregParams = IntPregParams( 182 numEntries = 224, 183 numRead = None, 184 numWrite = None, 185 ), 186 fpPreg: PregParams = FpPregParams( 187 numEntries = 192, 188 numRead = None, 189 numWrite = None, 190 ), 191 vfPreg: VfPregParams = VfPregParams( 192 numEntries = 128, 193 numRead = None, 194 numWrite = None, 195 ), 196 v0Preg: V0PregParams = V0PregParams( 197 numEntries = 22, 198 numRead = None, 199 numWrite = None, 200 ), 201 vlPreg: VlPregParams = VlPregParams( 202 numEntries = 32, 203 numRead = None, 204 numWrite = None, 205 ), 206 IntRegCacheSize: Int = 16, 207 MemRegCacheSize: Int = 12, 208 intSchdVlWbPort: Int = 0, 209 vfSchdVlWbPort: Int = 1, 210 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 211 IfuRedirectNum: Int = 1, 212 LoadPipelineWidth: Int = 3, 213 StorePipelineWidth: Int = 2, 214 VecLoadPipelineWidth: Int = 2, 215 VecStorePipelineWidth: Int = 2, 216 VecMemSrcInWidth: Int = 2, 217 VecMemInstWbWidth: Int = 1, 218 VecMemDispatchWidth: Int = 1, 219 VecMemDispatchMaxNumber: Int = 16, 220 VecMemUnitStrideMaxFlowNum: Int = 2, 221 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 16, 16, 16, 16, 16), 222 StoreBufferSize: Int = 16, 223 StoreBufferThreshold: Int = 7, 224 EnsbufferWidth: Int = 2, 225 LoadDependencyWidth: Int = 2, 226 // ============ VLSU ============ 227 VlMergeBufferSize: Int = 16, 228 VsMergeBufferSize: Int = 16, 229 UopWritebackWidth: Int = 2, 230 VLUopWritebackWidth: Int = 2, 231 VSUopWritebackWidth: Int = 1, 232 VSegmentBufferSize: Int = 8, 233 VFOFBufferSize: Int = 8, 234 VLFOFWritebackWidth: Int = 1, 235 // ============================== 236 UncacheBufferSize: Int = 4, 237 EnableLoadToLoadForward: Boolean = false, 238 EnableFastForward: Boolean = true, 239 EnableLdVioCheckAfterReset: Boolean = true, 240 EnableSoftPrefetchAfterReset: Boolean = true, 241 EnableCacheErrorAfterReset: Boolean = true, 242 EnableAccurateLoadError: Boolean = false, 243 EnableUncacheWriteOutstanding: Boolean = false, 244 EnableHardwareStoreMisalign: Boolean = true, 245 EnableHardwareLoadMisalign: Boolean = true, 246 EnableStorePrefetchAtIssue: Boolean = false, 247 EnableStorePrefetchAtCommit: Boolean = false, 248 EnableAtCommitMissTrigger: Boolean = true, 249 EnableStorePrefetchSMS: Boolean = false, 250 EnableStorePrefetchSPB: Boolean = false, 251 HasCMO: Boolean = true, 252 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 253 MMUVmidLen: Int = 14, 254 ReSelectLen: Int = 7, // load replay queue replay select counter len 255 iwpuParameters: WPUParameters = WPUParameters( 256 enWPU = false, 257 algoName = "mmru", 258 isICache = true, 259 ), 260 dwpuParameters: WPUParameters = WPUParameters( 261 enWPU = false, 262 algoName = "mmru", 263 enCfPred = false, 264 isICache = false, 265 ), 266 itlbParameters: TLBParameters = TLBParameters( 267 name = "itlb", 268 fetchi = true, 269 useDmode = false, 270 NWays = 48, 271 ), 272 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 273 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 274 ldtlbParameters: TLBParameters = TLBParameters( 275 name = "ldtlb", 276 NWays = 48, 277 outReplace = false, 278 partialStaticPMP = true, 279 outsideRecvFlush = true, 280 saveLevel = false, 281 lgMaxSize = 4 282 ), 283 sttlbParameters: TLBParameters = TLBParameters( 284 name = "sttlb", 285 NWays = 48, 286 outReplace = false, 287 partialStaticPMP = true, 288 outsideRecvFlush = true, 289 saveLevel = false, 290 lgMaxSize = 4 291 ), 292 hytlbParameters: TLBParameters = TLBParameters( 293 name = "hytlb", 294 NWays = 48, 295 outReplace = false, 296 partialStaticPMP = true, 297 outsideRecvFlush = true, 298 saveLevel = false, 299 lgMaxSize = 4 300 ), 301 pftlbParameters: TLBParameters = TLBParameters( 302 name = "pftlb", 303 NWays = 48, 304 outReplace = false, 305 partialStaticPMP = true, 306 outsideRecvFlush = true, 307 saveLevel = false, 308 lgMaxSize = 4 309 ), 310 l2ToL1tlbParameters: TLBParameters = TLBParameters( 311 name = "l2tlb", 312 NWays = 48, 313 outReplace = false, 314 partialStaticPMP = true, 315 outsideRecvFlush = true, 316 saveLevel = false 317 ), 318 refillBothTlb: Boolean = false, 319 btlbParameters: TLBParameters = TLBParameters( 320 name = "btlb", 321 NWays = 48, 322 ), 323 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 324 NumPerfCounters: Int = 16, 325 icacheParameters: ICacheParameters = ICacheParameters( 326 tagECC = Some("parity"), 327 dataECC = Some("parity"), 328 replacer = Some("setplru"), 329 cacheCtrlAddressOpt = Some(AddressSet(0x38022080, 0x7f)) 330 ), 331 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 332 tagECC = Some("secded"), 333 dataECC = Some("secded"), 334 replacer = Some("setplru"), 335 nMissEntries = 16, 336 nProbeEntries = 8, 337 nReleaseEntries = 18, 338 nMaxPrefetchEntry = 6, 339 enableTagEcc = true, 340 enableDataEcc = true, 341 cacheCtrlAddressOpt = Some(AddressSet(0x38022000, 0x7f)) 342 )), 343 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 344 name = "l2", 345 ways = 8, 346 sets = 1024, // default 512KB L2 347 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 348 coupledL2.prefetch.TPParameters()), 349 )), 350 L2NBanks: Int = 1, 351 usePTWRepeater: Boolean = false, 352 softTLB: Boolean = false, // dpi-c l1tlb debug only 353 softPTW: Boolean = false, // dpi-c l2tlb debug only 354 softPTWDelay: Int = 1 355){ 356 def ISABase = "rv64i" 357 def ISAExtensions = Seq( 358 // single letter extensions, in canonical order 359 "i", "m", "a", "f", "d", "c", /* "b", */ "v", "h", 360 // multi-letter extensions, sorted alphanumerically 361 "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", 362 "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", 363 "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", 364 "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", 365 "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", 366 "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", 367 "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", 368 "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", 369 "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b" 370 ) 371 372 def vlWidth = log2Up(VLEN) + 1 373 374 /** 375 * the minimum element length of vector elements 376 */ 377 val minVecElen: Int = 8 378 379 /** 380 * the maximum number of elements in vector register 381 */ 382 val maxElemPerVreg: Int = VLEN / minVecElen 383 384 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 385 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 386 387 val RegCacheSize = IntRegCacheSize + MemRegCacheSize 388 val RegCacheIdxWidth = log2Up(RegCacheSize) 389 390 val intSchdParams = { 391 implicit val schdType: SchedulerType = IntScheduler() 392 SchdBlockParams(Seq( 393 IssueBlockParams(Seq( 394 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 395 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1))), true, 2), 396 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 397 IssueBlockParams(Seq( 398 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 399 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1))), true, 2), 400 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 401 IssueBlockParams(Seq( 402 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 403 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = intSchdVlWbPort, 0), FpWB(port = 2, 1)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 404 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 405 IssueBlockParams(Seq( 406 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 407 ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 408 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 409 ), 410 numPregs = intPreg.numEntries, 411 numDeqOutside = 0, 412 schdType = schdType, 413 rfDataWidth = intPreg.dataCfg.dataWidth, 414 ) 415 } 416 417 val fpSchdParams = { 418 implicit val schdType: SchedulerType = FpScheduler() 419 SchdBlockParams(Seq( 420 IssueBlockParams(Seq( 421 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 422 ExeUnitParams("FEX1", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 423 ), numEntries = 18, numEnq = 2, numComp = 14), 424 IssueBlockParams(Seq( 425 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 426 ExeUnitParams("FEX3", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(9, 1)))), 427 ), numEntries = 18, numEnq = 2, numComp = 14), 428 IssueBlockParams(Seq( 429 ExeUnitParams("FEX4", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 1)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 430 ), numEntries = 18, numEnq = 2, numComp = 14), 431 ), 432 numPregs = fpPreg.numEntries, 433 numDeqOutside = 0, 434 schdType = schdType, 435 rfDataWidth = fpPreg.dataCfg.dataWidth, 436 ) 437 } 438 439 val vfSchdParams = { 440 implicit val schdType: SchedulerType = VfScheduler() 441 SchdBlockParams(Seq( 442 IssueBlockParams(Seq( 443 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 444 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = vfSchdVlWbPort, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 445 ), numEntries = 16, numEnq = 2, numComp = 12), 446 IssueBlockParams(Seq( 447 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 448 ExeUnitParams("VFEX3", Seq(VfaluCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 449 ), numEntries = 16, numEnq = 2, numComp = 12), 450 IssueBlockParams(Seq( 451 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 452 ), numEntries = 10, numEnq = 2, numComp = 6), 453 ), 454 numPregs = vfPreg.numEntries, 455 numDeqOutside = 0, 456 schdType = schdType, 457 rfDataWidth = vfPreg.dataCfg.dataWidth, 458 ) 459 } 460 461 val memSchdParams = { 462 implicit val schdType: SchedulerType = MemScheduler() 463 val rfDataWidth = 64 464 465 SchdBlockParams(Seq( 466 IssueBlockParams(Seq( 467 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(7, 2)))), 468 ), numEntries = 16, numEnq = 2, numComp = 12), 469 IssueBlockParams(Seq( 470 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(6, 2)))), 471 ), numEntries = 16, numEnq = 2, numComp = 12), 472 IssueBlockParams(Seq( 473 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(3, 0)), Seq(Seq(IntRD(8, 0))), true, 2), 474 ), numEntries = 16, numEnq = 2, numComp = 12), 475 IssueBlockParams(Seq( 476 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(4, 0)), Seq(Seq(IntRD(9, 0))), true, 2), 477 ), numEntries = 16, numEnq = 2, numComp = 12), 478 IssueBlockParams(Seq( 479 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(5, 0)), Seq(Seq(IntRD(10, 0))), true, 2), 480 ), numEntries = 16, numEnq = 2, numComp = 12), 481 IssueBlockParams(Seq( 482 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0), VlWB(port = 2, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 483 ), numEntries = 16, numEnq = 2, numComp = 12), 484 IssueBlockParams(Seq( 485 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0), VlWB(port = 3, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 486 ), numEntries = 16, numEnq = 2, numComp = 12), 487 IssueBlockParams(Seq( 488 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(9, 0)))), 489 ), numEntries = 16, numEnq = 2, numComp = 12), 490 IssueBlockParams(Seq( 491 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(10, 0)))), 492 ), numEntries = 16, numEnq = 2, numComp = 12), 493 ), 494 numPregs = intPreg.numEntries max vfPreg.numEntries, 495 numDeqOutside = 0, 496 schdType = schdType, 497 rfDataWidth = rfDataWidth, 498 ) 499 } 500 501 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 502 503 def iqWakeUpParams = { 504 Seq( 505 WakeUpConfig( 506 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 507 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 508 ), 509 // TODO: add load -> fp slow wakeup 510 WakeUpConfig( 511 Seq("FEX0", "FEX2", "FEX4") -> 512 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4") 513 ), 514 ).flatten 515 } 516 517 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 518 519 val backendParams: BackendParams = backend.BackendParams( 520 Map( 521 IntScheduler() -> intSchdParams, 522 FpScheduler() -> fpSchdParams, 523 VfScheduler() -> vfSchdParams, 524 MemScheduler() -> memSchdParams, 525 ), 526 Seq( 527 intPreg, 528 fpPreg, 529 vfPreg, 530 v0Preg, 531 vlPreg, 532 fakeIntPreg 533 ), 534 iqWakeUpParams, 535 ) 536 537 // Parameters for trace extension. 538 // Trace parameters is useful for XSTOP. 539 val traceParams: TraceParams = new TraceParams( 540 TraceGroupNum = 3, 541 IaddrWidth = GPAddrBitsSv48x4, 542 PrivWidth = 3, 543 ItypeWidth = 4, 544 IlastsizeWidth = 1, 545 ) 546} 547 548case object DebugOptionsKey extends Field[DebugOptions] 549 550case class DebugOptions 551( 552 FPGAPlatform: Boolean = false, 553 ResetGen: Boolean = false, 554 EnableDifftest: Boolean = false, 555 AlwaysBasicDiff: Boolean = true, 556 EnableDebug: Boolean = false, 557 EnablePerfDebug: Boolean = true, 558 PerfLevel: String = "VERBOSE", 559 UseDRAMSim: Boolean = false, 560 EnableConstantin: Boolean = false, 561 EnableChiselDB: Boolean = false, 562 AlwaysBasicDB: Boolean = true, 563 EnableRollingDB: Boolean = false 564) 565 566trait HasXSParameter { 567 568 implicit val p: Parameters 569 570 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 571 def PmemRanges = p(SoCParamsKey).PmemRanges 572 final val PageOffsetWidth = 12 573 def NodeIDWidth = p(SoCParamsKey).NodeIDWidthList(p(CHIIssue)) // NodeID width among NoC 574 575 def coreParams = p(XSCoreParamsKey) 576 def env = p(DebugOptionsKey) 577 578 def ISABase = coreParams.ISABase 579 def ISAExtensions = coreParams.ISAExtensions 580 def XLEN = coreParams.XLEN 581 def VLEN = coreParams.VLEN 582 def ELEN = coreParams.ELEN 583 def HSXLEN = coreParams.HSXLEN 584 val minFLen = 32 585 val fLen = 64 586 def hartIdLen = p(MaxHartIdBits) 587 val xLen = XLEN 588 589 def HasMExtension = coreParams.HasMExtension 590 def HasCExtension = coreParams.HasCExtension 591 def HasHExtension = coreParams.HasHExtension 592 def EnableSv48 = coreParams.EnableSv48 593 def HasDiv = coreParams.HasDiv 594 def HasIcache = coreParams.HasICache 595 def HasDcache = coreParams.HasDCache 596 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 597 def PAddrBitsMax = coreParams.PAddrBitsMax 598 def GPAddrBitsSv39x4 = coreParams.GPAddrBitsSv39x4 599 def GPAddrBitsSv48x4 = coreParams.GPAddrBitsSv48x4 600 def GPAddrBits = { 601 if (EnableSv48) 602 coreParams.GPAddrBitsSv48x4 603 else 604 coreParams.GPAddrBitsSv39x4 605 } 606 def VAddrBits = { 607 if (HasHExtension) { 608 if (EnableSv48) 609 coreParams.GPAddrBitsSv48x4 610 else 611 coreParams.GPAddrBitsSv39x4 612 } else { 613 if (EnableSv48) 614 coreParams.VAddrBitsSv48 615 else 616 coreParams.VAddrBitsSv39 617 } 618 } // VAddrBits is Virtual Memory addr bits 619 620 def VAddrMaxBits = { 621 if(EnableSv48) { 622 coreParams.VAddrBitsSv48 max coreParams.GPAddrBitsSv48x4 623 } else { 624 coreParams.VAddrBitsSv39 max coreParams.GPAddrBitsSv39x4 625 } 626 } 627 628 def AsidLength = coreParams.AsidLength 629 def VmidLength = coreParams.VmidLength 630 def ReSelectLen = coreParams.ReSelectLen 631 def AddrBytes = AddrBits / 8 // unused 632 def DataBits = XLEN 633 def DataBytes = DataBits / 8 634 def QuadWordBits = DataBits * 2 635 def QuadWordBytes = QuadWordBits / 8 636 def VDataBytes = VLEN / 8 637 def HasFPU = coreParams.HasFPU 638 def HasVPU = coreParams.HasVPU 639 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 640 def FetchWidth = coreParams.FetchWidth 641 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 642 def EnableBPU = coreParams.EnableBPU 643 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 644 def EnableRAS = coreParams.EnableRAS 645 def EnableLB = coreParams.EnableLB 646 def EnableLoop = coreParams.EnableLoop 647 def EnableSC = coreParams.EnableSC 648 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 649 def HistoryLength = coreParams.HistoryLength 650 def EnableGHistDiff = coreParams.EnableGHistDiff 651 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 652 def EnableClockGate = coreParams.EnableClockGate 653 def UbtbGHRLength = coreParams.UbtbGHRLength 654 def UbtbSize = coreParams.UbtbSize 655 def EnableFauFTB = coreParams.EnableFauFTB 656 def FtbSize = coreParams.FtbSize 657 def FtbWays = coreParams.FtbWays 658 def FtbTagLength = coreParams.FtbTagLength 659 def RasSize = coreParams.RasSize 660 def RasSpecSize = coreParams.RasSpecSize 661 def RasCtrSize = coreParams.RasCtrSize 662 663 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 664 coreParams.branchPredictor(resp_in, p) 665 } 666 def numBr = coreParams.numBr 667 def TageTableInfos = coreParams.TageTableInfos 668 def TageBanks = coreParams.numBr 669 def SCNRows = coreParams.SCNRows 670 def SCCtrBits = coreParams.SCCtrBits 671 def SCHistLens = coreParams.SCHistLens 672 def SCNTables = coreParams.SCNTables 673 674 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 675 case ((n, cb), h) => (n, cb, h) 676 } 677 def ITTageTableInfos = coreParams.ITTageTableInfos 678 type FoldedHistoryInfo = Tuple2[Int, Int] 679 def foldedGHistInfos = 680 (TageTableInfos.map{ case (nRows, h, t) => 681 if (h > 0) 682 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 683 else 684 Set[FoldedHistoryInfo]() 685 }.reduce(_++_).toSet ++ 686 SCTableInfos.map{ case (nRows, _, h) => 687 if (h > 0) 688 Set((h, min(log2Ceil(nRows/TageBanks), h))) 689 else 690 Set[FoldedHistoryInfo]() 691 }.reduce(_++_).toSet ++ 692 ITTageTableInfos.map{ case (nRows, h, t) => 693 if (h > 0) 694 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 695 else 696 Set[FoldedHistoryInfo]() 697 }.reduce(_++_) ++ 698 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 699 ).toList 700 701 702 703 def CacheLineSize = coreParams.CacheLineSize 704 def CacheLineHalfWord = CacheLineSize / 16 705 def ExtHistoryLength = HistoryLength + 64 706 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 707 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 708 def IBufSize = coreParams.IBufSize 709 def IBufNBank = coreParams.IBufNBank 710 def backendParams: BackendParams = coreParams.backendParams 711 def DecodeWidth = coreParams.DecodeWidth 712 def RenameWidth = coreParams.RenameWidth 713 def CommitWidth = coreParams.CommitWidth 714 def RobCommitWidth = coreParams.RobCommitWidth 715 def RabCommitWidth = coreParams.RabCommitWidth 716 def MaxUopSize = coreParams.MaxUopSize 717 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 718 def RenameSnapshotNum = coreParams.RenameSnapshotNum 719 def FtqSize = coreParams.FtqSize 720 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 721 def IntLogicRegs = coreParams.IntLogicRegs 722 def FpLogicRegs = coreParams.FpLogicRegs 723 def VecLogicRegs = coreParams.VecLogicRegs 724 def V0LogicRegs = coreParams.V0LogicRegs 725 def VlLogicRegs = coreParams.VlLogicRegs 726 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 727 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 728 def V0_IDX = coreParams.V0_IDX 729 def Vl_IDX = coreParams.Vl_IDX 730 def IntPhyRegs = coreParams.intPreg.numEntries 731 def FpPhyRegs = coreParams.fpPreg.numEntries 732 def VfPhyRegs = coreParams.vfPreg.numEntries 733 def V0PhyRegs = coreParams.v0Preg.numEntries 734 def VlPhyRegs = coreParams.vlPreg.numEntries 735 def MaxPhyRegs = Seq(IntPhyRegs, FpPhyRegs, VfPhyRegs, V0PhyRegs, VlPhyRegs).max 736 def IntPhyRegIdxWidth = log2Up(IntPhyRegs) 737 def FpPhyRegIdxWidth = log2Up(FpPhyRegs) 738 def VfPhyRegIdxWidth = log2Up(VfPhyRegs) 739 def V0PhyRegIdxWidth = log2Up(V0PhyRegs) 740 def VlPhyRegIdxWidth = log2Up(VlPhyRegs) 741 def PhyRegIdxWidth = Seq(IntPhyRegIdxWidth, FpPhyRegIdxWidth, VfPhyRegIdxWidth, V0PhyRegIdxWidth, VlPhyRegIdxWidth).max 742 def RobSize = coreParams.RobSize 743 def RabSize = coreParams.RabSize 744 def VTypeBufferSize = coreParams.VTypeBufferSize 745 def IntRegCacheSize = coreParams.IntRegCacheSize 746 def MemRegCacheSize = coreParams.MemRegCacheSize 747 def RegCacheSize = coreParams.RegCacheSize 748 def RegCacheIdxWidth = coreParams.RegCacheIdxWidth 749 /** 750 * the minimum element length of vector elements 751 */ 752 def minVecElen: Int = coreParams.minVecElen 753 754 /** 755 * the maximum number of elements in vector register 756 */ 757 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 758 759 def IntRefCounterWidth = log2Ceil(RobSize) 760 def LSQEnqWidth = RenameWidth 761 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 762 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 763 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 764 def LoadQueueRARSize = coreParams.LoadQueueRARSize 765 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 766 def RollbackGroupSize = coreParams.RollbackGroupSize 767 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 768 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 769 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 770 def StoreQueueSize = coreParams.StoreQueueSize 771 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 772 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 773 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 774 def VlsQueueSize = coreParams.VlsQueueSize 775 776 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 777 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 778 779 def NumRedirect = backendParams.numRedirect 780 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 781 def FtqRedirectAheadNum = NumRedirect 782 def IfuRedirectNum = coreParams.IfuRedirectNum 783 def LoadPipelineWidth = coreParams.LoadPipelineWidth 784 def StorePipelineWidth = coreParams.StorePipelineWidth 785 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 786 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 787 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 788 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 789 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 790 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 791 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 792 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 793 def StoreBufferSize = coreParams.StoreBufferSize 794 def StoreBufferThreshold = coreParams.StoreBufferThreshold 795 def EnsbufferWidth = coreParams.EnsbufferWidth 796 def LoadDependencyWidth = coreParams.LoadDependencyWidth 797 def VlMergeBufferSize = coreParams.VlMergeBufferSize 798 def VsMergeBufferSize = coreParams.VsMergeBufferSize 799 def UopWritebackWidth = coreParams.UopWritebackWidth 800 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 801 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 802 def VSegmentBufferSize = coreParams.VSegmentBufferSize 803 def VFOFBufferSize = coreParams.VFOFBufferSize 804 def UncacheBufferSize = coreParams.UncacheBufferSize 805 def UncacheBufferIndexWidth = log2Up(UncacheBufferSize) 806 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 807 def EnableFastForward = coreParams.EnableFastForward 808 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 809 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 810 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 811 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 812 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 813 def EnableHardwareStoreMisalign = coreParams.EnableHardwareStoreMisalign 814 def EnableHardwareLoadMisalign = coreParams.EnableHardwareLoadMisalign 815 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 816 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 817 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 818 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 819 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 820 def HasCMO = coreParams.HasCMO && p(EnableCHI) 821 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 822 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 823 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 824 def asidLen = coreParams.MMUAsidLen 825 def vmidLen = coreParams.MMUVmidLen 826 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 827 def refillBothTlb = coreParams.refillBothTlb 828 def iwpuParam = coreParams.iwpuParameters 829 def dwpuParam = coreParams.dwpuParameters 830 def itlbParams = coreParams.itlbParameters 831 def ldtlbParams = coreParams.ldtlbParameters 832 def sttlbParams = coreParams.sttlbParameters 833 def hytlbParams = coreParams.hytlbParameters 834 def pftlbParams = coreParams.pftlbParameters 835 def l2ToL1Params = coreParams.l2ToL1tlbParameters 836 def btlbParams = coreParams.btlbParameters 837 def l2tlbParams = coreParams.l2tlbParameters 838 def NumPerfCounters = coreParams.NumPerfCounters 839 840 def instBytes = if (HasCExtension) 2 else 4 841 def instOffsetBits = log2Ceil(instBytes) 842 843 def icacheParameters = coreParams.icacheParameters 844 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 845 846 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 847 // for constrained LR/SC loop 848 def LRSCCycles = 64 849 // for lr storm 850 def LRSCBackOff = 8 851 852 // cache hierarchy configurations 853 def l1BusDataWidth = 256 854 855 // load violation predict 856 def ResetTimeMax2Pow = 20 //1078576 857 def ResetTimeMin2Pow = 10 //1024 858 // wait table parameters 859 def WaitTableSize = 1024 860 def MemPredPCWidth = log2Up(WaitTableSize) 861 def LWTUse2BitCounter = true 862 // store set parameters 863 def SSITSize = WaitTableSize 864 def LFSTSize = 32 865 def SSIDWidth = log2Up(LFSTSize) 866 def LFSTWidth = 4 867 def StoreSetEnable = true // LWT will be disabled if SS is enabled 868 def LFSTEnable = true 869 870 def PCntIncrStep: Int = 6 871 def numPCntHc: Int = 12 872 def numPCntPtw: Int = 19 873 874 def numCSRPCntFrontend = 8 875 def numCSRPCntCtrl = 8 876 def numCSRPCntLsu = 8 877 def numCSRPCntHc = 5 878 def printEventCoding = true 879 def printCriticalError = false 880 def maxCommitStuck = pow(2, 21).toInt 881 882 // Vector load exception 883 def maxMergeNumPerCycle = 4 884 885 // Parameters for Sdtrig extension 886 protected def TriggerNum = 4 887 protected def TriggerChainMaxLength = 2 888 889 // Parameters for Trace extension 890 def TraceGroupNum = coreParams.traceParams.TraceGroupNum 891 def CauseWidth = XLEN 892 def TvalWidth = coreParams.traceParams.IaddrWidth 893 def PrivWidth = coreParams.traceParams.PrivWidth 894 def IaddrWidth = coreParams.traceParams.IaddrWidth 895 def ItypeWidth = coreParams.traceParams.ItypeWidth 896 def IretireWidthInPipe = log2Up(RenameWidth * 2) 897 def IretireWidthCompressed = log2Up(RenameWidth * CommitWidth * 2) 898 def IlastsizeWidth = coreParams.traceParams.IlastsizeWidth 899} 900