1package xiangshan.backend.datapath 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan._ 7import xiangshan.backend.Bundles.{ExuOutput, MemExuOutput} 8import xiangshan.backend.exu.ExeUnitParams 9import xiangshan.backend.fu.vector.{ByteMaskTailGen, Mgu, VldMgu, VecInfo} 10import xiangshan.mem.GenUSMaskRegVL 11import yunsuan.vector.SewOH 12 13class VldMergeUnit(val params: ExeUnitParams)(implicit p: Parameters) extends XSModule { 14 val io = IO(new VldMergeUnitIO(params)) 15 16 io.writeback.ready := io.writebackAfterMerge.ready 17 18 val wbReg = Reg(Valid(new ExuOutput(params))) 19 val mgu = Module(new VldMgu(VLEN)) 20 val vdAfterMerge = Wire(UInt(VLEN.W)) 21 22 val wbFire = !io.writeback.bits.robIdx.needFlush(io.flush) && io.writeback.fire 23 wbReg.bits := Mux(io.writeback.fire, io.writeback.bits, wbReg.bits) 24 wbReg.valid := wbFire 25 mgu.io.in.vd := wbReg.bits.data(0) 26 // oldVd is contained in data and is already masked with new data 27 mgu.io.in.oldVd := wbReg.bits.data(0) 28 mgu.io.in.mask := Mux(wbReg.bits.vls.get.vpu.vm, Fill(VLEN, 1.U(1.W)), wbReg.bits.vls.get.vpu.vmask) 29 mgu.io.in.info.valid := wbReg.valid 30 mgu.io.in.info.ta := wbReg.bits.vls.get.isMasked || wbReg.bits.vls.get.vpu.vta 31 mgu.io.in.info.ma := wbReg.bits.vls.get.vpu.vma 32 mgu.io.in.info.vl := wbReg.bits.vls.get.vpu.vl 33 mgu.io.in.info.vstart := wbReg.bits.vls.get.vpu.vstart 34 mgu.io.in.info.eew := wbReg.bits.vls.get.vpu.veew 35 mgu.io.in.info.vsew := wbReg.bits.vls.get.vpu.vsew 36 mgu.io.in.info.vdIdx := wbReg.bits.vls.get.vdIdxInField 37 mgu.io.in.info.vlmul := wbReg.bits.vls.get.vpu.vlmul 38 mgu.io.in.info.narrow := false.B // never narrow 39 mgu.io.in.info.dstMask := false.B // vlm need not mask 40 mgu.io.in.isIndexedVls := wbReg.bits.vls.get.isIndexed 41 42 //For the uop whose vl is modified by first-only-fault, the data written back can be used directly 43 vdAfterMerge := Mux(wbReg.bits.vlWen.getOrElse(false.B), wbReg.bits.data(0), mgu.io.out.vd) 44 45 io.writebackAfterMerge.valid := wbReg.valid 46 io.writebackAfterMerge.bits := wbReg.bits 47 io.writebackAfterMerge.bits.vecWen.foreach(_ := wbReg.bits.vecWen.get) 48 io.writebackAfterMerge.bits.v0Wen.foreach(_ := wbReg.bits.v0Wen.get) 49 io.writebackAfterMerge.bits.data := VecInit(Seq.fill(params.wbPathNum)(vdAfterMerge)) 50} 51 52class VldMergeUnitIO(param: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 53 val flush = Flipped(ValidIO(new Redirect)) 54 val writeback = Flipped(DecoupledIO(new ExuOutput(param))) 55 val writebackAfterMerge = DecoupledIO(new ExuOutput(param)) 56}