xref: /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala (revision c41f725a91c55e75c95c55b4bb0d2649f43e4c83) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:
9*          http://license.coscl.org.cn/MulanPSL2
10*
11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
14*
15* See the Mulan PSL v2 for more details.
16***************************************************************************************/
17
18package xiangshan.mem
19
20
21import org.chipsalliance.cde.config.Parameters
22import chisel3._
23import chisel3.util._
24import utility._
25import utils._
26import xiangshan._
27import xiangshan.backend.Bundles.{DynInst, MemExuInput}
28import xiangshan.backend.rob.RobPtr
29import xiangshan.cache._
30import xiangshan.backend.fu.FenceToSbuffer
31import xiangshan.cache.wpu.ReplayCarry
32import xiangshan.mem.prefetch.PrefetchReqBundle
33import math._
34
35object genWmask {
36  def apply(addr: UInt, sizeEncode: UInt): UInt = {
37    (LookupTree(sizeEncode, List(
38      "b00".U -> 0x1.U, //0001 << addr(2:0)
39      "b01".U -> 0x3.U, //0011
40      "b10".U -> 0xf.U, //1111
41      "b11".U -> 0xff.U //11111111
42    )) << addr(2, 0)).asUInt
43  }
44}
45
46object genVWmask {
47  def apply(addr: UInt, sizeEncode: UInt): UInt = {
48    (LookupTree(sizeEncode, List(
49      "b00".U -> 0x1.U, //0001 << addr(2:0)
50      "b01".U -> 0x3.U, //0011
51      "b10".U -> 0xf.U, //1111
52      "b11".U -> 0xff.U //11111111
53    )) << addr(3, 0)).asUInt
54  }
55}
56
57object genBasemask {
58  /**
59   *
60   * @param addr
61   * @param sizeEncode
62   * @return Return 16-byte aligned mask.
63   *
64   *         Example:
65   *         Address: 0x80000003 Encoding size: ‘b11
66   *         Return: 0xff
67   */
68  def apply(addr: UInt, sizeEncode: UInt): UInt = {
69    LookupTree(sizeEncode, List(
70      "b00".U -> 0x1.U,
71      "b01".U -> 0x3.U,
72      "b10".U -> 0xf.U,
73      "b11".U -> 0xff.U
74    ))
75  }
76}
77
78object shiftDataToLow {
79  def apply(addr: UInt, data : UInt): UInt = {
80    Mux(addr(3), (data >> 64).asUInt, data)
81  }
82}
83object shiftMaskToLow {
84  def apply(addr: UInt, mask: UInt): UInt = {
85    Mux(addr(3), (mask >> 8).asUInt, mask)
86  }
87}
88object shiftDataToHigh {
89  def apply(addr: UInt, data : UInt): UInt = {
90    Mux(addr(3), (data << 64).asUInt, data)
91  }
92}
93object shiftMaskToHigh {
94  def apply(addr: UInt, mask: UInt): UInt = {
95    Mux(addr(3), (mask << 8).asUInt, mask)
96  }
97}
98
99object AddPipelineReg {
100  class PipelineRegModule[T <: Data](gen: T) extends Module {
101    val io = IO(new Bundle() {
102      val in = Flipped(DecoupledIO(gen.cloneType))
103      val out = DecoupledIO(gen.cloneType)
104      val isFlush = Input(Bool())
105    })
106
107    val valid = RegInit(false.B)
108    valid.suggestName("pipeline_reg_valid")
109    when (io.out.fire) { valid := false.B }
110    when (io.in.fire) { valid := true.B }
111    when (io.isFlush) { valid := false.B }
112
113    io.in.ready := !valid || io.out.ready
114    io.out.bits := RegEnable(io.in.bits, io.in.fire)
115    io.out.valid := valid //&& !isFlush
116  }
117
118  def apply[T <: Data]
119  (left: DecoupledIO[T], right: DecoupledIO[T], isFlush: Bool,
120   moduleName: Option[String] = None
121  ): Unit = {
122    val pipelineReg = Module(new PipelineRegModule[T](left.bits.cloneType))
123    if(moduleName.nonEmpty) pipelineReg.suggestName(moduleName.get)
124    pipelineReg.io.in <> left
125    right <> pipelineReg.io.out
126    pipelineReg.io.isFlush := isFlush
127  }
128}
129