xref: /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala (revision 38d0d7c5a34a23dfdb58a3cb2737c3cfddb3ec9d) 
1package xiangshan.backend.fu.wrapper
2
3import chisel3._
4import chisel3.util._
5import org.chipsalliance.cde.config.Parameters
6import utility._
7import xiangshan._
8import xiangshan.backend.fu.NewCSR._
9import xiangshan.backend.fu.util._
10import xiangshan.backend.fu.{FuConfig, FuncUnit}
11import device._
12import system.HasSoCParameter
13import xiangshan.ExceptionNO._
14import xiangshan.backend.Bundles.TrapInstInfo
15import xiangshan.backend.decode.Imm_Z
16import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState
17import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode
18import xiangshan.frontend.FtqPtr
19
20class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg)
21  with HasCircularQueuePtrHelper with HasCriticalErrors
22{
23  val csrIn = io.csrio.get
24  val csrOut = io.csrio.get
25  val csrToDecode = io.csrToDecode.get
26
27  val setFsDirty = csrIn.fpu.dirty_fs
28  val setFflags = csrIn.fpu.fflags
29
30  val setVsDirty = csrIn.vpu.dirty_vs
31  val setVstart = csrIn.vpu.set_vstart
32  val setVtype = csrIn.vpu.set_vtype
33  val setVxsat = csrIn.vpu.set_vxsat
34  val vlFromPreg = csrIn.vpu.vl
35
36  val flushPipe = Wire(Bool())
37  val flush = io.flush.valid
38
39  /** Alias of input signals */
40  val (valid, src1, imm, func) = (
41    io.in.valid,
42    io.in.bits.data.src(0),
43    io.in.bits.data.imm(Imm_Z().len - 1, 0),
44    io.in.bits.ctrl.fuOpType
45  )
46
47  // split imm/src1/rd from IMM_Z: src1/rd for tval
48  val addr = Imm_Z().getCSRAddr(imm)
49  val rd   = Imm_Z().getRD(imm)
50  val rs1  = Imm_Z().getRS1(imm)
51  val imm5 = Imm_Z().getImm5(imm)
52  val csri = ZeroExt(imm5, XLEN)
53
54  import CSRConst._
55
56  private val isEcall  = CSROpType.isSystemOp(func) && addr === privEcall
57  private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak
58  private val isMNret  = CSROpType.isSystemOp(func) && addr === privMNret
59  private val isMret   = CSROpType.isSystemOp(func) && addr === privMret
60  private val isSret   = CSROpType.isSystemOp(func) && addr === privSret
61  private val isDret   = CSROpType.isSystemOp(func) && addr === privDret
62  private val isWfi    = CSROpType.isWfi(func)
63  private val isCSRAcc = CSROpType.isCsrAccess(func)
64
65  val csrMod = Module(new NewCSR)
66  val trapInstMod = Module(new TrapInstMod)
67  val trapTvalMod = Module(new TrapTvalMod)
68
69  private val privState = csrMod.io.status.privState
70  // The real reg value in CSR, with no read mask
71  private val regOut = csrMod.io.out.bits.regOut
72  private val src = Mux(CSROpType.needImm(func), csri, src1)
73  private val wdata = LookupTree(func, Seq(
74    CSROpType.wrt  -> src1,
75    CSROpType.set  -> (regOut | src1),
76    CSROpType.clr  -> (regOut & (~src1).asUInt),
77    CSROpType.wrti -> csri,
78    CSROpType.seti -> (regOut | csri),
79    CSROpType.clri -> (regOut & (~csri).asUInt),
80  ))
81
82  private val csrAccess = valid && CSROpType.isCsrAccess(func)
83  private val csrWen = valid && (
84    CSROpType.isCSRRW(func) ||
85    CSROpType.isCSRRSorRC(func) && rs1 =/= 0.U
86  )
87  private val csrRen = valid && (
88    CSROpType.isCSRRW(func) && rd =/= 0.U ||
89    CSROpType.isCSRRSorRC(func)
90  )
91
92  private val waddrReg = RegEnable(addr, 0.U(12.W), io.in.fire)
93  private val wdataReg = RegEnable(wdata, 0.U(64.W), io.in.fire)
94
95  csrMod.io.in match {
96    case in =>
97      in.valid := valid
98      in.bits.wen := csrWen
99      in.bits.ren := csrRen
100      in.bits.op  := CSROpType.getCSROp(func)
101      in.bits.addr := addr
102      in.bits.waddrReg := waddrReg
103      in.bits.src := src
104      in.bits.wdata := wdataReg
105      in.bits.mret := isMret
106      in.bits.mnret := isMNret
107      in.bits.sret := isSret
108      in.bits.dret := isDret
109  }
110  csrMod.io.trapInst := trapInstMod.io.currentTrapInst
111  csrMod.io.fetchMalTval := trapTvalMod.io.tval
112  csrMod.io.fromMem.excpVA  := csrIn.memExceptionVAddr
113  csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr
114  csrMod.io.fromMem.excpIsForVSnonLeafPTE := csrIn.memExceptionIsForVSnonLeafPTE
115
116  csrMod.io.fromRob.trap.valid := csrIn.exception.valid
117  csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc
118  csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr
119  csrMod.io.fromRob.trap.bits.pcGPA := csrIn.exception.bits.gpaddr
120  // Todo: shrink the width of trap vector.
121  // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle.
122  csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt
123  csrMod.io.fromRob.trap.bits.isFetchBkpt := csrIn.exception.bits.isPcBkpt
124  csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep
125  csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix
126  csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt
127  csrMod.io.fromRob.trap.bits.trigger := csrIn.exception.bits.trigger
128  csrMod.io.fromRob.trap.bits.isHls := csrIn.exception.bits.isHls
129  csrMod.io.fromRob.trap.bits.isFetchMalAddr := csrIn.exception.bits.isFetchMalAddr
130  csrMod.io.fromRob.trap.bits.isForVSnonLeafPTE := csrIn.exception.bits.isForVSnonLeafPTE
131
132  csrMod.io.fromRob.commit.fflags := setFflags
133  csrMod.io.fromRob.commit.fsDirty := setFsDirty
134  csrMod.io.fromRob.commit.vxsat.valid := setVxsat.valid
135  csrMod.io.fromRob.commit.vxsat.bits := setVxsat.bits
136  csrMod.io.fromRob.commit.vsDirty := setVsDirty
137  csrMod.io.fromRob.commit.vstart := setVstart
138  csrMod.io.fromRob.commit.vl := vlFromPreg
139  // Todo: correct vtype
140  csrMod.io.fromRob.commit.vtype.valid := setVtype.valid
141  csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1)
142  csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7)
143  csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6)
144  csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3)
145  csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0)
146
147  csrMod.io.fromRob.commit.instNum.valid := true.B  // Todo: valid control signal
148  csrMod.io.fromRob.commit.instNum.bits  := csrIn.perf.retiredInstr
149
150  csrMod.io.fromRob.robDeqPtr := csrIn.robDeqPtr
151
152  csrMod.io.fromVecExcpMod.busy := io.csrin.get.fromVecExcpMod.busy
153
154  csrMod.io.perf  := csrIn.perf
155
156  csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip
157  csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip
158  csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip
159  csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip
160  csrMod.platformIRP.STIP := false.B
161  csrMod.platformIRP.VSEIP := false.B // Todo
162  csrMod.platformIRP.VSTIP := false.B // Todo
163  csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug
164  csrMod.nonMaskableIRP.NMI_43 := csrIn.externalInterrupt.nmi.nmi_43
165  csrMod.nonMaskableIRP.NMI_31 := csrIn.externalInterrupt.nmi.nmi_31
166
167  csrMod.io.fromTop.hartId := io.csrin.get.hartId
168  csrMod.io.fromTop.clintTime := io.csrin.get.clintTime
169  csrMod.io.fromTop.criticalErrorState := io.csrin.get.criticalErrorState
170  private val csrModOutValid = csrMod.io.out.valid
171  private val csrModOut      = csrMod.io.out.bits
172
173  trapInstMod.io.fromDecode.trapInstInfo := RegNextWithEnable(io.csrin.get.trapInstInfo, hasInit = true)
174  trapInstMod.io.fromRob.flush.valid := io.flush.valid
175  trapInstMod.io.fromRob.flush.bits.ftqPtr := io.flush.bits.ftqIdx
176  trapInstMod.io.fromRob.flush.bits.ftqOffset := io.flush.bits.ftqOffset
177  trapInstMod.io.faultCsrUop.valid         := csrMod.io.out.valid && (csrMod.io.out.bits.EX_II || csrMod.io.out.bits.EX_VI)
178  trapInstMod.io.faultCsrUop.bits.fuOpType := DataHoldBypass(io.in.bits.ctrl.fuOpType, io.in.fire)
179  trapInstMod.io.faultCsrUop.bits.imm      := DataHoldBypass(io.in.bits.data.imm, io.in.fire)
180  trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqPtr    := DataHoldBypass(io.in.bits.ctrl.ftqIdx.get, io.in.fire)
181  trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqOffset := DataHoldBypass(io.in.bits.ctrl.ftqOffset.get, io.in.fire)
182  // Clear trap instruction when instruction fault trap(EX_II, EX_VI) occurs.
183  trapInstMod.io.readClear := (csrMod.io.fromRob.trap match {
184    case t =>
185      t.valid && !t.bits.isInterrupt && (t.bits.trapVec(EX_II) || t.bits.trapVec(EX_VI))
186  })
187
188  trapTvalMod.io.targetPc.valid := csrMod.io.out.bits.targetPcUpdate
189  trapTvalMod.io.targetPc.bits := csrMod.io.out.bits.targetPc
190  trapTvalMod.io.clear := csrIn.exception.valid && csrIn.exception.bits.isFetchMalAddr
191  trapTvalMod.io.fromCtrlBlock.flush := io.flush
192  trapTvalMod.io.fromCtrlBlock.robDeqPtr := io.csrio.get.robDeqPtr
193
194  private val imsic = Module(new IMSIC(NumVSIRFiles = 5, NumHart = 1, XLEN = 64, NumIRSrc = 256))
195  imsic.i.hartId := io.csrin.get.hartId
196  imsic.i.msiInfo := io.csrin.get.msiInfo
197  imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid
198  imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr
199  imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt
200  imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt
201  imsic.i.csr.vgein := csrMod.toAIA.vgein
202  imsic.i.csr.mClaim := csrMod.toAIA.mClaim
203  imsic.i.csr.sClaim := csrMod.toAIA.sClaim
204  imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim
205  imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid
206  imsic.i.csr.wdata.bits.op := csrMod.toAIA.wdata.bits.op
207  imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data
208
209  csrMod.fromAIA.rdata.valid        := imsic.o.csr.rdata.valid
210  csrMod.fromAIA.rdata.bits.data    := imsic.o.csr.rdata.bits.rdata
211  csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal
212  csrMod.fromAIA.meip    := imsic.o.meip
213  csrMod.fromAIA.seip    := imsic.o.seip
214  csrMod.fromAIA.vseip   := imsic.o.vseip
215  csrMod.fromAIA.mtopei  := imsic.o.mtopei
216  csrMod.fromAIA.stopei  := imsic.o.stopei
217  csrMod.fromAIA.vstopei := imsic.o.vstopei
218
219  private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo:
220
221  exceptionVec(EX_BP    ) := DataHoldBypass(isEbreak, false.B, io.in.fire)
222  exceptionVec(EX_MCALL ) := DataHoldBypass(isEcall && privState.isModeM, false.B, io.in.fire)
223  exceptionVec(EX_HSCALL) := DataHoldBypass(isEcall && privState.isModeHS, false.B, io.in.fire)
224  exceptionVec(EX_VSCALL) := DataHoldBypass(isEcall && privState.isModeVS, false.B, io.in.fire)
225  exceptionVec(EX_UCALL ) := DataHoldBypass(isEcall && privState.isModeHUorVU, false.B, io.in.fire)
226  exceptionVec(EX_II    ) := csrMod.io.out.bits.EX_II
227  exceptionVec(EX_VI    ) := csrMod.io.out.bits.EX_VI
228
229  val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak
230
231  flushPipe := csrMod.io.out.bits.flushPipe
232
233  // tlb
234  val tlb = Wire(new TlbCsrBundle)
235  tlb.satp.changed  := csrMod.io.tlb.satpASIDChanged
236  tlb.satp.mode     := csrMod.io.tlb.satp.MODE.asUInt
237  tlb.satp.asid     := csrMod.io.tlb.satp.ASID.asUInt
238  tlb.satp.ppn      := csrMod.io.tlb.satp.PPN.asUInt
239  tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged
240  tlb.vsatp.mode    := csrMod.io.tlb.vsatp.MODE.asUInt
241  tlb.vsatp.asid    := csrMod.io.tlb.vsatp.ASID.asUInt
242  tlb.vsatp.ppn     := csrMod.io.tlb.vsatp.PPN.asUInt
243  tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged
244  tlb.hgatp.mode    := csrMod.io.tlb.hgatp.MODE.asUInt
245  tlb.hgatp.vmid    := csrMod.io.tlb.hgatp.VMID.asUInt
246  tlb.hgatp.ppn     := csrMod.io.tlb.hgatp.PPN.asUInt
247
248  // expose several csr bits for tlb
249  tlb.priv.mxr := csrMod.io.tlb.mxr
250  tlb.priv.sum := csrMod.io.tlb.sum
251  tlb.priv.vmxr := csrMod.io.tlb.vmxr
252  tlb.priv.vsum := csrMod.io.tlb.vsum
253  tlb.priv.spvp := csrMod.io.tlb.spvp
254  tlb.priv.virt := csrMod.io.tlb.dvirt
255  tlb.priv.imode := csrMod.io.tlb.imode
256  tlb.priv.dmode := csrMod.io.tlb.dmode
257
258  // Svpbmt extension enable
259  tlb.mPBMTE := csrMod.io.tlb.mPBMTE
260  tlb.hPBMTE := csrMod.io.tlb.hPBMTE
261
262  // pointer masking extension
263  tlb.pmm := csrMod.io.tlb.pmm
264
265  /** Since some CSR read instructions are allowed to be pipelined, ready/valid signals should be modified */
266  io.in.ready := csrMod.io.in.ready // Todo: Async read imsic may block CSR
267  io.out.valid := csrModOutValid
268  io.out.bits.ctrl.exceptionVec.get := exceptionVec
269  io.out.bits.ctrl.flushPipe.get := flushPipe
270  io.out.bits.res.data := csrMod.io.out.bits.rData
271
272  /** initialize NewCSR's io_out_ready from wrapper's io */
273  csrMod.io.out.ready := io.out.ready
274
275  io.out.bits.res.redirect.get.valid := io.out.valid && RegEnable(isXRet, false.B, io.in.fire)
276  val redirect = io.out.bits.res.redirect.get.bits
277  redirect := 0.U.asTypeOf(redirect)
278  redirect.level := RedirectLevel.flushAfter
279  redirect.robIdx := RegEnable(io.in.bits.ctrl.robIdx, io.in.fire)
280  redirect.ftqIdx := RegEnable(io.in.bits.ctrl.ftqIdx.get, io.in.fire)
281  redirect.ftqOffset := RegEnable(io.in.bits.ctrl.ftqOffset.get, io.in.fire)
282  redirect.cfiUpdate.predTaken := true.B
283  redirect.cfiUpdate.taken := true.B
284  redirect.cfiUpdate.target := csrMod.io.out.bits.targetPc.pc
285  redirect.cfiUpdate.backendIPF := csrMod.io.out.bits.targetPc.raiseIPF
286  redirect.cfiUpdate.backendIAF := csrMod.io.out.bits.targetPc.raiseIAF
287  redirect.cfiUpdate.backendIGPF := csrMod.io.out.bits.targetPc.raiseIGPF
288  // Only mispred will send redirect to frontend
289  redirect.cfiUpdate.isMisPred := true.B
290
291  connectNonPipedCtrlSingal
292
293  override val criticalErrors = csrMod.getCriticalErrors
294  generateCriticalErrors()
295
296  // Todo: summerize all difftest skip condition
297  csrOut.isPerfCnt  := io.out.valid && csrMod.io.out.bits.isPerfCnt && RegEnable(func =/= CSROpType.jmp, false.B, io.in.fire)
298  csrOut.fpu.frm    := csrMod.io.status.fpState.frm.asUInt
299  csrOut.vpu.vstart := csrMod.io.status.vecState.vstart.asUInt
300  csrOut.vpu.vxrm   := csrMod.io.status.vecState.vxrm.asUInt
301
302  csrOut.isXRet := isXRet
303
304  csrOut.trapTarget := csrMod.io.out.bits.targetPc
305  csrOut.interrupt := csrMod.io.status.interrupt
306  csrOut.wfi_event := csrMod.io.status.wfiEvent
307
308  csrOut.tlb := tlb
309
310  csrOut.debugMode := csrMod.io.status.debugMode
311
312  csrOut.traceCSR := csrMod.io.status.traceCSR
313
314  csrOut.customCtrl match {
315    case custom =>
316      custom.l1I_pf_enable            := csrMod.io.status.custom.l1I_pf_enable
317      custom.l2_pf_enable             := csrMod.io.status.custom.l2_pf_enable
318      custom.l1D_pf_enable            := csrMod.io.status.custom.l1D_pf_enable
319      custom.l1D_pf_train_on_hit      := csrMod.io.status.custom.l1D_pf_train_on_hit
320      custom.l1D_pf_enable_agt        := csrMod.io.status.custom.l1D_pf_enable_agt
321      custom.l1D_pf_enable_pht        := csrMod.io.status.custom.l1D_pf_enable_pht
322      custom.l1D_pf_active_threshold  := csrMod.io.status.custom.l1D_pf_active_threshold
323      custom.l1D_pf_active_stride     := csrMod.io.status.custom.l1D_pf_active_stride
324      custom.l1D_pf_enable_stride     := csrMod.io.status.custom.l1D_pf_enable_stride
325      custom.l2_pf_store_only         := csrMod.io.status.custom.l2_pf_store_only
326      // ICache
327      custom.icache_parity_enable     := csrMod.io.status.custom.icache_parity_enable
328      // Load violation predictor
329      custom.lvpred_disable           := csrMod.io.status.custom.lvpred_disable
330      custom.no_spec_load             := csrMod.io.status.custom.no_spec_load
331      custom.storeset_wait_store      := csrMod.io.status.custom.storeset_wait_store
332      custom.storeset_no_fast_wakeup  := csrMod.io.status.custom.storeset_no_fast_wakeup
333      custom.lvpred_timeout           := csrMod.io.status.custom.lvpred_timeout
334      // Branch predictor
335      custom.bp_ctrl                  := csrMod.io.status.custom.bp_ctrl
336      // Memory Block
337      custom.sbuffer_threshold                := csrMod.io.status.custom.sbuffer_threshold
338      custom.ldld_vio_check_enable            := csrMod.io.status.custom.ldld_vio_check_enable
339      custom.soft_prefetch_enable             := csrMod.io.status.custom.soft_prefetch_enable
340      custom.cache_error_enable               := csrMod.io.status.custom.cache_error_enable
341      custom.uncache_write_outstanding_enable := csrMod.io.status.custom.uncache_write_outstanding_enable
342      custom.hd_misalign_st_enable            := csrMod.io.status.custom.hd_misalign_st_enable
343      custom.hd_misalign_ld_enable            := csrMod.io.status.custom.hd_misalign_ld_enable
344      // Rename
345      custom.fusion_enable            := csrMod.io.status.custom.fusion_enable
346      custom.wfi_enable               := csrMod.io.status.custom.wfi_enable
347      // distribute csr write signal
348      // write to frontend and memory
349      custom.distribute_csr.w.valid := csrMod.io.distributedWenLegal
350      custom.distribute_csr.w.bits.addr := waddrReg
351      custom.distribute_csr.w.bits.data := wdataReg
352      // rename single step
353      custom.singlestep := csrMod.io.status.singleStepFlag
354      // trigger
355      custom.frontend_trigger := csrMod.io.status.frontendTrigger
356      custom.mem_trigger      := csrMod.io.status.memTrigger
357      // virtual mode
358      custom.virtMode := csrMod.io.status.privState.V.asBool
359      // xstatus.fs field is off
360      custom.fsIsOff := csrMod.io.toDecode.illegalInst.fsIsOff
361  }
362
363  csrOut.instrAddrTransType := csrMod.io.status.instrAddrTransType
364  csrOut.criticalErrorState := csrMod.io.status.criticalErrorState
365
366  csrToDecode := csrMod.io.toDecode
367}
368
369class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{
370  val hartId = Input(UInt(8.W))
371  val msiInfo = Input(ValidIO(new MsiInfoBundle))
372  val criticalErrorState = Input(Bool())
373  val clintTime = Input(ValidIO(UInt(64.W)))
374  val trapInstInfo = Input(ValidIO(new TrapInstInfo))
375  val fromVecExcpMod = Input(new Bundle {
376    val busy = Bool()
377  })
378}
379
380class CSRToDecode(implicit p: Parameters) extends XSBundle {
381  val illegalInst = new Bundle {
382    /**
383     * illegal sfence.vma, sinval.vma
384     * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU
385     */
386    val sfenceVMA = Bool()
387
388    /**
389     * illegal sfence.w.inval sfence.inval.ir
390     * raise EX_II when isModeHU
391     */
392    val sfencePart = Bool()
393
394    /**
395     * illegal hfence.gvma, hinval.gvma
396     * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU
397     * the condition is the same as sfenceVMA
398     */
399    val hfenceGVMA = Bool()
400
401    /**
402     * illegal hfence.vvma, hinval.vvma
403     * raise EX_II when isModeHU
404     */
405    val hfenceVVMA = Bool()
406
407    /**
408     * illegal hlv, hlvx, and hsv
409     * raise EX_II when isModeHU && hstatus.HU=0
410     */
411    val hlsv = Bool()
412
413    /**
414     * decode all fp inst or all vecfp inst
415     * raise EX_II when FS=Off
416     */
417    val fsIsOff = Bool()
418
419    /**
420     * decode all vec inst
421     * raise EX_II when VS=Off
422     */
423    val vsIsOff = Bool()
424
425    /**
426     * illegal wfi
427     * raise EX_II when isModeHU || !isModeM && mstatus.TW=1
428     */
429    val wfi = Bool()
430
431    /**
432     * frm reserved
433     * raise EX_II when frm.data > 4
434     */
435    val frm = Bool()
436
437    /**
438     * illegal CBO.ZERO
439     * raise [[EX_II]] when !isModeM && !MEnvCfg.CBZE || isModeHU && !SEnvCfg.CBZE
440     */
441    val cboZ = Bool()
442
443    /**
444     * illegal CBO.CLEAN/FLUSH
445     * raise [[EX_II]] when !isModeM && !MEnvCfg.CBCFE || isModeHU && !SEnvCfg.CBCFE
446     */
447    val cboCF = Bool()
448
449    /**
450     * illegal CBO.INVAL
451     * raise [[EX_II]] when !isModeM && MEnvCfg.CBIE = EnvCBIE.Off || isModeHU && SEnvCfg.CBIE = EnvCBIE.Off
452     */
453    val cboI = Bool()
454  }
455
456  val virtualInst = new Bundle {
457    /**
458     * illegal sfence.vma, svinval.vma
459     * raise EX_VI when isModeVS && hstatus.VTVM=1 || isModeVU
460     */
461    val sfenceVMA = Bool()
462
463    /**
464     * illegal sfence.w.inval sfence.inval.ir
465     * raise EX_VI when isModeVU
466     */
467    val sfencePart = Bool()
468
469    /**
470     * illegal hfence.gvma, hinval.gvma, hfence.vvma, hinval.vvma
471     * raise EX_VI when isModeVS || isModeVU
472     */
473    val hfence = Bool()
474
475    /**
476     * illegal hlv, hlvx, and hsv
477     * raise EX_VI when isModeVS || isModeVU
478     */
479    val hlsv = Bool()
480
481    /**
482     * illegal wfi
483     * raise EX_VI when isModeVU && mstatus.TW=0 || isModeVS && mstatus.TW=0 && hstatus.VTW=1
484     */
485    val wfi = Bool()
486
487    /**
488     * illegal CBO.ZERO
489     * raise [[EX_VI]] when MEnvCfg.CBZE && (isModeVS && !HEnvCfg.CBZE || isModeVU && (!HEnvCfg.CBZE || !SEnvCfg.CBZE))
490     */
491    val cboZ = Bool()
492
493    /**
494     * illegal CBO.CLEAN/FLUSH
495     * raise [[EX_VI]] when MEnvCfg.CBZE && (isModeVS && !HEnvCfg.CBCFE || isModeVU && (!HEnvCfg.CBCFE || !SEnvCfg.CBCFE))
496     */
497    val cboCF = Bool()
498
499    /**
500     * illegal CBO.INVAL <br/>
501     * raise [[EX_VI]] when MEnvCfg.CBIE =/= EnvCBIE.Off && ( <br/>
502     *   isModeVS && HEnvCfg.CBIE === EnvCBIE.Off || <br/>
503     *   isModeVU && (HEnvCfg.CBIE === EnvCBIE.Off || SEnvCfg.CBIE === EnvCBIE.Off) <br/>
504     * ) <br/>
505     */
506    val cboI = Bool()
507  }
508
509  val special = new Bundle {
510    /**
511     * execute CBO.INVAL and perform flush operation when <br/>
512     * isModeHS && MEnvCfg.CBIE === EnvCBIE.Flush || <br/>
513     * isModeHU && (MEnvCfg.CBIE === EnvCBIE.Flush || SEnvCfg.CBIE === EnvCBIE.Flush) <br/>
514     * isModeVS && (MEnvCfg.CBIE === EnvCBIE.Flush || HEnvCfg.CBIE === EnvCBIE.Flush) <br/>
515     * isModeVU && (MEnvCfg.CBIE === EnvCBIE.Flush || HEnvCfg.CBIE === EnvCBIE.Flush || SEnvCfg.CBIE === EnvCBIE.Flush) <br/>
516     */
517    val cboI2F = Bool()
518  }
519}