1package xiangshan.backend.fu.fpu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan._ 7import xiangshan.backend.fu.{FuConfig, FuncUnit, HasPipelineReg} 8 9trait FpFuncUnitAlias { this: FuncUnit => 10 protected val inCtrl = io.in.bits.ctrl 11 protected val inData = io.in.bits.data 12 protected val fp_fmt = inCtrl.fpu.get.fmt 13 14 protected val frm = io.frm.getOrElse(0.U(3.W)) 15 protected val instRm = inCtrl.fpu.getOrElse(0.U.asTypeOf(new FPUCtrlSignals)).rm 16 protected val rm = Mux(instRm =/= "b111".U, instRm, frm) 17 18 protected val fuOpType = inCtrl.fuOpType 19} 20 21class FpPipedFuncUnit(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 22 with HasPipelineReg 23 with FpFuncUnitAlias 24{ 25 protected val outCtrl = ctrlVec.last 26 protected val outData = dataVec.last 27 28 override def latency: Int = cfg.latency.latencyVal.get 29 30} 31