xref: /XiangShan/src/main/scala/system/SoC.scala (revision e836c7705c53f8360816d56db7f6d37725aad2a6) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import org.chipsalliance.cde.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import device.{DebugModule, TLPMA, TLPMAIO}
23import freechips.rocketchip.amba.axi4._
24import freechips.rocketchip.devices.debug.DebugModuleKey
25import freechips.rocketchip.devices.tilelink._
26import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
27import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
28import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
29import freechips.rocketchip.tilelink._
30import freechips.rocketchip.util.AsyncQueueParams
31import huancun._
32import top.BusPerfMonitor
33import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger}
34import xiangshan.backend.fu.{MemoryRange, PMAConfigEntry, PMAConst}
35import xiangshan.{DebugOptionsKey, PMParameKey, XSTileKey}
36import coupledL2.{EnableCHI, L2Param}
37import coupledL2.tl2chi.CHIIssue
38import openLLC.OpenLLCParam
39
40case object SoCParamsKey extends Field[SoCParameters]
41
42case class SoCParameters
43(
44  EnableILA: Boolean = false,
45  PAddrBits: Int = 48,
46  PmemRanges: Seq[MemoryRange] = Seq(MemoryRange(0x80000000L, 0x80000000000L)),
47  PMAConfigs: Seq[PMAConfigEntry] = Seq(
48    PMAConfigEntry(0x0L, range = 0x1000000000000L, a = 3),
49    PMAConfigEntry(0x80000000000L, c = true, atomic = true, a = 1, x = true, w = true, r = true),
50    PMAConfigEntry(0x80000000L, a = 1, w = true, r = true),
51    PMAConfigEntry(0x3A000000L, a = 1),
52    PMAConfigEntry(0x38022000L, a = 1, w = true, r = true),
53    PMAConfigEntry(0x38021000L, a = 1, x = true, w = true, r = true),
54    PMAConfigEntry(0x38020000L, a = 1, w = true, r = true),
55    PMAConfigEntry(0x30050000L, a = 1, w = true, r = true), // FIXME: GPU space is cacheable?
56    PMAConfigEntry(0x30010000L, a = 1, w = true, r = true),
57    PMAConfigEntry(0x20000000L, a = 1, x = true, w = true, r = true),
58    PMAConfigEntry(0x10000000L, a = 1, w = true, r = true),
59    PMAConfigEntry(0)
60  ),
61  CLINTRange: AddressSet = AddressSet(0x38000000L, CLINTConsts.size - 1),
62  BEURange: AddressSet = AddressSet(0x38010000L, 0xfff),
63  PLICRange: AddressSet = AddressSet(0x3c000000L, PLICConsts.size(PLICConsts.maxMaxHarts) - 1),
64  PLLRange: AddressSet = AddressSet(0x3a000000L, 0xfff),
65  UARTLiteForDTS: Boolean = true, // should be false in SimMMIO
66  extIntrs: Int = 64,
67  L3NBanks: Int = 4,
68  L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
69    name = "L3",
70    level = 3,
71    ways = 8,
72    sets = 2048 // 1MB per bank
73  )),
74  OpenLLCParamsOpt: Option[OpenLLCParam] = Some(OpenLLCParam(
75    name = "LLC",
76    ways = 8,
77    sets = 2048,
78    banks = 4,
79    clientCaches = Seq(L2Param())
80  )),
81  XSTopPrefix: Option[String] = None,
82  NodeIDWidthList: Map[String, Int] = Map(
83    "B" -> 7,
84    "E.b" -> 11
85  ),
86  NumHart: Int = 64,
87  NumIRFiles: Int = 7,
88  NumIRSrc: Int = 256,
89  UseXSNoCTop: Boolean = false,
90  IMSICUseTL: Boolean = false,
91  EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 16, sync = 3, safe = false)),
92  EnableClintAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false))
93){
94  // L3 configurations
95  val L3InnerBusWidth = 256
96  val L3BlockSize = 64
97  // on chip network configurations
98  val L3OuterBusWidth = 256
99  val UARTLiteRange = AddressSet(0x40600000, if (UARTLiteForDTS) 0x3f else 0xf)
100}
101
102trait HasSoCParameter {
103  implicit val p: Parameters
104
105  val soc = p(SoCParamsKey)
106  val debugOpts = p(DebugOptionsKey)
107  val tiles = p(XSTileKey)
108  val enableCHI = p(EnableCHI)
109  val issue = p(CHIIssue)
110
111  val NumCores = tiles.size
112  val EnableILA = soc.EnableILA
113
114  // Parameters for trace extension
115  val TraceTraceGroupNum          = tiles.head.traceParams.TraceGroupNum
116  val TraceCauseWidth             = tiles.head.XLEN
117  val TraceTvalWidth              = tiles.head.traceParams.IaddrWidth
118  val TracePrivWidth              = tiles.head.traceParams.PrivWidth
119  val TraceIaddrWidth             = tiles.head.traceParams.IaddrWidth
120  val TraceItypeWidth             = tiles.head.traceParams.ItypeWidth
121  val TraceIretireWidthCompressed = log2Up(tiles.head.RenameWidth * tiles.head.CommitWidth * 2)
122  val TraceIlastsizeWidth         = tiles.head.traceParams.IlastsizeWidth
123
124  // L3 configurations
125  val L3InnerBusWidth = soc.L3InnerBusWidth
126  val L3BlockSize = soc.L3BlockSize
127  val L3NBanks = soc.L3NBanks
128
129  // on chip network configurations
130  val L3OuterBusWidth = soc.L3OuterBusWidth
131
132  val NrExtIntr = soc.extIntrs
133
134  val SetIpNumValidSize = soc.NumHart * soc.NumIRFiles
135
136  val NumIRSrc = soc.NumIRSrc
137
138  val EnableCHIAsyncBridge = if (enableCHI && soc.EnableCHIAsyncBridge.isDefined)
139    soc.EnableCHIAsyncBridge else None
140  val EnableClintAsyncBridge = soc.EnableClintAsyncBridge
141}
142
143trait HasPeripheralRanges {
144  implicit val p: Parameters
145
146  private def soc = p(SoCParamsKey)
147  private def dm = p(DebugModuleKey)
148  private def pmParams = p(PMParameKey)
149
150  private def mmpma = pmParams.mmpma
151
152  def onChipPeripheralRanges: Map[String, AddressSet] = Map(
153    "CLINT" -> soc.CLINTRange,
154    "BEU"   -> soc.BEURange,
155    "PLIC"  -> soc.PLICRange,
156    "PLL"   -> soc.PLLRange,
157    "UART"  -> soc.UARTLiteRange,
158    "DEBUG" -> dm.get.address,
159    "MMPMA" -> AddressSet(mmpma.address, mmpma.mask)
160  ) ++ (
161    if (soc.L3CacheParamsOpt.map(_.ctrl.isDefined).getOrElse(false))
162      Map("L3CTL" -> AddressSet(soc.L3CacheParamsOpt.get.ctrl.get.address, 0xffff))
163    else
164      Map()
165  )
166
167  def peripheralRange = onChipPeripheralRanges.values.foldLeft(Seq(AddressSet(0x0, 0x7fffffffL))) { (acc, x) =>
168    acc.flatMap(_.subtract(x))
169  }
170}
171
172class ILABundle extends Bundle {}
173
174
175abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter with HasPeripheralRanges {
176  val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize))
177  val peripheralXbar = Option.when(!enableCHI)(TLXbar())
178  val l3_xbar = Option.when(!enableCHI)(TLXbar())
179  val l3_banked_xbar = Option.when(!enableCHI)(TLXbar())
180
181  val soc_xbar = Option.when(enableCHI)(AXI4Xbar())
182}
183
184// We adapt the following three traits from rocket-chip.
185// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
186trait HaveSlaveAXI4Port {
187  this: BaseSoC =>
188
189  val idBits = 14
190
191  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
192    Seq(AXI4MasterParameters(
193      name = "dma",
194      id = IdRange(0, 1 << idBits)
195    ))
196  )))
197
198  if (l3_xbar.isDefined) {
199    val errorDevice = LazyModule(new TLError(
200      params = DevNullParams(
201        address = Seq(AddressSet(0x0, 0x7fffffffL)),
202        maxAtomic = 8,
203        maxTransfer = 64),
204      beatBytes = L3InnerBusWidth / 8
205    ))
206    errorDevice.node :=
207      l3_xbar.get :=
208      TLFIFOFixer() :=
209      TLWidthWidget(32) :=
210      AXI4ToTL() :=
211      AXI4UserYanker(Some(1)) :=
212      AXI4Fragmenter() :=
213      AXI4Buffer() :=
214      AXI4Buffer() :=
215      AXI4IdIndexer(1) :=
216      l3FrontendAXI4Node
217  }
218
219  val dma = InModuleBody {
220    l3FrontendAXI4Node.makeIOs()
221  }
222}
223
224trait HaveAXI4MemPort {
225  this: BaseSoC =>
226  val device = new MemoryDevice
227  // 48-bit physical address
228  val memRange = AddressSet(0x00000000L, 0xffffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
229  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
230    AXI4SlavePortParameters(
231      slaves = Seq(
232        AXI4SlaveParameters(
233          address = memRange,
234          regionType = RegionType.UNCACHED,
235          executable = true,
236          supportsRead = TransferSizes(1, L3BlockSize),
237          supportsWrite = TransferSizes(1, L3BlockSize),
238          interleavedId = Some(0),
239          resources = device.reg("mem")
240        )
241      ),
242      beatBytes = L3OuterBusWidth / 8,
243      requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey),
244    )
245  ))
246
247  val mem_xbar = TLXbar()
248  val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
249  val axi4mem_node = AXI4IdentityNode()
250
251  if (enableCHI) {
252    axi4mem_node :=
253      soc_xbar.get
254  } else {
255    mem_xbar :=*
256      TLBuffer.chainNode(2) :=
257      TLCacheCork() :=
258      l3_mem_pmu :=
259      TLClientsMerger() :=
260      TLXbar() :=*
261      bankedNode.get
262
263    mem_xbar :=
264      TLWidthWidget(8) :=
265      TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
266      peripheralXbar.get
267
268    axi4mem_node :=
269      TLToAXI4() :=
270      TLSourceShrinker(64) :=
271      TLWidthWidget(L3OuterBusWidth / 8) :=
272      TLBuffer.chainNode(2) :=
273      mem_xbar
274  }
275
276  memAXI4SlaveNode :=
277    AXI4Buffer() :=
278    AXI4Buffer() :=
279    AXI4Buffer() :=
280    AXI4IdIndexer(idBits = 14) :=
281    AXI4UserYanker() :=
282    AXI4Deinterleaver(L3BlockSize) :=
283    axi4mem_node
284
285  val memory = InModuleBody {
286    memAXI4SlaveNode.makeIOs()
287  }
288}
289
290trait HaveAXI4PeripheralPort { this: BaseSoC =>
291  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
292  val uartParams = AXI4SlaveParameters(
293    address = Seq(soc.UARTLiteRange),
294    regionType = RegionType.UNCACHED,
295    supportsRead = TransferSizes(1, 32),
296    supportsWrite = TransferSizes(1, 32),
297    resources = uartDevice.reg
298  )
299  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
300    Seq(AXI4SlaveParameters(
301      address = peripheralRange,
302      regionType = RegionType.UNCACHED,
303      supportsRead = TransferSizes(1, 32),
304      supportsWrite = TransferSizes(1, 32),
305      interleavedId = Some(0)
306    ), uartParams),
307    beatBytes = 8
308  )))
309
310  val axi4peripheral_node = AXI4IdentityNode()
311  val error_xbar = Option.when(enableCHI)(TLXbar())
312
313  peripheralNode :=
314    AXI4UserYanker() :=
315    AXI4IdIndexer(idBits = 2) :=
316    AXI4Buffer() :=
317    AXI4Buffer() :=
318    AXI4Buffer() :=
319    AXI4Buffer() :=
320    AXI4UserYanker() :=
321    // AXI4Deinterleaver(8) :=
322    axi4peripheral_node
323
324  if (enableCHI) {
325    val error = LazyModule(new TLError(
326      params = DevNullParams(
327        address = Seq(AddressSet(0x1000000000000L, 0xffffffffffffL)),
328        maxAtomic = 8,
329        maxTransfer = 64),
330      beatBytes = 8
331    ))
332    error.node := error_xbar.get
333    axi4peripheral_node :=
334      AXI4Deinterleaver(8) :=
335      TLToAXI4() :=
336      error_xbar.get :=
337      TLBuffer.chainNode(2, Some("llc_to_peripheral_buffer")) :=
338      TLFIFOFixer() :=
339      TLWidthWidget(L3OuterBusWidth / 8) :=
340      AXI4ToTL() :=
341      AXI4UserYanker() :=
342      soc_xbar.get
343  } else {
344    axi4peripheral_node :=
345      AXI4Deinterleaver(8) :=
346      TLToAXI4() :=
347      TLBuffer.chainNode(3) :=
348      peripheralXbar.get
349  }
350
351  val peripheral = InModuleBody {
352    peripheralNode.makeIOs()
353  }
354
355}
356
357class MemMisc()(implicit p: Parameters) extends BaseSoC
358  with HaveAXI4MemPort
359  with PMAConst
360  with HaveAXI4PeripheralPort
361{
362
363  val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
364  val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
365
366  val l3_in = TLTempNode()
367  val l3_out = TLTempNode()
368
369  val device_xbar = Option.when(enableCHI)(TLXbar())
370  device_xbar.foreach(_ := error_xbar.get)
371
372  if (l3_banked_xbar.isDefined) {
373    l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar.get
374    l3_banked_xbar.get := TLBuffer.chainNode(2) := l3_xbar.get
375  }
376  bankedNode match {
377    case Some(bankBinder) =>
378      bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out
379    case None =>
380  }
381
382  if(soc.L3CacheParamsOpt.isEmpty){
383    l3_out :*= l3_in
384  }
385
386  if (!enableCHI) {
387    for (port <- peripheral_ports.get) {
388      peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port
389    }
390  }
391
392  core_to_l3_ports.foreach { case _ =>
393    for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){
394      l3_banked_xbar.get :=*
395        TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=*
396        TLBuffer() :=
397        core_out
398    }
399  }
400
401  val clint = LazyModule(new CLINT(CLINTParams(soc.CLINTRange.base), 8))
402  if (enableCHI) { clint.node := device_xbar.get }
403  else { clint.node := peripheralXbar.get }
404
405  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
406    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
407    class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
408      val in = IO(Input(Vec(num, Bool())))
409      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
410    }
411    lazy val module = new IntSourceNodeToModuleImp(this)
412  }
413
414  val plic = LazyModule(new TLPLIC(PLICParams(soc.PLICRange.base), 8))
415  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
416
417  plic.intnode := plicSource.sourceNode
418  if (enableCHI) { plic.node := device_xbar.get }
419  else { plic.node := peripheralXbar.get }
420
421  val pll_node = TLRegisterNode(
422    address = Seq(soc.PLLRange),
423    device = new SimpleDevice("pll_ctrl", Seq()),
424    beatBytes = 8,
425    concurrency = 1
426  )
427  if (enableCHI) { pll_node := device_xbar.get }
428  else { pll_node := peripheralXbar.get }
429
430  val debugModule = LazyModule(new DebugModule(NumCores)(p))
431  if (enableCHI) {
432    debugModule.debug.node := device_xbar.get
433    // TODO: l3_xbar
434    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
435      error_xbar.get := sb2tl.node
436    }
437  } else {
438    debugModule.debug.node := peripheralXbar.get
439    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
440      l3_xbar.get := TLBuffer() := TLWidthWidget(1) := sb2tl.node
441    }
442  }
443
444  val pma = LazyModule(new TLPMA)
445  if (enableCHI) {
446    pma.node := TLBuffer.chainNode(4) := device_xbar.get
447  } else {
448    pma.node := TLBuffer.chainNode(4) := peripheralXbar.get
449  }
450
451  class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
452
453    val debug_module_io = IO(new debugModule.DebugModuleIO)
454    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
455    val rtc_clock = IO(Input(Bool()))
456    val pll0_lock = IO(Input(Bool()))
457    val pll0_ctrl = IO(Output(Vec(6, UInt(32.W))))
458    val cacheable_check = IO(new TLPMAIO)
459    val clintTime = IO(Output(ValidIO(UInt(64.W))))
460
461    debugModule.module.io <> debug_module_io
462
463    // sync external interrupts
464    require(plicSource.module.in.length == ext_intrs.getWidth)
465    for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) {
466      val ext_intr_sync = RegInit(0.U(3.W))
467      ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt)
468      plic_in := ext_intr_sync(2)
469    }
470
471    pma.module.io <> cacheable_check
472
473    // positive edge sampling of the lower-speed rtc_clock
474    val rtcTick = RegInit(0.U(3.W))
475    rtcTick := Cat(rtcTick(1, 0), rtc_clock)
476    clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2)
477
478    val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) }
479    val pll_lock = RegNext(next = pll0_lock, init = false.B)
480
481    clintTime := clint.module.io.time
482
483    pll0_ctrl <> VecInit(pll_ctrl_regs)
484
485    pll_node.regmap(
486      0x000 -> RegFieldGroup(
487        "Pll", Some("PLL ctrl regs"),
488        pll_ctrl_regs.zipWithIndex.map{
489          case (r, i) => RegField(32, r, RegFieldDesc(
490            s"PLL_ctrl_$i",
491            desc = s"PLL ctrl register #$i"
492          ))
493        } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc(
494          "PLL_lock",
495          "PLL lock register"
496        ))
497      )
498    )
499  }
500
501  lazy val module = new SoCMiscImp(this)
502}
503
504class SoCMisc()(implicit p: Parameters) extends MemMisc
505  with HaveSlaveAXI4Port
506
507