1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import coupledL2.PrefetchCtrlFromCore 24import device.MsiInfoBundle 25import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp} 26import freechips.rocketchip.tile.HasFPUParameters 27import system.HasSoCParameter 28import utils._ 29import utility._ 30import xiangshan.frontend._ 31import xiangshan.backend._ 32import xiangshan.backend.fu.PMPRespBundle 33import xiangshan.backend.trace.TraceCoreInterface 34import xiangshan.mem._ 35import xiangshan.cache.mmu._ 36import xiangshan.cache.mmu.TlbRequestIO 37import scala.collection.mutable.ListBuffer 38 39abstract class XSModule(implicit val p: Parameters) extends Module 40 with HasXSParameter 41 with HasFPUParameters 42 43//remove this trait after impl module logic 44trait NeedImpl { 45 this: RawModule => 46 protected def IO[T <: Data](iodef: T): T = { 47 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 48 val io = chisel3.IO(iodef) 49 io <> DontCare 50 io 51 } 52} 53 54abstract class XSBundle(implicit val p: Parameters) extends Bundle 55 with HasXSParameter 56 57abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule 58 with HasXSParameter 59{ 60 override def shouldBeInlined: Boolean = false 61 // outer facing nodes 62 val frontend = LazyModule(new Frontend()) 63 val csrOut = BundleBridgeSource(Some(() => new DistributedCSRIO())) 64 val backend = LazyModule(new Backend(backendParams)) 65 66 val memBlock = LazyModule(new MemBlock) 67 68 memBlock.inner.frontendBridge.icache_node := frontend.inner.icache.clientNode 69 memBlock.inner.frontendBridge.instr_uncache_node := frontend.inner.instrUncache.clientNode 70 if (icacheParameters.cacheCtrlAddressOpt.nonEmpty) { 71 frontend.inner.icache.ctrlUnitOpt.get.node := memBlock.inner.frontendBridge.icachectrl_node 72 } 73} 74 75class XSCore()(implicit p: config.Parameters) extends XSCoreBase 76 with HasXSDts 77{ 78 lazy val module = new XSCoreImp(this) 79} 80 81class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) 82 with HasXSParameter 83 with HasSoCParameter { 84 val io = IO(new Bundle { 85 val hartId = Input(UInt(hartIdLen.W)) 86 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 87 val clintTime = Input(ValidIO(UInt(64.W))) 88 val reset_vector = Input(UInt(PAddrBits.W)) 89 val cpu_halt = Output(Bool()) 90 val l2_flush_done = Input(Bool()) 91 val l2_flush_en = Output(Bool()) 92 val power_down_en = Output(Bool()) 93 val cpu_critical_error = Output(Bool()) 94 val resetInFrontend = Output(Bool()) 95 val traceCoreInterface = new TraceCoreInterface 96 val l2PfCtrl = Output(new PrefetchCtrlFromCore) 97 val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent)) 98 val beu_errors = Output(new XSL1BusErrors()) 99 val l2_hint = Input(Valid(new L2ToL1Hint())) 100 val l2_tlb_req = Flipped(new TlbRequestIO(nRespDups = 2)) 101 val l2_pmp_resp = new PMPRespBundle 102 val l2PfqBusy = Input(Bool()) 103 val debugTopDown = new Bundle { 104 val robTrueCommit = Output(UInt(64.W)) 105 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 106 val l2MissMatch = Input(Bool()) 107 val l3MissMatch = Input(Bool()) 108 } 109 val topDownInfo = Input(new Bundle { 110 val l2Miss = Bool() 111 val l3Miss = Bool() 112 }) 113 }) 114 115 dontTouch(io.l2_flush_done) 116 dontTouch(io.l2_flush_en) 117 dontTouch(io.power_down_en) 118 119 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 120 121 val frontend = outer.frontend.module 122 val backend = outer.backend.module 123 val memBlock = outer.memBlock.module 124 125 frontend.io.hartId := memBlock.io.inner_hartId 126 frontend.io.reset_vector := memBlock.io.inner_reset_vector 127 frontend.io.softPrefetch <> memBlock.io.ifetchPrefetch 128 frontend.io.backend <> backend.io.frontend 129 frontend.io.sfence <> backend.io.frontendSfence 130 frontend.io.tlbCsr <> backend.io.frontendTlbCsr 131 frontend.io.csrCtrl <> backend.io.frontendCsrCtrl 132 frontend.io.fencei <> backend.io.fenceio.fencei 133 134 backend.io.fromTop := memBlock.io.mem_to_ooo.topToBackendBypass 135 136 require(backend.io.mem.stIn.length == memBlock.io.mem_to_ooo.stIn.length) 137 backend.io.mem.stIn.zip(memBlock.io.mem_to_ooo.stIn).foreach { case (sink, source) => 138 sink.valid := source.valid 139 sink.bits := 0.U.asTypeOf(sink.bits) 140 sink.bits.robIdx := source.bits.uop.robIdx 141 sink.bits.ssid := source.bits.uop.ssid 142 sink.bits.storeSetHit := source.bits.uop.storeSetHit 143 // The other signals have not been used 144 } 145 backend.io.mem.memoryViolation := memBlock.io.mem_to_ooo.memoryViolation 146 backend.io.mem.lsqEnqIO <> memBlock.io.ooo_to_mem.enqLsq 147 backend.io.mem.sqDeq := memBlock.io.mem_to_ooo.sqDeq 148 backend.io.mem.lqDeq := memBlock.io.mem_to_ooo.lqDeq 149 backend.io.mem.sqDeqPtr := memBlock.io.mem_to_ooo.sqDeqPtr 150 backend.io.mem.lqDeqPtr := memBlock.io.mem_to_ooo.lqDeqPtr 151 backend.io.mem.lqCancelCnt := memBlock.io.mem_to_ooo.lqCancelCnt 152 backend.io.mem.sqCancelCnt := memBlock.io.mem_to_ooo.sqCancelCnt 153 backend.io.mem.otherFastWakeup := memBlock.io.mem_to_ooo.otherFastWakeup 154 backend.io.mem.stIssuePtr := memBlock.io.mem_to_ooo.stIssuePtr 155 backend.io.mem.ldaIqFeedback := memBlock.io.mem_to_ooo.ldaIqFeedback 156 backend.io.mem.staIqFeedback := memBlock.io.mem_to_ooo.staIqFeedback 157 backend.io.mem.hyuIqFeedback := memBlock.io.mem_to_ooo.hyuIqFeedback 158 backend.io.mem.vstuIqFeedback := memBlock.io.mem_to_ooo.vstuIqFeedback 159 backend.io.mem.vlduIqFeedback := memBlock.io.mem_to_ooo.vlduIqFeedback 160 backend.io.mem.ldCancel := memBlock.io.mem_to_ooo.ldCancel 161 backend.io.mem.wakeup := memBlock.io.mem_to_ooo.wakeup 162 backend.io.mem.writebackLda <> memBlock.io.mem_to_ooo.writebackLda 163 backend.io.mem.writebackSta <> memBlock.io.mem_to_ooo.writebackSta 164 backend.io.mem.writebackHyuLda <> memBlock.io.mem_to_ooo.writebackHyuLda 165 backend.io.mem.writebackHyuSta <> memBlock.io.mem_to_ooo.writebackHyuSta 166 backend.io.mem.writebackStd <> memBlock.io.mem_to_ooo.writebackStd 167 backend.io.mem.writebackVldu <> memBlock.io.mem_to_ooo.writebackVldu 168 backend.io.mem.robLsqIO.mmio := memBlock.io.mem_to_ooo.lsqio.mmio 169 backend.io.mem.robLsqIO.uop := memBlock.io.mem_to_ooo.lsqio.uop 170 171 // memblock error exception writeback, 1 cycle after normal writeback 172 backend.io.mem.s3_delayed_load_error := memBlock.io.mem_to_ooo.s3_delayed_load_error 173 174 backend.io.mem.exceptionAddr.vaddr := memBlock.io.mem_to_ooo.lsqio.vaddr 175 backend.io.mem.exceptionAddr.gpaddr := memBlock.io.mem_to_ooo.lsqio.gpaddr 176 backend.io.mem.exceptionAddr.isForVSnonLeafPTE := memBlock.io.mem_to_ooo.lsqio.isForVSnonLeafPTE 177 backend.io.mem.debugLS := memBlock.io.debug_ls 178 backend.io.mem.lsTopdownInfo := memBlock.io.mem_to_ooo.lsTopdownInfo 179 backend.io.mem.lqCanAccept := memBlock.io.mem_to_ooo.lsqio.lqCanAccept 180 backend.io.mem.sqCanAccept := memBlock.io.mem_to_ooo.lsqio.sqCanAccept 181 backend.io.fenceio.sbuffer.sbIsEmpty := memBlock.io.mem_to_ooo.sbIsEmpty 182 183 backend.io.perf.frontendInfo := frontend.io.frontendInfo 184 backend.io.perf.memInfo := memBlock.io.memInfo 185 backend.io.perf.perfEventsFrontend := frontend.io_perf 186 backend.io.perf.perfEventsLsu := memBlock.io_perf 187 backend.io.perf.perfEventsHc := memBlock.io.inner_hc_perfEvents 188 backend.io.perf.perfEventsBackend := DontCare 189 backend.io.perf.retiredInstr := DontCare 190 backend.io.perf.ctrlInfo := DontCare 191 192 backend.io.mem.storeDebugInfo <> memBlock.io.mem_to_ooo.storeDebugInfo 193 194 // top -> memBlock 195 memBlock.io.fromTopToBackend.clintTime := io.clintTime 196 memBlock.io.fromTopToBackend.msiInfo := io.msiInfo 197 memBlock.io.hartId := io.hartId 198 memBlock.io.l2_flush_done := io.l2_flush_done 199 memBlock.io.outer_reset_vector := io.reset_vector 200 memBlock.io.outer_hc_perfEvents := io.perfEvents 201 // frontend -> memBlock 202 memBlock.io.inner_beu_errors_icache <> frontend.io.error.bits.toL1BusErrorUnitInfo(frontend.io.error.valid) 203 memBlock.io.ooo_to_mem.backendToTopBypass := backend.io.toTop 204 memBlock.io.ooo_to_mem.issueLda <> backend.io.mem.issueLda 205 memBlock.io.ooo_to_mem.issueSta <> backend.io.mem.issueSta 206 memBlock.io.ooo_to_mem.issueStd <> backend.io.mem.issueStd 207 memBlock.io.ooo_to_mem.issueHya <> backend.io.mem.issueHylda 208 backend.io.mem.issueHysta.foreach(_.ready := false.B) // this fake port should not be used 209 memBlock.io.ooo_to_mem.issueVldu <> backend.io.mem.issueVldu 210 211 // By default, instructions do not have exceptions when they enter the function units. 212 memBlock.io.ooo_to_mem.issueUops.map(_.bits.uop.clearExceptions()) 213 memBlock.io.ooo_to_mem.storePc := backend.io.mem.storePcRead 214 memBlock.io.ooo_to_mem.hybridPc := backend.io.mem.hyuPcRead 215 memBlock.io.ooo_to_mem.flushSb := backend.io.fenceio.sbuffer.flushSb 216 memBlock.io.ooo_to_mem.loadFastMatch := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastMatch) 217 memBlock.io.ooo_to_mem.loadFastImm := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastImm) 218 memBlock.io.ooo_to_mem.loadFastFuOpType := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastFuOpType) 219 220 memBlock.io.ooo_to_mem.sfence <> backend.io.mem.sfence 221 222 memBlock.io.redirect := backend.io.mem.redirect 223 memBlock.io.ooo_to_mem.csrCtrl := backend.io.mem.csrCtrl 224 memBlock.io.ooo_to_mem.tlbCsr := backend.io.mem.tlbCsr 225 memBlock.io.ooo_to_mem.lsqio.lcommit := backend.io.mem.robLsqIO.lcommit 226 memBlock.io.ooo_to_mem.lsqio.scommit := backend.io.mem.robLsqIO.scommit 227 memBlock.io.ooo_to_mem.lsqio.pendingMMIOld := backend.io.mem.robLsqIO.pendingMMIOld 228 memBlock.io.ooo_to_mem.lsqio.pendingld := backend.io.mem.robLsqIO.pendingld 229 memBlock.io.ooo_to_mem.lsqio.pendingst := backend.io.mem.robLsqIO.pendingst 230 memBlock.io.ooo_to_mem.lsqio.pendingVst := backend.io.mem.robLsqIO.pendingVst 231 memBlock.io.ooo_to_mem.lsqio.commit := backend.io.mem.robLsqIO.commit 232 memBlock.io.ooo_to_mem.lsqio.pendingPtr := backend.io.mem.robLsqIO.pendingPtr 233 memBlock.io.ooo_to_mem.lsqio.pendingPtrNext := backend.io.mem.robLsqIO.pendingPtrNext 234 memBlock.io.ooo_to_mem.isStoreException := backend.io.mem.isStoreException 235 memBlock.io.ooo_to_mem.isVlsException := backend.io.mem.isVlsException 236 237 memBlock.io.fetch_to_mem.itlb <> frontend.io.ptw 238 memBlock.io.l2_hint.valid := io.l2_hint.valid 239 memBlock.io.l2_hint.bits.sourceId := io.l2_hint.bits.sourceId 240 memBlock.io.l2_tlb_req <> io.l2_tlb_req 241 memBlock.io.l2_pmp_resp <> io.l2_pmp_resp 242 memBlock.io.l2_hint.bits.isKeyword := io.l2_hint.bits.isKeyword 243 memBlock.io.l2PfqBusy := io.l2PfqBusy 244 245 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 246 247 // top-down info 248 memBlock.io.debugTopDown.robHeadVaddr := backend.io.debugTopDown.fromRob.robHeadVaddr 249 frontend.io.debugTopDown.robHeadVaddr := backend.io.debugTopDown.fromRob.robHeadVaddr 250 io.debugTopDown.robHeadPaddr := backend.io.debugTopDown.fromRob.robHeadPaddr 251 io.debugTopDown.robTrueCommit := backend.io.debugRolling.robTrueCommit 252 backend.io.debugTopDown.fromCore.l2MissMatch := io.debugTopDown.l2MissMatch 253 backend.io.debugTopDown.fromCore.l3MissMatch := io.debugTopDown.l3MissMatch 254 backend.io.debugTopDown.fromCore.fromMem := memBlock.io.debugTopDown.toCore 255 memBlock.io.debugRolling := backend.io.debugRolling 256 257 io.cpu_halt := memBlock.io.outer_cpu_halt 258 io.l2_flush_en := memBlock.io.outer_l2_flush_en 259 io.power_down_en := memBlock.io.outer_power_down_en 260 io.cpu_critical_error := memBlock.io.outer_cpu_critical_error 261 io.beu_errors.icache <> memBlock.io.outer_beu_errors_icache 262 io.beu_errors.dcache <> memBlock.io.error.bits.toL1BusErrorUnitInfo(memBlock.io.error.valid) 263 io.beu_errors.l2 <> DontCare 264 io.l2PfCtrl := backend.io.mem.csrCtrl.pf_ctrl.toL2PrefetchCtrl() 265 266 memBlock.io.resetInFrontendBypass.fromFrontend := frontend.io.resetInFrontend 267 io.resetInFrontend := memBlock.io.resetInFrontendBypass.toL2Top 268 memBlock.io.traceCoreInterfaceBypass.fromBackend <> backend.io.traceCoreInterface 269 io.traceCoreInterface <> memBlock.io.traceCoreInterfaceBypass.toL2Top 270 memBlock.io.topDownInfo.fromL2Top.l2Miss := io.topDownInfo.l2Miss 271 memBlock.io.topDownInfo.fromL2Top.l3Miss := io.topDownInfo.l3Miss 272 memBlock.io.topDownInfo.toBackend.noUopsIssued := backend.io.topDownInfo.noUopsIssued 273 backend.io.topDownInfo.lqEmpty := memBlock.io.topDownInfo.toBackend.lqEmpty 274 backend.io.topDownInfo.sqEmpty := memBlock.io.topDownInfo.toBackend.sqEmpty 275 backend.io.topDownInfo.l1Miss := memBlock.io.topDownInfo.toBackend.l1Miss 276 backend.io.topDownInfo.l2TopMiss.l2Miss := memBlock.io.topDownInfo.toBackend.l2TopMiss.l2Miss 277 backend.io.topDownInfo.l2TopMiss.l3Miss := memBlock.io.topDownInfo.toBackend.l2TopMiss.l3Miss 278 279 280 if (debugOpts.ResetGen) { 281 backend.reset := memBlock.io.reset_backend 282 frontend.reset := backend.io.frontendReset 283 } 284} 285