xref: /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala (revision 42b75a597e916f6a6887cb8bc626483d0d2645dd) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15*
16*
17* Acknowledgement
18*
19* This implementation is inspired by several key papers:
20* [1] James E. Smith, and Andrew R. Pleszkun. "[Implementation of precise interrupts in pipelined processors.]
21* (https://dl.acm.org/doi/10.5555/327010.327125)" 12th Annual International Symposium on Computer Architecture (ISCA).
22* 1985.
23***************************************************************************************/
24
25package xiangshan.backend.rob
26
27import org.chipsalliance.cde.config.Parameters
28import chisel3._
29import chisel3.util._
30import chisel3.experimental.BundleLiterals._
31import difftest._
32import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
33import utility._
34import utils._
35import xiangshan._
36import xiangshan.backend.GPAMemEntry
37import xiangshan.backend.{BackendParams, RatToVecExcpMod, RegWriteFromRab, VecExcpInfo}
38import xiangshan.backend.Bundles.{DynInst, ExceptionInfo, ExuOutput}
39import xiangshan.backend.decode.isa.bitfield.XSInstBitFields
40import xiangshan.backend.fu.{FuConfig, FuType}
41import xiangshan.frontend.FtqPtr
42import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr}
43import xiangshan.backend.Bundles.{DynInst, ExceptionInfo, ExuOutput}
44import xiangshan.backend.ctrlblock.{DebugLSIO, DebugLsInfo, LsTopdownInfo}
45import xiangshan.backend.fu.vector.Bundles.VType
46import xiangshan.backend.rename.SnapshotGenerator
47import yunsuan.VfaluType
48import xiangshan.backend.rob.RobBundles._
49import xiangshan.backend.trace._
50import chisel3.experimental.BundleLiterals._
51
52class Rob(params: BackendParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
53  override def shouldBeInlined: Boolean = false
54
55  lazy val module = new RobImp(this)(p, params)
56}
57
58class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendParams) extends LazyModuleImp(wrapper)
59  with HasXSParameter with HasCircularQueuePtrHelper with HasPerfEvents with HasCriticalErrors {
60
61  private val LduCnt = params.LduCnt
62  private val StaCnt = params.StaCnt
63  private val HyuCnt = params.HyuCnt
64
65  val io = IO(new Bundle() {
66    val hartId = Input(UInt(hartIdLen.W))
67    val redirect = Input(Valid(new Redirect))
68    val enq = new RobEnqIO
69    val flushOut = ValidIO(new Redirect)
70    val exception = ValidIO(new ExceptionInfo)
71    // exu + brq
72    val writeback: MixedVec[ValidIO[ExuOutput]] = Flipped(params.genWrite2CtrlBundles)
73    val exuWriteback: MixedVec[ValidIO[ExuOutput]] = Flipped(params.genWrite2CtrlBundles)
74    val writebackNums = Flipped(Vec(writeback.size - params.StdCnt, ValidIO(UInt(writeback.size.U.getWidth.W))))
75    val writebackNeedFlush = Input(Vec(params.allExuParams.filter(_.needExceptionGen).length, Bool()))
76    val commits = Output(new RobCommitIO)
77    val trace = new Bundle {
78      val blockCommit = Input(Bool())
79      val traceCommitInfo = new TraceBundle(hasIaddr = false, CommitWidth, IretireWidthInPipe)
80    }
81    val rabCommits = Output(new RabCommitIO)
82    val diffCommits = if (backendParams.basicDebugEn) Some(Output(new DiffCommitIO)) else None
83    val isVsetFlushPipe = Output(Bool())
84    val lsq = new RobLsqIO
85    val robDeqPtr = Output(new RobPtr)
86    val csr = new RobCSRIO
87    val snpt = Input(new SnapshotPort)
88    val robFull = Output(Bool())
89    val headNotReady = Output(Bool())
90    val cpu_halt = Output(Bool())
91    val wfi_enable = Input(Bool())
92    val toDecode = new Bundle {
93      val isResumeVType = Output(Bool())
94      val walkToArchVType = Output(Bool())
95      val walkVType = ValidIO(VType())
96      val commitVType = new Bundle {
97        val vtype = ValidIO(VType())
98        val hasVsetvl = Output(Bool())
99      }
100    }
101    val fromVecExcpMod = Input(new Bundle {
102      val busy = Bool()
103    })
104    val readGPAMemAddr = ValidIO(new Bundle {
105      val ftqPtr = new FtqPtr()
106      val ftqOffset = UInt(log2Up(PredictWidth).W)
107    })
108    val readGPAMemData = Input(new GPAMemEntry)
109    val vstartIsZero = Input(Bool())
110
111    val toVecExcpMod = Output(new Bundle {
112      val logicPhyRegMap = Vec(RabCommitWidth, ValidIO(new RegWriteFromRab))
113      val excpInfo = ValidIO(new VecExcpInfo)
114    })
115    val debug_ls = Flipped(new DebugLSIO)
116    val debugRobHead = Output(new DynInst)
117    val debugEnqLsq = Input(new LsqEnqIO)
118    val debugHeadLsIssue = Input(Bool())
119    val lsTopdownInfo = Vec(LduCnt + HyuCnt, Input(new LsTopdownInfo))
120    val debugTopDown = new Bundle {
121      val toCore = new RobCoreTopDownIO
122      val toDispatch = new RobDispatchTopDownIO
123      val robHeadLqIdx = Valid(new LqPtr)
124    }
125    val debugRolling = new RobDebugRollingIO
126
127    // store event difftest information
128    val storeDebugInfo = Vec(EnsbufferWidth, new Bundle {
129      val robidx = Input(new RobPtr)
130      val pc     = Output(UInt(VAddrBits.W))
131    })
132  })
133
134  val exuWBs: Seq[ValidIO[ExuOutput]] = io.exuWriteback.filter(!_.bits.params.hasStdFu).toSeq
135  val stdWBs: Seq[ValidIO[ExuOutput]] = io.exuWriteback.filter(_.bits.params.hasStdFu).toSeq
136  val vldWBs: Seq[ValidIO[ExuOutput]] = io.exuWriteback.filter(_.bits.params.hasVLoadFu).toSeq
137  val fflagsWBs = io.exuWriteback.filter(x => x.bits.fflags.nonEmpty).toSeq
138  val exceptionWBs = io.writeback.filter(x => x.bits.exceptionVec.nonEmpty).toSeq
139  val redirectWBs = io.writeback.filter(x => x.bits.redirect.nonEmpty).toSeq
140  val vxsatWBs = io.exuWriteback.filter(x => x.bits.vxsat.nonEmpty).toSeq
141  val branchWBs = io.exuWriteback.filter(_.bits.params.hasBrhFu).toSeq
142  val jmpWBs = io.exuWriteback.filter(_.bits.params.hasJmpFu).toSeq
143  val csrWBs = io.exuWriteback.filter(x => x.bits.params.hasCSR).toSeq
144
145  val numExuWbPorts = exuWBs.length
146  val numStdWbPorts = stdWBs.length
147  val bankAddrWidth = log2Up(CommitWidth)
148
149  println(s"Rob: size $RobSize, numExuWbPorts: $numExuWbPorts, numStdWbPorts: $numStdWbPorts, commitwidth: $CommitWidth")
150
151  val rab = Module(new RenameBuffer(RabSize))
152  val vtypeBuffer = Module(new VTypeBuffer(VTypeBufferSize))
153  val bankNum = 8
154  assert(RobSize % bankNum == 0, "RobSize % bankNum must be 0")
155  val robEntries = RegInit(VecInit.fill(RobSize)((new RobEntryBundle).Lit(_.valid -> false.B)))
156  // pointers
157  // For enqueue ptr, we don't duplicate it since only enqueue needs it.
158  val enqPtrVec = Wire(Vec(RenameWidth, new RobPtr))
159  val deqPtrVec = Wire(Vec(CommitWidth, new RobPtr))
160  val deqPtrVec_next = Wire(Vec(CommitWidth, Output(new RobPtr)))
161  val walkPtrVec = Reg(Vec(CommitWidth, new RobPtr))
162  val walkPtrTrue = Reg(new RobPtr)
163  val lastWalkPtr = Reg(new RobPtr)
164  val allowEnqueue = RegInit(true.B)
165  val allowEnqueueForDispatch = RegInit(true.B)
166  val vecExcpInfo = RegInit(ValidIO(new VecExcpInfo).Lit(
167    _.valid -> false.B,
168  ))
169
170  /**
171   * Enqueue (from dispatch)
172   */
173  // special cases
174  val hasBlockBackward = RegInit(false.B)
175  val hasWaitForward = RegInit(false.B)
176  val doingSvinval = RegInit(false.B)
177  val enqPtr = enqPtrVec(0)
178  val deqPtr = deqPtrVec(0)
179  val walkPtr = walkPtrVec(0)
180  val allocatePtrVec = VecInit((0 until RenameWidth).map(i => enqPtrVec(PopCount(io.enq.req.take(i).map(req => req.valid && req.bits.firstUop)))))
181  io.enq.canAccept := allowEnqueue && !hasBlockBackward && rab.io.canEnq && vtypeBuffer.io.canEnq && !io.fromVecExcpMod.busy
182  io.enq.canAcceptForDispatch := allowEnqueueForDispatch && !hasBlockBackward && rab.io.canEnqForDispatch && vtypeBuffer.io.canEnqForDispatch && !io.fromVecExcpMod.busy
183  io.enq.resp := allocatePtrVec
184  val canEnqueue = VecInit(io.enq.req.map(req => req.valid && req.bits.firstUop && io.enq.canAccept))
185  val timer = GTimer()
186  // robEntries enqueue
187  for (i <- 0 until RobSize) {
188    val enqOH = VecInit(canEnqueue.zip(allocatePtrVec.map(_.value === i.U)).map(x => x._1 && x._2))
189    assert(PopCount(enqOH) < 2.U, s"robEntries$i enqOH is not one hot")
190    when(enqOH.asUInt.orR && !io.redirect.valid){
191      connectEnq(robEntries(i), Mux1H(enqOH, io.enq.req.map(_.bits)))
192    }
193  }
194  // robBanks0 include robidx : 0 8 16 24 32 ...
195  val robBanks = VecInit((0 until bankNum).map(i => VecInit(robEntries.zipWithIndex.filter(_._2 % bankNum == i).map(_._1))))
196  // each Bank has 20 Entries, read addr is one hot
197  // all banks use same raddr
198  val eachBankEntrieNum = robBanks(0).length
199  val robBanksRaddrThisLine = RegInit(1.U(eachBankEntrieNum.W))
200  val robBanksRaddrNextLine = Wire(UInt(eachBankEntrieNum.W))
201  robBanksRaddrThisLine := robBanksRaddrNextLine
202  val bankNumWidth = log2Up(bankNum)
203  val deqPtrWidth = deqPtr.value.getWidth
204  val robIdxThisLine = VecInit((0 until bankNum).map(i => Cat(deqPtr.value(deqPtrWidth - 1, bankNumWidth), i.U(bankNumWidth.W))))
205  val robIdxNextLine = VecInit((0 until bankNum).map(i => Cat(deqPtr.value(deqPtrWidth - 1, bankNumWidth) + 1.U, i.U(bankNumWidth.W))))
206  // robBanks read
207  val robBanksRdataThisLine = VecInit(robBanks.map{ case bank =>
208    Mux1H(robBanksRaddrThisLine, bank)
209  })
210  val robBanksRdataNextLine = VecInit(robBanks.map{ case bank =>
211    val shiftBank = bank.drop(1) :+ bank(0)
212    Mux1H(robBanksRaddrThisLine, shiftBank)
213  })
214  val robBanksRdataThisLineUpdate = Wire(Vec(CommitWidth, new RobEntryBundle))
215  val robBanksRdataNextLineUpdate = Wire(Vec(CommitWidth, new RobEntryBundle))
216  val commitValidThisLine = Wire(Vec(CommitWidth, Bool()))
217  val hasCommitted = RegInit(VecInit(Seq.fill(CommitWidth)(false.B)))
218  val donotNeedWalk = RegInit(VecInit(Seq.fill(CommitWidth)(false.B)))
219  val allCommitted = Wire(Bool())
220
221  when(allCommitted) {
222    hasCommitted := 0.U.asTypeOf(hasCommitted)
223  }.elsewhen(io.commits.isCommit){
224    for (i <- 0 until CommitWidth){
225      hasCommitted(i) := commitValidThisLine(i) || hasCommitted(i)
226    }
227  }
228  allCommitted := io.commits.isCommit && commitValidThisLine.last
229  val walkPtrHead = Wire(new RobPtr)
230  val changeBankAddrToDeqPtr = (walkPtrVec.head + CommitWidth.U) > lastWalkPtr
231  when(io.redirect.valid){
232    robBanksRaddrNextLine := UIntToOH(walkPtrHead.value(walkPtrHead.value.getWidth-1, bankAddrWidth))
233  }.elsewhen(allCommitted || io.commits.isWalk && !changeBankAddrToDeqPtr){
234    robBanksRaddrNextLine := Mux(robBanksRaddrThisLine.head(1) === 1.U, 1.U, robBanksRaddrThisLine << 1)
235  }.elsewhen(io.commits.isWalk && changeBankAddrToDeqPtr){
236    robBanksRaddrNextLine := UIntToOH(deqPtr.value(deqPtr.value.getWidth-1, bankAddrWidth))
237  }.otherwise(
238    robBanksRaddrNextLine := robBanksRaddrThisLine
239  )
240  val robDeqGroup = Reg(Vec(bankNum, new RobCommitEntryBundle))
241  val rawInfo = VecInit((0 until CommitWidth).map(i => robDeqGroup(deqPtrVec(i).value(bankAddrWidth-1, 0)))).toSeq
242  val commitInfo = VecInit((0 until CommitWidth).map(i => robDeqGroup(deqPtrVec(i).value(bankAddrWidth-1,0)))).toSeq
243  val walkInfo = VecInit((0 until CommitWidth).map(i => robDeqGroup(walkPtrVec(i).value(bankAddrWidth-1, 0)))).toSeq
244  for (i <- 0 until CommitWidth) {
245    connectCommitEntry(robDeqGroup(i), robBanksRdataThisLineUpdate(i))
246    when(allCommitted){
247      connectCommitEntry(robDeqGroup(i), robBanksRdataNextLineUpdate(i))
248    }
249  }
250
251  // In each robentry, the ftqIdx and ftqOffset belong to the first instruction that was compressed,
252  // That is Necessary when exceptions happen.
253  // Update the ftqOffset to correctly notify the frontend which instructions have been committed.
254  // Instructions in multiple Ftq entries compressed to one RobEntry do not occur.
255  for (i <- 0 until CommitWidth) {
256    val lastOffset = (rawInfo(i).traceBlockInPipe.iretire - (1.U << rawInfo(i).traceBlockInPipe.ilastsize.asUInt).asUInt) + rawInfo(i).ftqOffset
257    commitInfo(i).ftqOffset := Mux(CommitType.isFused(rawInfo(i).commitType), rawInfo(i).ftqOffset, lastOffset)
258  }
259
260  // data for debug
261  // Warn: debug_* prefix should not exist in generated verilog.
262  val debug_microOp = DebugMem(RobSize, new DynInst)
263  val debug_exuData = Reg(Vec(RobSize, UInt(XLEN.W))) //for debug
264  val debug_exuDebug = Reg(Vec(RobSize, new DebugBundle)) //for debug
265  val debug_lsInfo = RegInit(VecInit(Seq.fill(RobSize)(DebugLsInfo.init)))
266  val debug_lsTopdownInfo = RegInit(VecInit(Seq.fill(RobSize)(LsTopdownInfo.init)))
267  val debug_lqIdxValid = RegInit(VecInit.fill(RobSize)(false.B))
268  val debug_lsIssued = RegInit(VecInit.fill(RobSize)(false.B))
269
270  val isEmpty = enqPtr === deqPtr
271  val snptEnq = io.enq.canAccept && io.enq.req.map(x => x.valid && x.bits.snapshot).reduce(_ || _)
272  val snapshotPtrVec = Wire(Vec(CommitWidth, new RobPtr))
273  snapshotPtrVec(0) := io.enq.req(0).bits.robIdx
274  for (i <- 1 until CommitWidth) {
275    snapshotPtrVec(i) := snapshotPtrVec(0) + i.U
276  }
277  val snapshots = SnapshotGenerator(snapshotPtrVec, snptEnq, io.snpt.snptDeq, io.redirect.valid, io.snpt.flushVec)
278  val debug_lsIssue = WireDefault(debug_lsIssued)
279  debug_lsIssue(deqPtr.value) := io.debugHeadLsIssue
280
281  /**
282   * states of Rob
283   */
284  val s_idle :: s_walk :: Nil = Enum(2)
285  val state = RegInit(s_idle)
286  val state_next = Wire(chiselTypeOf(state))
287
288  val tip_computing :: tip_stalled :: tip_walk :: tip_drained :: Nil = Enum(4)
289  val tip_state = WireInit(0.U(4.W))
290  when(!isEmpty) {  // One or more inst in ROB
291    when(state === s_walk || io.redirect.valid) {
292      tip_state := tip_walk
293    }.elsewhen(io.commits.isCommit && PopCount(io.commits.commitValid) =/= 0.U) {
294      tip_state := tip_computing
295    }.otherwise {
296      tip_state := tip_stalled
297    }
298  }.otherwise {
299    tip_state := tip_drained
300  }
301  class TipEntry()(implicit p: Parameters) extends XSBundle {
302    val state = UInt(4.W)
303    val commits = new RobCommitIO()      // info of commit
304    val redirect = Valid(new Redirect)   // info of redirect
305    val redirect_pc = UInt(VAddrBits.W)  // PC of the redirect uop
306    val debugLsInfo = new DebugLsInfo()
307  }
308  val tip_table = ChiselDB.createTable("Tip_" + p(XSCoreParamsKey).HartId.toString, new TipEntry)
309  val tip_data = Wire(new TipEntry())
310  tip_data.state := tip_state
311  tip_data.commits := io.commits
312  tip_data.redirect := io.redirect
313  tip_data.redirect_pc := debug_microOp(io.redirect.bits.robIdx.value).pc
314  tip_data.debugLsInfo := debug_lsInfo(io.commits.robIdx(0).value)
315  tip_table.log(tip_data, true.B, "", clock, reset)
316
317  val exceptionGen = Module(new ExceptionGen(params))
318  val exceptionDataRead = exceptionGen.io.state
319  val fflagsDataRead = Wire(Vec(CommitWidth, UInt(5.W)))
320  val vxsatDataRead = Wire(Vec(CommitWidth, Bool()))
321  io.robDeqPtr := deqPtr
322  io.debugRobHead := debug_microOp(deqPtr.value)
323
324  /**
325   * connection of [[rab]]
326   */
327  rab.io.redirect.valid := io.redirect.valid
328
329  rab.io.req.zip(io.enq.req).map { case (dest, src) =>
330    dest.bits := src.bits
331    dest.valid := src.valid && io.enq.canAccept
332  }
333
334  val walkDestSizeDeqGroup = RegInit(VecInit(Seq.fill(CommitWidth)(0.U(log2Up(MaxUopSize + 1).W))))
335  val realDestSizeSeq = VecInit(robDeqGroup.zip(hasCommitted).map{case (r, h) => Mux(h, 0.U, r.realDestSize)})
336  val walkDestSizeSeq = VecInit(robDeqGroup.zip(donotNeedWalk).map{case (r, d) => Mux(d, 0.U, r.realDestSize)})
337  val commitSizeSumSeq = VecInit((0 until CommitWidth).map(i => realDestSizeSeq.take(i + 1).reduce(_ +& _)))
338  val walkSizeSumSeq   = VecInit((0 until CommitWidth).map(i => walkDestSizeSeq.take(i + 1).reduce(_ +& _)))
339  val commitSizeSumCond = VecInit(commitValidThisLine.zip(hasCommitted).map{case (c,h) => (c || h) && io.commits.isCommit})
340  val walkSizeSumCond   = VecInit(io.commits.walkValid.zip(donotNeedWalk).map{case (w,d) => (w || d) && io.commits.isWalk})
341  val commitSizeSum = PriorityMuxDefault(commitSizeSumCond.reverse.zip(commitSizeSumSeq.reverse), 0.U)
342  val walkSizeSum   = PriorityMuxDefault(walkSizeSumCond.reverse.zip(walkSizeSumSeq.reverse), 0.U)
343
344  val deqVlsExceptionNeedCommit = RegInit(false.B)
345  val deqVlsExceptionCommitSize = RegInit(0.U(log2Up(MaxUopSize + 1).W))
346  val deqVlsCanCommit= RegInit(false.B)
347  rab.io.fromRob.commitSize := Mux(deqVlsExceptionNeedCommit, deqVlsExceptionCommitSize, commitSizeSum)
348  rab.io.fromRob.walkSize := walkSizeSum
349  rab.io.fromRob.vecLoadExcp.valid := RegNext(exceptionDataRead.valid && exceptionDataRead.bits.isVecLoad)
350  rab.io.fromRob.vecLoadExcp.bits.isStrided := RegEnable(exceptionDataRead.bits.isStrided, exceptionDataRead.valid)
351  rab.io.fromRob.vecLoadExcp.bits.isVlm := RegEnable(exceptionDataRead.bits.isVlm, exceptionDataRead.valid)
352  rab.io.snpt := io.snpt
353  rab.io.snpt.snptEnq := snptEnq
354
355  // pipe rab commits for better timing and area
356  io.rabCommits := RegNext(rab.io.commits)
357  io.diffCommits.foreach(_ := rab.io.diffCommits.get)
358
359  /**
360   * connection of [[vtypeBuffer]]
361   */
362
363  vtypeBuffer.io.redirect.valid := io.redirect.valid
364
365  vtypeBuffer.io.req.zip(io.enq.req).map { case (sink, source) =>
366    sink.valid := source.valid && io.enq.canAccept
367    sink.bits := source.bits
368  }
369
370  private val commitIsVTypeVec = VecInit(io.commits.commitValid.zip(io.commits.info).map { case (valid, info) => io.commits.isCommit && valid && info.isVset })
371  private val walkIsVTypeVec = VecInit(io.commits.walkValid.zip(walkInfo).map { case (valid, info) => io.commits.isWalk && valid && info.isVset })
372  vtypeBuffer.io.fromRob.commitSize := PopCount(commitIsVTypeVec)
373  vtypeBuffer.io.fromRob.walkSize := PopCount(walkIsVTypeVec)
374  vtypeBuffer.io.snpt := io.snpt
375  vtypeBuffer.io.snpt.snptEnq := snptEnq
376  io.toDecode.isResumeVType := vtypeBuffer.io.toDecode.isResumeVType
377  io.toDecode.walkToArchVType := vtypeBuffer.io.toDecode.walkToArchVType
378  io.toDecode.commitVType := vtypeBuffer.io.toDecode.commitVType
379  io.toDecode.walkVType := vtypeBuffer.io.toDecode.walkVType
380
381  // When blockBackward instruction leaves Rob (commit or walk), hasBlockBackward should be set to false.B
382  // To reduce registers usage, for hasBlockBackward cases, we allow enqueue after ROB is empty.
383  when(isEmpty) {
384    hasBlockBackward := false.B
385  }
386  // When any instruction commits, hasNoSpecExec should be set to false.B
387  when(io.commits.hasWalkInstr || io.commits.hasCommitInstr) {
388    hasWaitForward := false.B
389  }
390
391  // The wait-for-interrupt (WFI) instruction waits in the ROB until an interrupt might need servicing.
392  // io.csr.wfiEvent will be asserted if the WFI can resume execution, and we change the state to s_wfi_idle.
393  // It does not affect how interrupts are serviced. Note that WFI is noSpecExec and it does not trigger interrupts.
394  val hasWFI = RegInit(false.B)
395  io.cpu_halt := hasWFI
396  // WFI Timeout: 2^20 = 1M cycles
397  val wfi_cycles = RegInit(0.U(20.W))
398  when(hasWFI) {
399    wfi_cycles := wfi_cycles + 1.U
400  }.elsewhen(!hasWFI && RegNext(hasWFI)) {
401    wfi_cycles := 0.U
402  }
403  val wfi_timeout = wfi_cycles.andR
404  when(RegNext(RegNext(io.csr.wfiEvent)) || io.flushOut.valid || wfi_timeout) {
405    hasWFI := false.B
406  }
407
408  for (i <- 0 until RenameWidth) {
409    // we don't check whether io.redirect is valid here since redirect has higher priority
410    when(canEnqueue(i)) {
411      val enqUop = io.enq.req(i).bits
412      val enqIndex = allocatePtrVec(i).value
413      // store uop in data module and debug_microOp Vec
414      debug_microOp(enqIndex) := enqUop
415      debug_microOp(enqIndex).debugInfo.dispatchTime := timer
416      debug_microOp(enqIndex).debugInfo.enqRsTime := timer
417      debug_microOp(enqIndex).debugInfo.selectTime := timer
418      debug_microOp(enqIndex).debugInfo.issueTime := timer
419      debug_microOp(enqIndex).debugInfo.writebackTime := timer
420      debug_microOp(enqIndex).debugInfo.tlbFirstReqTime := timer
421      debug_microOp(enqIndex).debugInfo.tlbRespTime := timer
422      debug_lsInfo(enqIndex) := DebugLsInfo.init
423      debug_lsTopdownInfo(enqIndex) := LsTopdownInfo.init
424      debug_lqIdxValid(enqIndex) := false.B
425      debug_lsIssued(enqIndex) := false.B
426      when (enqUop.waitForward) {
427        hasWaitForward := true.B
428      }
429      val enqTriggerActionIsDebugMode = TriggerAction.isDmode(io.enq.req(i).bits.trigger)
430      val enqHasException = ExceptionNO.selectFrontend(enqUop.exceptionVec).asUInt.orR
431      // the begin instruction of Svinval enqs so mark doingSvinval as true to indicate this process
432      when(!enqTriggerActionIsDebugMode && !enqHasException && enqUop.isSvinvalBegin(enqUop.flushPipe)) {
433        doingSvinval := true.B
434      }
435      // the end instruction of Svinval enqs so clear doingSvinval
436      when(!enqTriggerActionIsDebugMode && !enqHasException && enqUop.isSvinvalEnd(enqUop.flushPipe)) {
437        doingSvinval := false.B
438      }
439      // when we are in the process of Svinval software code area , only Svinval.vma and end instruction of Svinval can appear
440      assert(!doingSvinval || (enqUop.isSvinval(enqUop.flushPipe) || enqUop.isSvinvalEnd(enqUop.flushPipe) || enqUop.isNotSvinval))
441      when(enqUop.isWFI && !enqHasException && !enqTriggerActionIsDebugMode) {
442        hasWFI := true.B
443      }
444
445      robEntries(enqIndex).mmio := false.B
446      robEntries(enqIndex).vls := enqUop.vlsInstr
447    }
448  }
449
450  for (i <- 0 until RenameWidth) {
451    val enqUop = io.enq.req(i)
452    when(enqUop.valid && enqUop.bits.blockBackward && io.enq.canAccept) {
453      hasBlockBackward := true.B
454    }
455  }
456
457  val dispatchNum = Mux(io.enq.canAccept, PopCount(io.enq.req.map(req => req.valid && req.bits.firstUop)), 0.U)
458  io.enq.isEmpty := RegNext(isEmpty && !VecInit(io.enq.req.map(_.valid)).asUInt.orR)
459
460  when(!io.wfi_enable) {
461    hasWFI := false.B
462  }
463  // sel vsetvl's flush position
464  val vs_idle :: vs_waitVinstr :: vs_waitFlush :: Nil = Enum(3)
465  val vsetvlState = RegInit(vs_idle)
466
467  val firstVInstrFtqPtr = RegInit(0.U.asTypeOf(new FtqPtr))
468  val firstVInstrFtqOffset = RegInit(0.U.asTypeOf(UInt(log2Up(PredictWidth).W)))
469  val firstVInstrRobIdx = RegInit(0.U.asTypeOf(new RobPtr))
470
471  val enq0 = io.enq.req(0)
472  val enq0IsVset = enq0.bits.isVset && enq0.bits.lastUop && canEnqueue(0)
473  val enq0IsVsetFlush = enq0IsVset && enq0.bits.flushPipe
474  val enqIsVInstrVec = io.enq.req.zip(canEnqueue).map { case (req, fire) => FuType.isVArith(req.bits.fuType) && fire }
475  // for vs_idle
476  val firstVInstrIdle = PriorityMux(enqIsVInstrVec.zip(io.enq.req).drop(1) :+ (true.B, 0.U.asTypeOf(io.enq.req(0).cloneType)))
477  // for vs_waitVinstr
478  val enqIsVInstrOrVset = (enqIsVInstrVec(0) || enq0IsVset) +: enqIsVInstrVec.drop(1)
479  val firstVInstrWait = PriorityMux(enqIsVInstrOrVset, io.enq.req)
480  when(vsetvlState === vs_idle) {
481    firstVInstrFtqPtr := firstVInstrIdle.bits.ftqPtr
482    firstVInstrFtqOffset := firstVInstrIdle.bits.ftqOffset
483    firstVInstrRobIdx := firstVInstrIdle.bits.robIdx
484  }.elsewhen(vsetvlState === vs_waitVinstr) {
485    when(Cat(enqIsVInstrOrVset).orR) {
486      firstVInstrFtqPtr := firstVInstrWait.bits.ftqPtr
487      firstVInstrFtqOffset := firstVInstrWait.bits.ftqOffset
488      firstVInstrRobIdx := firstVInstrWait.bits.robIdx
489    }
490  }
491
492  val hasVInstrAfterI = Cat(enqIsVInstrVec(0)).orR
493  when(vsetvlState === vs_idle && !io.redirect.valid) {
494    when(enq0IsVsetFlush) {
495      vsetvlState := Mux(hasVInstrAfterI, vs_waitFlush, vs_waitVinstr)
496    }
497  }.elsewhen(vsetvlState === vs_waitVinstr) {
498    when(io.redirect.valid) {
499      vsetvlState := vs_idle
500    }.elsewhen(Cat(enqIsVInstrOrVset).orR) {
501      vsetvlState := vs_waitFlush
502    }
503  }.elsewhen(vsetvlState === vs_waitFlush) {
504    when(io.redirect.valid) {
505      vsetvlState := vs_idle
506    }
507  }
508
509  // lqEnq
510  io.debugEnqLsq.needAlloc.map(_(0)).zip(io.debugEnqLsq.req).foreach { case (alloc, req) =>
511    when(io.debugEnqLsq.canAccept && alloc && req.valid) {
512      debug_microOp(req.bits.robIdx.value).lqIdx := req.bits.lqIdx
513      debug_lqIdxValid(req.bits.robIdx.value) := true.B
514    }
515  }
516
517  // lsIssue
518  when(io.debugHeadLsIssue) {
519    debug_lsIssued(deqPtr.value) := true.B
520  }
521
522  /**
523   * Writeback (from execution units)
524   */
525  for (wb <- exuWBs) {
526    val wbIdx = wb.bits.robIdx.value
527    val debug_Uop = debug_microOp(wbIdx)
528    when(wb.valid) {
529      debug_exuData(wbIdx) := wb.bits.data(0)
530      debug_exuDebug(wbIdx) := wb.bits.debug
531      debug_microOp(wbIdx).debugInfo.enqRsTime := wb.bits.debugInfo.enqRsTime
532      debug_microOp(wbIdx).debugInfo.selectTime := wb.bits.debugInfo.selectTime
533      debug_microOp(wbIdx).debugInfo.issueTime := wb.bits.debugInfo.issueTime
534      debug_microOp(wbIdx).debugInfo.writebackTime := wb.bits.debugInfo.writebackTime
535
536      // debug for lqidx and sqidx
537      debug_microOp(wbIdx).lqIdx := wb.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr))
538      debug_microOp(wbIdx).sqIdx := wb.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr))
539    }
540    XSInfo(wb.valid,
541      p"writebacked pc 0x${Hexadecimal(debug_Uop.pc)} wen ${debug_Uop.rfWen} " +
542        p"data 0x${Hexadecimal(wb.bits.data(0))} ldst ${debug_Uop.ldest} pdst ${debug_Uop.pdest} " +
543        p"skip ${wb.bits.debug.isSkipDiff} robIdx: ${wb.bits.robIdx}\n"
544    )
545  }
546
547  val writebackNum = PopCount(exuWBs.map(_.valid))
548  XSInfo(writebackNum =/= 0.U, "writebacked %d insts\n", writebackNum)
549
550  for (i <- 0 until LoadPipelineWidth) {
551    when(RegNext(io.lsq.mmio(i))) {
552      robEntries(RegEnable(io.lsq.uop(i).robIdx, io.lsq.mmio(i)).value).mmio := true.B
553    }
554  }
555
556
557  /**
558   * RedirectOut: Interrupt and Exceptions
559   */
560  val debug_deqUop = debug_microOp(deqPtr.value)
561
562  val deqPtrEntry = rawInfo(0)
563  val deqPtrEntryValid = deqPtrEntry.commit_v
564  val deqHasFlushed = RegInit(false.B)
565  val intrBitSetReg = RegNext(io.csr.intrBitSet)
566  val intrEnable = intrBitSetReg && !hasWaitForward && deqPtrEntry.interrupt_safe && !deqHasFlushed
567  val deqNeedFlush = deqPtrEntry.needFlush && deqPtrEntry.commit_v && deqPtrEntry.commit_w
568  val deqHitExceptionGenState = exceptionDataRead.valid && exceptionDataRead.bits.robIdx === deqPtr
569  val deqNeedFlushAndHitExceptionGenState = deqNeedFlush && deqHitExceptionGenState
570  val exceptionGenStateIsException = exceptionDataRead.bits.exceptionVec.asUInt.orR || exceptionDataRead.bits.singleStep || TriggerAction.isDmode(exceptionDataRead.bits.trigger)
571  val deqHasException = deqNeedFlushAndHitExceptionGenState && exceptionGenStateIsException && (!deqPtrEntry.isVls || RegNext(RegNext(deqPtrEntry.commit_w)))
572  val deqHasFlushPipe = deqNeedFlushAndHitExceptionGenState && exceptionDataRead.bits.flushPipe && !deqHasException && (!deqPtrEntry.isVls || RegNext(RegNext(deqPtrEntry.commit_w)))
573  val deqHasReplayInst = deqNeedFlushAndHitExceptionGenState && exceptionDataRead.bits.replayInst
574  val deqIsVlsException = deqHasException && deqPtrEntry.isVls && !exceptionDataRead.bits.isEnqExcp
575  // delay 2 cycle wait exceptionGen out
576  // vls exception can be committed only when RAB commit all its reg pairs
577  deqVlsCanCommit := RegNext(RegNext(deqIsVlsException && deqPtrEntry.commit_w)) && rab.io.status.commitEnd
578
579  // lock at assertion of deqVlsExceptionNeedCommit until condition not assert
580  val deqVlsExcpLock = RegInit(false.B)
581  val handleVlsExcp = deqIsVlsException && deqVlsCanCommit && !deqVlsExcpLock && state === s_idle
582  when(handleVlsExcp) {
583    deqVlsExcpLock := true.B
584  }.elsewhen(deqPtrVec.head =/= deqPtrVec_next.head) {
585    deqVlsExcpLock := false.B
586  }
587
588  // Only assert once when deqVlsExcp occurs until condition not assert to avoid multi message passed to RAB
589  when (deqVlsExceptionNeedCommit) {
590    deqVlsExceptionNeedCommit := false.B
591  }.elsewhen(handleVlsExcp){
592    deqVlsExceptionCommitSize := deqPtrEntry.realDestSize
593    deqVlsExceptionNeedCommit := true.B
594  }
595
596  XSDebug(deqHasException && exceptionDataRead.bits.singleStep, "Debug Mode: Deq has singlestep exception\n")
597  XSDebug(deqHasException && TriggerAction.isDmode(exceptionDataRead.bits.trigger), "Debug Mode: Deq has trigger entry debug Mode\n")
598
599  val isFlushPipe = deqPtrEntry.commit_w && (deqHasFlushPipe || deqHasReplayInst)
600
601  val isVsetFlushPipe = deqPtrEntry.commit_w && deqHasFlushPipe && exceptionDataRead.bits.isVset
602  //  val needModifyFtqIdxOffset = isVsetFlushPipe && (vsetvlState === vs_waitFlush)
603  val needModifyFtqIdxOffset = false.B
604  io.isVsetFlushPipe := isVsetFlushPipe
605  // io.flushOut will trigger redirect at the next cycle.
606  // Block any redirect or commit at the next cycle.
607  val lastCycleFlush = RegNext(io.flushOut.valid)
608
609  io.flushOut.valid := (state === s_idle) && deqPtrEntryValid && (intrEnable || deqHasException && (!deqIsVlsException || deqVlsCanCommit) || isFlushPipe) && !lastCycleFlush
610  io.flushOut.bits := DontCare
611  io.flushOut.bits.isRVC := deqPtrEntry.isRVC
612  io.flushOut.bits.robIdx := Mux(needModifyFtqIdxOffset, firstVInstrRobIdx, deqPtr)
613  io.flushOut.bits.ftqIdx := Mux(needModifyFtqIdxOffset, firstVInstrFtqPtr, deqPtrEntry.ftqIdx)
614  io.flushOut.bits.ftqOffset := Mux(needModifyFtqIdxOffset, firstVInstrFtqOffset, deqPtrEntry.ftqOffset)
615  io.flushOut.bits.level := Mux(deqHasReplayInst || intrEnable || deqHasException || needModifyFtqIdxOffset, RedirectLevel.flush, RedirectLevel.flushAfter) // TODO use this to implement "exception next"
616  io.flushOut.bits.interrupt := true.B
617  XSPerfAccumulate("flush_num", io.flushOut.valid)
618  XSPerfAccumulate("interrupt_num", io.flushOut.valid && intrEnable)
619  XSPerfAccumulate("exception_num", io.flushOut.valid && deqHasException)
620  XSPerfAccumulate("flush_pipe_num", io.flushOut.valid && isFlushPipe)
621  XSPerfAccumulate("replay_inst_num", io.flushOut.valid && isFlushPipe && deqHasReplayInst)
622
623  val exceptionHappen = (state === s_idle) && deqPtrEntryValid && (intrEnable || deqHasException && (!deqIsVlsException || deqVlsCanCommit)) && !lastCycleFlush
624  io.exception.valid := RegNext(exceptionHappen)
625  io.exception.bits.pc := RegEnable(debug_deqUop.pc, exceptionHappen)
626  io.exception.bits.gpaddr := io.readGPAMemData.gpaddr
627  io.exception.bits.isForVSnonLeafPTE := io.readGPAMemData.isForVSnonLeafPTE
628  io.exception.bits.instr := RegEnable(debug_deqUop.instr, exceptionHappen)
629  io.exception.bits.commitType := RegEnable(deqPtrEntry.commitType, exceptionHappen)
630  io.exception.bits.exceptionVec := RegEnable(exceptionDataRead.bits.exceptionVec, exceptionHappen)
631  // fetch trigger fire or execute ebreak
632  io.exception.bits.isPcBkpt := RegEnable(
633    exceptionDataRead.bits.exceptionVec(ExceptionNO.EX_BP) && (
634      exceptionDataRead.bits.isEnqExcp ||
635      exceptionDataRead.bits.trigger === TriggerAction.None
636    ),
637    exceptionHappen,
638  )
639  io.exception.bits.isFetchMalAddr := RegEnable(exceptionDataRead.bits.isFetchMalAddr && deqHasException, exceptionHappen)
640  io.exception.bits.singleStep := RegEnable(exceptionDataRead.bits.singleStep, exceptionHappen)
641  io.exception.bits.crossPageIPFFix := RegEnable(exceptionDataRead.bits.crossPageIPFFix, exceptionHappen)
642  io.exception.bits.isInterrupt := RegEnable(intrEnable, exceptionHappen)
643  io.exception.bits.isHls := RegEnable(deqPtrEntry.isHls, exceptionHappen)
644  io.exception.bits.vls := RegEnable(deqPtrEntry.vls, exceptionHappen)
645  io.exception.bits.trigger := RegEnable(exceptionDataRead.bits.trigger, exceptionHappen)
646
647  // data will be one cycle after valid
648  io.readGPAMemAddr.valid := exceptionHappen
649  io.readGPAMemAddr.bits.ftqPtr := exceptionDataRead.bits.ftqPtr
650  io.readGPAMemAddr.bits.ftqOffset := exceptionDataRead.bits.ftqOffset
651
652  XSDebug(io.flushOut.valid,
653    p"generate redirect: pc 0x${Hexadecimal(io.exception.bits.pc)} intr $intrEnable " +
654      p"excp $deqHasException flushPipe $isFlushPipe " +
655      p"Trap_target 0x${Hexadecimal(io.csr.trapTarget.pc)} exceptionVec ${Binary(exceptionDataRead.bits.exceptionVec.asUInt)}\n")
656
657
658  /**
659   * Commits (and walk)
660   * They share the same width.
661   */
662  // T redirect.valid, T+1 use walkPtrVec read robEntries, T+2 start walk, shouldWalkVec used in T+2
663  val shouldWalkVec = Wire(Vec(CommitWidth,Bool()))
664  val walkingPtrVec = RegNext(walkPtrVec)
665  when(io.redirect.valid){
666    shouldWalkVec := 0.U.asTypeOf(shouldWalkVec)
667  }.elsewhen(RegNext(io.redirect.valid)){
668    shouldWalkVec := 0.U.asTypeOf(shouldWalkVec)
669  }.elsewhen(state === s_walk){
670    shouldWalkVec := VecInit(walkingPtrVec.map(_ <= lastWalkPtr).zip(donotNeedWalk).map(x => x._1 && !x._2))
671  }.otherwise(
672    shouldWalkVec := 0.U.asTypeOf(shouldWalkVec)
673  )
674  val walkFinished = walkPtrTrue > lastWalkPtr
675  rab.io.fromRob.walkEnd := state === s_walk && walkFinished
676  vtypeBuffer.io.fromRob.walkEnd := state === s_walk && walkFinished
677
678  require(RenameWidth <= CommitWidth)
679
680  // wiring to csr
681  val (wflags, dirtyFs) = (0 until CommitWidth).map(i => {
682    val v = io.commits.commitValid(i)
683    val info = io.commits.info(i)
684    (v & info.wflags, v & info.dirtyFs)
685  }).unzip
686  val fflags = Wire(Valid(UInt(5.W)))
687  fflags.valid := io.commits.isCommit && VecInit(wflags).asUInt.orR
688  fflags.bits := wflags.zip(fflagsDataRead).map({
689    case (w, f) => Mux(w, f, 0.U)
690  }).reduce(_ | _)
691  val dirtyVs = (0 until CommitWidth).map(i => {
692    val v = io.commits.commitValid(i)
693    val info = io.commits.info(i)
694    v & info.dirtyVs
695  })
696  val dirty_fs = io.commits.isCommit && VecInit(dirtyFs).asUInt.orR
697  val dirty_vs = io.commits.isCommit && VecInit(dirtyVs).asUInt.orR
698
699  val resetVstart = dirty_vs && !io.vstartIsZero
700
701  vecExcpInfo.valid := exceptionHappen && !intrEnable && exceptionDataRead.bits.vstartEn && exceptionDataRead.bits.isVecLoad && !exceptionDataRead.bits.isEnqExcp
702  when (exceptionHappen) {
703    vecExcpInfo.bits.nf := exceptionDataRead.bits.nf
704    vecExcpInfo.bits.vsew := exceptionDataRead.bits.vsew
705    vecExcpInfo.bits.veew := exceptionDataRead.bits.veew
706    vecExcpInfo.bits.vlmul := exceptionDataRead.bits.vlmul
707    vecExcpInfo.bits.isStride := exceptionDataRead.bits.isStrided
708    vecExcpInfo.bits.isIndexed := exceptionDataRead.bits.isIndexed
709    vecExcpInfo.bits.isWhole := exceptionDataRead.bits.isWhole
710    vecExcpInfo.bits.isVlm := exceptionDataRead.bits.isVlm
711    vecExcpInfo.bits.vstart := exceptionDataRead.bits.vstart
712  }
713
714  io.csr.vstart.valid := RegNext(Mux(exceptionHappen && deqHasException, exceptionDataRead.bits.vstartEn, resetVstart))
715  io.csr.vstart.bits := RegNext(Mux(exceptionHappen && deqHasException, exceptionDataRead.bits.vstart, 0.U))
716
717  val vxsat = Wire(Valid(Bool()))
718  vxsat.valid := io.commits.isCommit && vxsat.bits
719  vxsat.bits := io.commits.commitValid.zip(vxsatDataRead).map {
720    case (valid, vxsat) => valid & vxsat
721  }.reduce(_ | _)
722
723  // when mispredict branches writeback, stop commit in the next 2 cycles
724  // TODO: don't check all exu write back
725  val misPredWb = Cat(VecInit(redirectWBs.map(wb =>
726    wb.bits.redirect.get.bits.cfiUpdate.isMisPred && wb.bits.redirect.get.valid && wb.valid
727  ).toSeq)).orR
728  val misPredBlockCounter = Reg(UInt(3.W))
729  misPredBlockCounter := Mux(misPredWb,
730    "b111".U,
731    misPredBlockCounter >> 1.U
732  )
733  val misPredBlock = misPredBlockCounter(0)
734  val deqFlushBlockCounter = Reg(UInt(3.W))
735  val deqFlushBlock = deqFlushBlockCounter(0)
736  val deqHasCommitted = io.commits.isCommit && io.commits.commitValid(0)
737  // TODO *** WARNING ***
738  // Blocking commit. Don't change this before we fully understand the logic.
739  val deqHitRedirectReg = RegNext(io.redirect.valid && io.redirect.bits.robIdx === deqPtr) || RegNext(RegNext(io.redirect.valid && io.redirect.bits.robIdx === deqPtr))
740  val criticalErrorState = io.csr.criticalErrorState
741  when(deqNeedFlush && deqHitRedirectReg){
742    deqFlushBlockCounter := "b111".U
743  }.otherwise{
744    deqFlushBlockCounter := deqFlushBlockCounter >> 1.U
745  }
746  when(deqHasCommitted){
747    deqHasFlushed := false.B
748  }.elsewhen(deqNeedFlush && io.flushOut.valid && !io.flushOut.bits.flushItself()){
749    deqHasFlushed := true.B
750  }
751  val traceBlock = io.trace.blockCommit
752  val blockCommit = misPredBlock || lastCycleFlush || hasWFI || io.redirect.valid ||
753    (deqNeedFlush && !deqHasFlushed) || deqFlushBlock || criticalErrorState || traceBlock
754
755  io.commits.isWalk := state === s_walk
756  io.commits.isCommit := state === s_idle && !blockCommit
757
758  val walk_v = VecInit(walkingPtrVec.map(ptr => robEntries(ptr.value).valid))
759  val commit_vDeqGroup = VecInit(robDeqGroup.map(_.commit_v))
760  val commit_wDeqGroup = VecInit(robDeqGroup.map(_.commit_w))
761  val realCommitLast = deqPtrVec(0).lineHeadPtr + Fill(bankAddrWidth, 1.U)
762  val commit_block = VecInit((0 until CommitWidth).map(i => !commit_wDeqGroup(i) && !hasCommitted(i)))
763  val allowOnlyOneCommit = VecInit(robDeqGroup.map(x => x.commit_v && x.needFlush)).asUInt.orR || intrBitSetReg
764  // for instructions that may block others, we don't allow them to commit
765  io.commits.commitValid := PriorityMux(commitValidThisLine, (0 until CommitWidth).map(i => (commitValidThisLine.asUInt >> i).asUInt.asTypeOf(io.commits.commitValid)))
766
767  for (i <- 0 until CommitWidth) {
768    // defaults: state === s_idle and instructions commit
769    // when intrBitSetReg, allow only one instruction to commit at each clock cycle
770    val isBlocked = intrEnable || (deqNeedFlush && !deqHasFlushed)
771    val isBlockedByOlder = if (i != 0) commit_block.asUInt(i, 0).orR || allowOnlyOneCommit && !hasCommitted.asUInt(i - 1, 0).andR else false.B
772    commitValidThisLine(i) := commit_vDeqGroup(i) && commit_wDeqGroup(i) && !isBlocked && !isBlockedByOlder && !hasCommitted(i)
773    io.commits.info(i) := commitInfo(i)
774    io.commits.robIdx(i) := deqPtrVec(i)
775
776    io.commits.walkValid(i) := shouldWalkVec(i)
777    XSError(
778      state === s_walk &&
779      io.commits.isWalk && state === s_walk && shouldWalkVec(i) &&
780      !walk_v(i),
781      s"The walking entry($i) should be valid\n")
782
783    XSInfo(io.commits.isCommit && io.commits.commitValid(i),
784      "retired pc %x wen %d ldest %d pdest %x data %x fflags: %b vxsat: %b\n",
785      debug_microOp(deqPtrVec(i).value).pc,
786      io.commits.info(i).rfWen,
787      io.commits.info(i).debug_ldest.getOrElse(0.U),
788      io.commits.info(i).debug_pdest.getOrElse(0.U),
789      debug_exuData(deqPtrVec(i).value),
790      fflagsDataRead(i),
791      vxsatDataRead(i)
792    )
793    XSInfo(state === s_walk && io.commits.walkValid(i), "walked pc %x wen %d ldst %d data %x\n",
794      debug_microOp(walkPtrVec(i).value).pc,
795      io.commits.info(i).rfWen,
796      io.commits.info(i).debug_ldest.getOrElse(0.U),
797      debug_exuData(walkPtrVec(i).value)
798    )
799  }
800
801  // sync fflags/dirty_fs/vxsat to csr
802  io.csr.fflags   := RegNextWithEnable(fflags)
803  io.csr.dirty_fs := GatedValidRegNext(dirty_fs)
804  io.csr.dirty_vs := GatedValidRegNext(dirty_vs)
805  io.csr.vxsat    := RegNextWithEnable(vxsat)
806
807  // commit load/store to lsq
808  val ldCommitVec = VecInit((0 until CommitWidth).map(i => io.commits.commitValid(i) && io.commits.info(i).commitType === CommitType.LOAD))
809  // TODO: Check if meet the require that only set scommit when commit scala store uop
810  val stCommitVec = VecInit((0 until CommitWidth).map(i => io.commits.commitValid(i) && io.commits.info(i).commitType === CommitType.STORE && !robEntries(deqPtrVec(i).value).vls ))
811  io.lsq.lcommit := RegNext(Mux(io.commits.isCommit, PopCount(ldCommitVec), 0.U))
812  io.lsq.scommit := RegNext(Mux(io.commits.isCommit, PopCount(stCommitVec), 0.U))
813  // indicate a pending load or store
814  io.lsq.pendingMMIOld := RegNext(io.commits.isCommit && io.commits.info(0).commitType === CommitType.LOAD && deqPtrEntryValid && deqPtrEntry.mmio)
815  io.lsq.pendingld := RegNext(io.commits.isCommit && io.commits.info(0).commitType === CommitType.LOAD && deqPtrEntryValid)
816  // TODO: Check if need deassert pendingst when it is vst
817  io.lsq.pendingst := RegNext(io.commits.isCommit && io.commits.info(0).commitType === CommitType.STORE && deqPtrEntryValid)
818  // TODO: Check if set correctly when vector store is at the head of ROB
819  io.lsq.pendingVst := RegNext(io.commits.isCommit && io.commits.info(0).commitType === CommitType.STORE && deqPtrEntryValid && deqPtrEntry.vls)
820  io.lsq.commit := RegNext(io.commits.isCommit && io.commits.commitValid(0))
821  io.lsq.pendingPtr := RegNext(deqPtr)
822  io.lsq.pendingPtrNext := RegNext(deqPtrVec_next.head)
823
824  /**
825   * state changes
826   * (1) redirect: switch to s_walk
827   * (2) walk: when walking comes to the end, switch to s_idle
828   */
829  state_next := Mux(
830    io.redirect.valid || RegNext(io.redirect.valid), s_walk,
831    Mux(
832      state === s_walk && walkFinished && rab.io.status.walkEnd && vtypeBuffer.io.status.walkEnd, s_idle,
833      state
834    )
835  )
836  XSPerfAccumulate("s_idle_to_idle", state === s_idle && state_next === s_idle)
837  XSPerfAccumulate("s_idle_to_walk", state === s_idle && state_next === s_walk)
838  XSPerfAccumulate("s_walk_to_idle", state === s_walk && state_next === s_idle)
839  XSPerfAccumulate("s_walk_to_walk", state === s_walk && state_next === s_walk)
840  state := state_next
841
842  /**
843   * pointers and counters
844   */
845  val deqPtrGenModule = Module(new NewRobDeqPtrWrapper)
846  deqPtrGenModule.io.state := state
847  deqPtrGenModule.io.deq_v := commit_vDeqGroup
848  deqPtrGenModule.io.deq_w := commit_wDeqGroup
849  deqPtrGenModule.io.exception_state := exceptionDataRead
850  deqPtrGenModule.io.intrBitSetReg := intrBitSetReg
851  deqPtrGenModule.io.hasNoSpecExec := hasWaitForward
852  deqPtrGenModule.io.allowOnlyOneCommit := allowOnlyOneCommit
853  deqPtrGenModule.io.interrupt_safe := robDeqGroup(deqPtr.value(bankAddrWidth-1,0)).interrupt_safe
854  deqPtrGenModule.io.blockCommit := blockCommit
855  deqPtrGenModule.io.hasCommitted := hasCommitted
856  deqPtrGenModule.io.allCommitted := allCommitted
857  deqPtrVec := deqPtrGenModule.io.out
858  deqPtrVec_next := deqPtrGenModule.io.next_out
859
860  val enqPtrGenModule = Module(new RobEnqPtrWrapper)
861  enqPtrGenModule.io.redirect := io.redirect
862  enqPtrGenModule.io.allowEnqueue := allowEnqueue && rab.io.canEnq && !io.fromVecExcpMod.busy
863  enqPtrGenModule.io.hasBlockBackward := hasBlockBackward
864  enqPtrGenModule.io.enq := VecInit(io.enq.req.map(req => req.valid && req.bits.firstUop))
865  enqPtrVec := enqPtrGenModule.io.out
866
867  // next walkPtrVec:
868  // (1) redirect occurs: update according to state
869  // (2) walk: move forwards
870  val deqPtrReadBank = deqPtrVec_next(0).lineHeadPtr
871  val deqPtrVecForWalk = VecInit((0 until CommitWidth).map(i => deqPtrReadBank + i.U))
872  val snapPtrReadBank = snapshots(io.snpt.snptSelect)(0).lineHeadPtr
873  val snapPtrVecForWalk = VecInit((0 until CommitWidth).map(i => snapPtrReadBank + i.U))
874  val walkPtrVec_next: Vec[RobPtr] = Mux(io.redirect.valid,
875    Mux(io.snpt.useSnpt, snapPtrVecForWalk, deqPtrVecForWalk),
876    Mux((state === s_walk) && !walkFinished, VecInit(walkPtrVec.map(_ + CommitWidth.U)), walkPtrVec)
877  )
878  val walkPtrTrue_next: RobPtr = Mux(io.redirect.valid,
879    Mux(io.snpt.useSnpt, snapshots(io.snpt.snptSelect)(0), deqPtrVec_next(0)),
880    Mux((state === s_walk) && !walkFinished, walkPtrVec_next.head, walkPtrTrue)
881  )
882  walkPtrHead := walkPtrVec_next.head
883  walkPtrVec := walkPtrVec_next
884  walkPtrTrue := walkPtrTrue_next
885  // T io.redirect.valid, T+1 walkPtrLowBits update, T+2 donotNeedWalk update
886  val walkPtrLowBits = Reg(UInt(bankAddrWidth.W))
887  when(io.redirect.valid){
888    walkPtrLowBits := Mux(io.snpt.useSnpt, snapshots(io.snpt.snptSelect)(0).value(bankAddrWidth-1, 0), deqPtrVec_next(0).value(bankAddrWidth-1, 0))
889  }
890  when(io.redirect.valid) {
891    donotNeedWalk := Fill(donotNeedWalk.length, true.B).asTypeOf(donotNeedWalk)
892  }.elsewhen(RegNext(io.redirect.valid)){
893    donotNeedWalk := (0 until CommitWidth).map(i => (i.U < walkPtrLowBits))
894  }.otherwise{
895    donotNeedWalk := 0.U.asTypeOf(donotNeedWalk)
896  }
897  walkDestSizeDeqGroup.zip(walkPtrVec_next).map {
898    case (reg, ptrNext) => reg := deqPtrEntry.realDestSize
899  }
900  val numValidEntries = distanceBetween(enqPtr, deqPtr)
901  val commitCnt = PopCount(io.commits.commitValid)
902
903  allowEnqueue := numValidEntries + dispatchNum <= (RobSize - RenameWidth).U
904  allowEnqueueForDispatch := numValidEntries + dispatchNum <= (RobSize - 2 * RenameWidth).U
905
906  val redirectWalkDistance = distanceBetween(io.redirect.bits.robIdx, deqPtrVec_next(0))
907  when(io.redirect.valid) {
908    lastWalkPtr := Mux(io.redirect.bits.flushItself(), io.redirect.bits.robIdx - 1.U, io.redirect.bits.robIdx)
909  }
910
911
912  /**
913   * States
914   * We put all the stage bits changes here.
915   *
916   * All events: (1) enqueue (dispatch); (2) writeback; (3) cancel; (4) dequeue (commit);
917   * All states: (1) valid; (2) writebacked; (3) flagBkup
918   */
919
920  val deqPtrGroup = Wire(Vec(2 * CommitWidth, new RobPtr))
921  deqPtrGroup.zipWithIndex.map { case (deq, i) => deq := deqPtrVec(0) + i.U }
922  val commitReadAddr = Mux(state === s_idle, VecInit(deqPtrVec.map(_.value)), VecInit(walkPtrVec.map(_.value)))
923
924  val redirectValidReg = RegNext(io.redirect.valid)
925  val redirectBegin = Reg(UInt(log2Up(RobSize).W))
926  val redirectEnd = Reg(UInt(log2Up(RobSize).W))
927  val redirectAll = RegInit(false.B)
928  when(io.redirect.valid){
929    redirectBegin := Mux(io.redirect.bits.flushItself(), io.redirect.bits.robIdx.value - 1.U, io.redirect.bits.robIdx.value)
930    redirectEnd := enqPtr.value
931    redirectAll := io.redirect.bits.flushItself() && (io.redirect.bits.robIdx.value === enqPtr.value) && (io.redirect.bits.robIdx.flag ^ enqPtr.flag)
932  }
933
934  // update robEntries valid
935  for (i <- 0 until RobSize) {
936    val enqOH = VecInit(canEnqueue.zip(allocatePtrVec.map(_.value === i.U)).map(x => x._1 && x._2))
937    val commitCond = io.commits.isCommit && io.commits.commitValid.zip(deqPtrVec.map(_.value === i.U)).map(x => x._1 && x._2).reduce(_ || _)
938    assert(PopCount(enqOH) < 2.U, s"robEntries$i enqOH is not one hot")
939    val needFlush = redirectValidReg && (Mux(
940      redirectEnd > redirectBegin,
941      (i.U > redirectBegin) && (i.U < redirectEnd),
942      (i.U > redirectBegin) || (i.U < redirectEnd)
943    ) || redirectAll)
944    when(commitCond) {
945      robEntries(i).valid := false.B
946    }.elsewhen(enqOH.asUInt.orR && !io.redirect.valid) {
947      robEntries(i).valid := true.B
948    }.elsewhen(needFlush){
949      robEntries(i).valid := false.B
950    }
951  }
952
953  // debug_inst update
954  for (i <- 0 until (LduCnt + StaCnt)) {
955    debug_lsInfo(io.debug_ls.debugLsInfo(i).s1_robIdx).s1SignalEnable(io.debug_ls.debugLsInfo(i))
956    debug_lsInfo(io.debug_ls.debugLsInfo(i).s2_robIdx).s2SignalEnable(io.debug_ls.debugLsInfo(i))
957    debug_lsInfo(io.debug_ls.debugLsInfo(i).s3_robIdx).s3SignalEnable(io.debug_ls.debugLsInfo(i))
958  }
959  for (i <- 0 until LduCnt) {
960    debug_lsTopdownInfo(io.lsTopdownInfo(i).s1.robIdx).s1SignalEnable(io.lsTopdownInfo(i))
961    debug_lsTopdownInfo(io.lsTopdownInfo(i).s2.robIdx).s2SignalEnable(io.lsTopdownInfo(i))
962  }
963
964  // status field: writebacked
965  // enqueue logic set 6 writebacked to false
966
967  // writeback logic set numWbPorts writebacked to true
968
969  // if the first uop of an instruction is valid , write writebackedCounter
970  val uopEnqValidSeq = io.enq.req.map(req => io.enq.canAccept && req.valid)
971  val instEnqValidSeq = io.enq.req.map(req => io.enq.canAccept && req.valid && req.bits.firstUop)
972  val enqNeedWriteRFSeq = io.enq.req.map(_.bits.needWriteRf)
973  val enqHasExcpSeq = io.enq.req.map(_.bits.hasException)
974  val enqRobIdxSeq = io.enq.req.map(req => req.bits.robIdx.value)
975  val enqUopNumVec = VecInit(io.enq.req.map(req => req.bits.numUops))
976  val enqWBNumVec = VecInit(io.enq.req.map(req => req.bits.numWB))
977
978  private val enqWriteStdVec: Vec[Bool] = VecInit(io.enq.req.map {
979    req => FuType.isStore(req.bits.fuType)
980  })
981  val fflags_wb = fflagsWBs
982  val vxsat_wb = vxsatWBs
983  for (i <- 0 until RobSize) {
984
985    val robIdxMatchSeq = io.enq.req.map(_.bits.robIdx.value === i.U)
986    val uopCanEnqSeq = uopEnqValidSeq.zip(robIdxMatchSeq).map { case (valid, isMatch) => valid && isMatch }
987    val instCanEnqSeq = instEnqValidSeq.zip(robIdxMatchSeq).map { case (valid, isMatch) => valid && isMatch }
988    val instCanEnqFlag = Cat(instCanEnqSeq).orR
989    val hasExcpSeq = enqHasExcpSeq.lazyZip(robIdxMatchSeq).lazyZip(uopEnqValidSeq).map { case (excp, isMatch, valid) => excp && isMatch && valid }
990    val hasExcpFlag = Cat(hasExcpSeq).orR
991    val isFirstEnq = !robEntries(i).valid && instCanEnqFlag
992    val realDestEnqNum = PopCount(enqNeedWriteRFSeq.zip(uopCanEnqSeq).map { case (writeFlag, valid) => writeFlag && valid })
993    when(isFirstEnq){
994      robEntries(i).realDestSize := realDestEnqNum //Mux(hasExcpFlag, 0.U, realDestEnqNum)
995    }.elsewhen(robEntries(i).valid && Cat(uopCanEnqSeq).orR){
996      robEntries(i).realDestSize := robEntries(i).realDestSize + realDestEnqNum
997    }
998    val enqUopNum = PriorityMux(instCanEnqSeq, enqUopNumVec)
999    val enqWBNum = PriorityMux(instCanEnqSeq, enqWBNumVec)
1000    val enqWriteStd = PriorityMux(instCanEnqSeq, enqWriteStdVec)
1001
1002    val canWbSeq = exuWBs.map(writeback => writeback.valid && writeback.bits.robIdx.value === i.U)
1003    val canStdWbSeq = VecInit(stdWBs.map(writeback => writeback.valid && writeback.bits.robIdx.value === i.U))
1004    val wbCnt = Mux1H(canWbSeq, io.writebackNums.map(_.bits))
1005
1006    val canWbExceptionSeq = exceptionWBs.map(writeback => writeback.valid && writeback.bits.robIdx.value === i.U)
1007    val needFlush = robEntries(i).needFlush
1008    val needFlushWriteBack = Wire(Bool())
1009    needFlushWriteBack := Mux1H(canWbExceptionSeq, io.writebackNeedFlush)
1010    when(robEntries(i).valid){
1011      needFlush := needFlush || needFlushWriteBack
1012    }
1013
1014    when(robEntries(i).valid && (needFlush || needFlushWriteBack)) {
1015      // exception flush
1016      robEntries(i).uopNum := robEntries(i).uopNum - wbCnt
1017      robEntries(i).stdWritebacked := true.B
1018    }.elsewhen(!robEntries(i).valid && instCanEnqFlag) {
1019      // enq set num of uops
1020      robEntries(i).uopNum := enqWBNum
1021      robEntries(i).stdWritebacked := Mux(enqWriteStd, false.B, true.B)
1022    }.elsewhen(robEntries(i).valid) {
1023      // update by writing back
1024      robEntries(i).uopNum := robEntries(i).uopNum - wbCnt
1025      assert(!(robEntries(i).uopNum - wbCnt > robEntries(i).uopNum), s"robEntries $i uopNum is overflow!")
1026      when(canStdWbSeq.asUInt.orR) {
1027        robEntries(i).stdWritebacked := true.B
1028      }
1029    }
1030
1031    val fflagsCanWbSeq = fflags_wb.map(writeback => writeback.valid && writeback.bits.robIdx.value === i.U && writeback.bits.wflags.getOrElse(false.B))
1032    val fflagsRes = fflagsCanWbSeq.zip(fflags_wb).map { case (canWb, wb) => Mux(canWb, wb.bits.fflags.get, 0.U) }.fold(false.B)(_ | _)
1033    when(isFirstEnq) {
1034      robEntries(i).fflags := 0.U
1035    }.elsewhen(fflagsRes.orR) {
1036      robEntries(i).fflags := robEntries(i).fflags | fflagsRes
1037    }
1038
1039    val vxsatCanWbSeq = vxsat_wb.map(writeback => writeback.valid && writeback.bits.robIdx.value === i.U)
1040    val vxsatRes = vxsatCanWbSeq.zip(vxsat_wb).map { case (canWb, wb) => Mux(canWb, wb.bits.vxsat.get, 0.U) }.fold(false.B)(_ | _)
1041    when(isFirstEnq) {
1042      robEntries(i).vxsat := 0.U
1043    }.elsewhen(vxsatRes.orR) {
1044      robEntries(i).vxsat := robEntries(i).vxsat | vxsatRes
1045    }
1046
1047    // trace
1048    val taken = branchWBs.map(writeback => writeback.valid && writeback.bits.robIdx.value === i.U && writeback.bits.redirect.get.bits.cfiUpdate.taken).reduce(_ || _)
1049    when(robEntries(i).valid && Itype.isBranchType(robEntries(i).traceBlockInPipe.itype) && taken){
1050      // BranchType code(notaken itype = 4) must be correctly replaced!
1051      robEntries(i).traceBlockInPipe.itype := Itype.Taken
1052    }
1053  }
1054
1055  // begin update robBanksRdata
1056  val robBanksRdata = VecInit(robBanksRdataThisLine ++ robBanksRdataNextLine)
1057  val needUpdate = Wire(Vec(2 * CommitWidth, new RobEntryBundle))
1058  needUpdate := VecInit(robBanksRdataThisLine ++ robBanksRdataNextLine)
1059  val needUpdateRobIdx = robIdxThisLine ++ robIdxNextLine
1060  for (i <- 0 until 2 * CommitWidth) {
1061    val robIdxMatchSeq = io.enq.req.map(_.bits.robIdx.value === needUpdateRobIdx(i))
1062    val uopCanEnqSeq = uopEnqValidSeq.zip(robIdxMatchSeq).map { case (valid, isMatch) => valid && isMatch }
1063    val instCanEnqSeq = instEnqValidSeq.zip(robIdxMatchSeq).map { case (valid, isMatch) => valid && isMatch }
1064    val instCanEnqFlag = Cat(instCanEnqSeq).orR
1065    val realDestEnqNum = PopCount(enqNeedWriteRFSeq.zip(uopCanEnqSeq).map { case (writeFlag, valid) => writeFlag && valid })
1066    when(!needUpdate(i).valid && instCanEnqFlag) {
1067      needUpdate(i).realDestSize := realDestEnqNum
1068    }.elsewhen(needUpdate(i).valid && instCanEnqFlag) {
1069      needUpdate(i).realDestSize := robBanksRdata(i).realDestSize + realDestEnqNum
1070    }
1071    val enqUopNum = PriorityMux(instCanEnqSeq, enqUopNumVec)
1072    val enqWBNum = PriorityMux(instCanEnqSeq, enqWBNumVec)
1073    val enqWriteStd = PriorityMux(instCanEnqSeq, enqWriteStdVec)
1074
1075    val canWbSeq = exuWBs.map(writeback => writeback.valid && writeback.bits.robIdx.value === needUpdateRobIdx(i))
1076    val canStdWbSeq = VecInit(stdWBs.map(writeback => writeback.valid && writeback.bits.robIdx.value === needUpdateRobIdx(i)))
1077    val wbCnt = Mux1H(canWbSeq, io.writebackNums.map(_.bits))
1078
1079    val canWbExceptionSeq = exceptionWBs.map(writeback => writeback.valid && (writeback.bits.robIdx.value === needUpdateRobIdx(i)))
1080    val needFlush = robBanksRdata(i).needFlush
1081    val needFlushWriteBack = Wire(Bool())
1082    needFlushWriteBack := Mux1H(canWbExceptionSeq, io.writebackNeedFlush)
1083    when(needUpdate(i).valid) {
1084      needUpdate(i).needFlush := needFlush || needFlushWriteBack
1085    }
1086
1087    when(needUpdate(i).valid && (needFlush || needFlushWriteBack)) {
1088      // exception flush
1089      needUpdate(i).uopNum := robBanksRdata(i).uopNum - wbCnt
1090      needUpdate(i).stdWritebacked := true.B
1091    }.elsewhen(!needUpdate(i).valid && instCanEnqFlag) {
1092      // enq set num of uops
1093      needUpdate(i).uopNum := enqWBNum
1094      needUpdate(i).stdWritebacked := Mux(enqWriteStd, false.B, true.B)
1095    }.elsewhen(needUpdate(i).valid) {
1096      // update by writing back
1097      needUpdate(i).uopNum := robBanksRdata(i).uopNum - wbCnt
1098      when(canStdWbSeq.asUInt.orR) {
1099        needUpdate(i).stdWritebacked := true.B
1100      }
1101    }
1102
1103    val fflagsCanWbSeq = fflags_wb.map(writeback => writeback.valid && writeback.bits.robIdx.value === needUpdateRobIdx(i) && writeback.bits.wflags.getOrElse(false.B))
1104    val fflagsRes = fflagsCanWbSeq.zip(fflags_wb).map { case (canWb, wb) => Mux(canWb, wb.bits.fflags.get, 0.U) }.fold(false.B)(_ | _)
1105    needUpdate(i).fflags := Mux(!robBanksRdata(i).valid && instCanEnqFlag, 0.U, robBanksRdata(i).fflags | fflagsRes)
1106
1107    val vxsatCanWbSeq = vxsat_wb.map(writeback => writeback.valid && writeback.bits.robIdx.value === needUpdateRobIdx(i))
1108    val vxsatRes = vxsatCanWbSeq.zip(vxsat_wb).map { case (canWb, wb) => Mux(canWb, wb.bits.vxsat.get, 0.U) }.fold(false.B)(_ | _)
1109    needUpdate(i).vxsat := Mux(!robBanksRdata(i).valid && instCanEnqFlag, 0.U, robBanksRdata(i).vxsat | vxsatRes)
1110
1111    // trace
1112    val taken = branchWBs.map(writeback => writeback.valid && writeback.bits.robIdx.value === needUpdateRobIdx(i) && writeback.bits.redirect.get.bits.cfiUpdate.taken).reduce(_ || _)
1113    when(robBanksRdata(i).valid && Itype.isBranchType(robBanksRdata(i).traceBlockInPipe.itype) && taken){
1114      // BranchType code(notaken itype = 4) must be correctly replaced!
1115      needUpdate(i).traceBlockInPipe.itype := Itype.Taken
1116    }
1117  }
1118  robBanksRdataThisLineUpdate := VecInit(needUpdate.take(8))
1119  robBanksRdataNextLineUpdate := VecInit(needUpdate.drop(8))
1120  // end update robBanksRdata
1121
1122  // interrupt_safe
1123  for (i <- 0 until RenameWidth) {
1124    when(canEnqueue(i)) {
1125      // For now, we allow non-load-store instructions to trigger interrupts
1126      // For MMIO instructions, they should not trigger interrupts since they may
1127      // be sent to lower level before it writes back.
1128      // However, we cannot determine whether a load/store instruction is MMIO.
1129      // Thus, we don't allow load/store instructions to trigger an interrupt.
1130      // TODO: support non-MMIO load-store instructions to trigger interrupts
1131      val allow_interrupts = !CommitType.isLoadStore(io.enq.req(i).bits.commitType) && !FuType.isFence(io.enq.req(i).bits.fuType) && !FuType.isCsr(io.enq.req(i).bits.fuType) && !FuType.isVset(io.enq.req(i).bits.fuType)
1132      robEntries(allocatePtrVec(i).value).interrupt_safe := allow_interrupts
1133    }
1134  }
1135
1136  /**
1137   * read and write of data modules
1138   */
1139  val commitReadAddr_next = Mux(state_next === s_idle,
1140    VecInit(deqPtrVec_next.map(_.value)),
1141    VecInit(walkPtrVec_next.map(_.value))
1142  )
1143
1144  exceptionGen.io.redirect <> io.redirect
1145  exceptionGen.io.flush := io.flushOut.valid
1146
1147  val canEnqueueEG = VecInit(io.enq.req.map(req => req.valid && io.enq.canAccept))
1148  for (i <- 0 until RenameWidth) {
1149    exceptionGen.io.enq(i).valid := canEnqueueEG(i)
1150    exceptionGen.io.enq(i).bits.robIdx := io.enq.req(i).bits.robIdx
1151    exceptionGen.io.enq(i).bits.ftqPtr := io.enq.req(i).bits.ftqPtr
1152    exceptionGen.io.enq(i).bits.ftqOffset := io.enq.req(i).bits.ftqOffset
1153    exceptionGen.io.enq(i).bits.exceptionVec := ExceptionNO.selectFrontend(io.enq.req(i).bits.exceptionVec)
1154    exceptionGen.io.enq(i).bits.hasException := io.enq.req(i).bits.hasException
1155    exceptionGen.io.enq(i).bits.isEnqExcp := io.enq.req(i).bits.hasException
1156    exceptionGen.io.enq(i).bits.isFetchMalAddr := io.enq.req(i).bits.isFetchMalAddr
1157    exceptionGen.io.enq(i).bits.flushPipe := io.enq.req(i).bits.flushPipe
1158    exceptionGen.io.enq(i).bits.isVset := io.enq.req(i).bits.isVset
1159    exceptionGen.io.enq(i).bits.replayInst := false.B
1160    XSError(canEnqueue(i) && io.enq.req(i).bits.replayInst, "enq should not set replayInst")
1161    exceptionGen.io.enq(i).bits.singleStep := io.enq.req(i).bits.singleStep
1162    exceptionGen.io.enq(i).bits.crossPageIPFFix := io.enq.req(i).bits.crossPageIPFFix
1163    exceptionGen.io.enq(i).bits.trigger := io.enq.req(i).bits.trigger
1164    exceptionGen.io.enq(i).bits.vstartEn := false.B //DontCare
1165    exceptionGen.io.enq(i).bits.vstart := 0.U //DontCare
1166    exceptionGen.io.enq(i).bits.vuopIdx := 0.U
1167    exceptionGen.io.enq(i).bits.isVecLoad := false.B
1168    exceptionGen.io.enq(i).bits.isVlm := false.B
1169    exceptionGen.io.enq(i).bits.isStrided := false.B
1170    exceptionGen.io.enq(i).bits.isIndexed := false.B
1171    exceptionGen.io.enq(i).bits.isWhole := false.B
1172    exceptionGen.io.enq(i).bits.nf := 0.U
1173    exceptionGen.io.enq(i).bits.vsew := 0.U
1174    exceptionGen.io.enq(i).bits.veew := 0.U
1175    exceptionGen.io.enq(i).bits.vlmul := 0.U
1176  }
1177
1178  println(s"ExceptionGen:")
1179  println(s"num of exceptions: ${params.numException}")
1180  require(exceptionWBs.length == exceptionGen.io.wb.length,
1181    f"exceptionWBs.length: ${exceptionWBs.length}, " +
1182      f"exceptionGen.io.wb.length: ${exceptionGen.io.wb.length}")
1183  for (((wb, exc_wb), i) <- exceptionWBs.zip(exceptionGen.io.wb).zipWithIndex) {
1184    exc_wb.valid       := wb.valid
1185    exc_wb.bits.robIdx := wb.bits.robIdx
1186    // only enq inst use ftqPtr to read gpa
1187    exc_wb.bits.ftqPtr          := 0.U.asTypeOf(exc_wb.bits.ftqPtr)
1188    exc_wb.bits.ftqOffset       := 0.U.asTypeOf(exc_wb.bits.ftqOffset)
1189    exc_wb.bits.exceptionVec    := wb.bits.exceptionVec.get
1190    exc_wb.bits.hasException    := wb.bits.exceptionVec.get.asUInt.orR // Todo: use io.writebackNeedFlush(i) instead
1191    exc_wb.bits.isEnqExcp       := false.B
1192    exc_wb.bits.isFetchMalAddr  := false.B
1193    exc_wb.bits.flushPipe       := wb.bits.flushPipe.getOrElse(false.B)
1194    exc_wb.bits.isVset          := false.B
1195    exc_wb.bits.replayInst      := wb.bits.replay.getOrElse(false.B)
1196    exc_wb.bits.singleStep      := false.B
1197    exc_wb.bits.crossPageIPFFix := false.B
1198    val trigger = wb.bits.trigger.getOrElse(TriggerAction.None).asTypeOf(exc_wb.bits.trigger)
1199    exc_wb.bits.trigger := trigger
1200    exc_wb.bits.vstartEn := (if (wb.bits.vls.nonEmpty) wb.bits.exceptionVec.get.asUInt.orR || TriggerAction.isDmode(trigger) else 0.U)
1201    exc_wb.bits.vstart := (if (wb.bits.vls.nonEmpty) wb.bits.vls.get.vpu.vstart else 0.U)
1202    exc_wb.bits.vuopIdx := (if (wb.bits.vls.nonEmpty) wb.bits.vls.get.vpu.vuopIdx else 0.U)
1203    exc_wb.bits.isVecLoad := wb.bits.vls.map(_.isVecLoad).getOrElse(false.B)
1204    exc_wb.bits.isVlm := wb.bits.vls.map(_.isVlm).getOrElse(false.B)
1205    exc_wb.bits.isStrided := wb.bits.vls.map(_.isStrided).getOrElse(false.B) // strided need two mode tmp vreg
1206    exc_wb.bits.isIndexed := wb.bits.vls.map(_.isIndexed).getOrElse(false.B) // indexed and nf=0 need non-sequential uopidx -> vdidx
1207    exc_wb.bits.isWhole := wb.bits.vls.map(_.isWhole).getOrElse(false.B) // indexed and nf=0 need non-sequential uopidx -> vdidx
1208    exc_wb.bits.nf := wb.bits.vls.map(_.vpu.nf).getOrElse(0.U)
1209    exc_wb.bits.vsew := wb.bits.vls.map(_.vpu.vsew).getOrElse(0.U)
1210    exc_wb.bits.veew := wb.bits.vls.map(_.vpu.veew).getOrElse(0.U)
1211    exc_wb.bits.vlmul := wb.bits.vls.map(_.vpu.vlmul).getOrElse(0.U)
1212  }
1213
1214  fflagsDataRead := (0 until CommitWidth).map(i => robEntries(deqPtrVec(i).value).fflags)
1215  vxsatDataRead := (0 until CommitWidth).map(i => robEntries(deqPtrVec(i).value).vxsat)
1216
1217  val isCommit = io.commits.isCommit
1218  val isCommitReg = GatedValidRegNext(io.commits.isCommit)
1219  val instrCntReg = RegInit(0.U(64.W))
1220  val fuseCommitCnt = PopCount(io.commits.commitValid.zip(io.commits.info).map { case (v, i) => RegEnable(v && CommitType.isFused(i.commitType), isCommit) })
1221  val trueCommitCnt = RegEnable(io.commits.commitValid.zip(io.commits.info).map { case (v, i) => Mux(v, i.instrSize, 0.U) }.reduce(_ +& _), isCommit) +& fuseCommitCnt
1222  val retireCounter = Mux(isCommitReg, trueCommitCnt, 0.U)
1223  val instrCnt = instrCntReg + retireCounter
1224  when(isCommitReg){
1225    instrCntReg := instrCnt
1226  }
1227  io.csr.perfinfo.retiredInstr := retireCounter
1228  io.robFull := !allowEnqueue
1229  io.headNotReady := commit_vDeqGroup(deqPtr.value(bankNumWidth-1, 0)) && !commit_wDeqGroup(deqPtr.value(bankNumWidth-1, 0))
1230
1231  io.toVecExcpMod.logicPhyRegMap := rab.io.toVecExcpMod.logicPhyRegMap
1232  io.toVecExcpMod.excpInfo := vecExcpInfo
1233
1234  /**
1235   * trace
1236   */
1237
1238  // trace output
1239  val traceValids = io.trace.traceCommitInfo.blocks.map(_.valid)
1240  val traceBlocks = io.trace.traceCommitInfo.blocks
1241  val traceBlockInPipe = io.trace.traceCommitInfo.blocks.map(_.bits.tracePipe)
1242
1243  // The reg 'isTraceXret' only for trace xret instructions. xret only occur in block(0).
1244  val isTraceXret = RegInit(false.B)
1245  when(io.csr.isXRet){
1246    isTraceXret := true.B
1247  }.elsewhen(isTraceXret && io.commits.isCommit && io.commits.commitValid(0)){
1248    isTraceXret := false.B
1249  }
1250
1251  for (i <- 0 until CommitWidth) {
1252    traceBlocks(i).bits.ftqIdx.foreach(_ := rawInfo(i).ftqIdx)
1253    traceBlocks(i).bits.ftqOffset.foreach(_ := rawInfo(i).ftqOffset)
1254    traceBlockInPipe(i).itype := rawInfo(i).traceBlockInPipe.itype
1255    traceBlockInPipe(i).iretire := rawInfo(i).traceBlockInPipe.iretire
1256    traceBlockInPipe(i).ilastsize := rawInfo(i).traceBlockInPipe.ilastsize
1257    traceValids(i) := io.commits.isCommit && io.commits.commitValid(i)
1258    // exception/xret only occur in block(0).
1259    if(i == 0) {
1260      when(isTraceXret && io.commits.isCommit && io.commits.commitValid(0)){ // trace xret
1261        traceBlocks(i).bits.tracePipe.itype := Itype.ExpIntReturn
1262      }.elsewhen(io.exception.valid){ // trace exception
1263        traceBlocks(i).bits.tracePipe.itype := Mux(io.exception.bits.isInterrupt,
1264          Itype.Interrupt,
1265          Itype.Exception
1266        )
1267        traceValids(i) := true.B
1268        traceBlockInPipe(i).iretire := 0.U
1269      }
1270    }
1271  }
1272
1273  /**
1274   * debug info
1275   */
1276  XSDebug(p"enqPtr ${enqPtr} deqPtr ${deqPtr}\n")
1277  XSDebug("")
1278  XSError(isBefore(enqPtr, deqPtr) && !isFull(enqPtr, deqPtr), "\ndeqPtr is older than enqPtr!\n")
1279  for (i <- 0 until RobSize) {
1280    XSDebug(false, !robEntries(i).valid, "-")
1281    XSDebug(false, robEntries(i).valid && robEntries(i).isWritebacked, "w")
1282    XSDebug(false, robEntries(i).valid && !robEntries(i).isWritebacked, "v")
1283  }
1284  XSDebug(false, true.B, "\n")
1285
1286  for (i <- 0 until RobSize) {
1287    if (i % 4 == 0) XSDebug("")
1288    XSDebug(false, true.B, "%x ", debug_microOp(i).pc)
1289    XSDebug(false, !robEntries(i).valid, "- ")
1290    XSDebug(false, robEntries(i).valid && robEntries(i).isWritebacked, "w ")
1291    XSDebug(false, robEntries(i).valid && !robEntries(i).isWritebacked, "v ")
1292    if (i % 4 == 3) XSDebug(false, true.B, "\n")
1293  }
1294
1295  def ifCommit(counter: UInt): UInt = Mux(isCommit, counter, 0.U)
1296
1297  def ifCommitReg(counter: UInt): UInt = Mux(isCommitReg, counter, 0.U)
1298
1299  val commitDebugUop = deqPtrVec.map(_.value).map(debug_microOp(_))
1300  XSPerfAccumulate("clock_cycle", 1.U)
1301  QueuePerf(RobSize, numValidEntries, numValidEntries === RobSize.U)
1302  XSPerfAccumulate("commitUop", ifCommit(commitCnt))
1303  XSPerfAccumulate("commitInstr", ifCommitReg(trueCommitCnt))
1304  XSPerfRolling("ipc", ifCommitReg(trueCommitCnt), 1000, clock, reset)
1305  XSPerfRolling("cpi", perfCnt = 1.U /*Cycle*/ , eventTrigger = ifCommitReg(trueCommitCnt), granularity = 1000, clock, reset)
1306  XSPerfAccumulate("commitInstrFused", ifCommitReg(fuseCommitCnt))
1307  val commitIsLoad = io.commits.info.map(_.commitType).map(_ === CommitType.LOAD)
1308  val commitLoadValid = io.commits.commitValid.zip(commitIsLoad).map { case (v, t) => v && t }
1309  XSPerfAccumulate("commitInstrLoad", ifCommit(PopCount(commitLoadValid)))
1310  val commitIsBranch = io.commits.info.map(_.commitType).map(_ === CommitType.BRANCH)
1311  val commitBranchValid = io.commits.commitValid.zip(commitIsBranch).map { case (v, t) => v && t }
1312  XSPerfAccumulate("commitInstrBranch", ifCommit(PopCount(commitBranchValid)))
1313  val commitIsStore = io.commits.info.map(_.commitType).map(_ === CommitType.STORE)
1314  XSPerfAccumulate("commitInstrStore", ifCommit(PopCount(io.commits.commitValid.zip(commitIsStore).map { case (v, t) => v && t })))
1315  XSPerfAccumulate("writeback", PopCount((0 until RobSize).map(i => robEntries(i).valid && robEntries(i).isWritebacked)))
1316  // XSPerfAccumulate("enqInstr", PopCount(io.dp1Req.map(_.fire)))
1317  // XSPerfAccumulate("d2rVnR", PopCount(io.dp1Req.map(p => p.valid && !p.ready)))
1318  XSPerfAccumulate("walkInstr", Mux(io.commits.isWalk, PopCount(io.commits.walkValid), 0.U))
1319  XSPerfAccumulate("walkCycleTotal", state === s_walk)
1320  XSPerfAccumulate("waitRabWalkEnd", state === s_walk && walkFinished && !rab.io.status.walkEnd)
1321  private val walkCycle = RegInit(0.U(8.W))
1322  private val waitRabWalkCycle = RegInit(0.U(8.W))
1323  walkCycle := Mux(io.redirect.valid, 0.U, Mux(state === s_walk, walkCycle + 1.U, 0.U))
1324  waitRabWalkCycle := Mux(state === s_walk && walkFinished, 0.U, Mux(state === s_walk, walkCycle + 1.U, 0.U))
1325
1326  XSPerfHistogram("walkRobCycleHist", walkCycle, state === s_walk && walkFinished, 0, 32)
1327  XSPerfHistogram("walkRabExtraCycleHist", waitRabWalkCycle, state === s_walk && walkFinished && rab.io.status.walkEnd, 0, 32)
1328  XSPerfHistogram("walkTotalCycleHist", walkCycle, state === s_walk && state_next === s_idle, 0, 32)
1329
1330  private val deqNotWritebacked = robEntries(deqPtr.value).valid && !robEntries(deqPtr.value).isWritebacked
1331  private val deqStdNotWritebacked = robEntries(deqPtr.value).valid && !robEntries(deqPtr.value).stdWritebacked
1332  private val deqUopNotWritebacked = robEntries(deqPtr.value).valid && !robEntries(deqPtr.value).isUopWritebacked
1333  private val deqHeadInfo = debug_microOp(deqPtr.value)
1334  val deqUopCommitType = debug_microOp(deqPtr.value).commitType
1335
1336  XSPerfAccumulate("waitAluCycle", deqNotWritebacked && deqHeadInfo.fuType === FuType.alu.U)
1337  XSPerfAccumulate("waitMulCycle", deqNotWritebacked && deqHeadInfo.fuType === FuType.mul.U)
1338  XSPerfAccumulate("waitDivCycle", deqNotWritebacked && deqHeadInfo.fuType === FuType.div.U)
1339  XSPerfAccumulate("waitBrhCycle", deqNotWritebacked && deqHeadInfo.fuType === FuType.brh.U)
1340  XSPerfAccumulate("waitJmpCycle", deqNotWritebacked && deqHeadInfo.fuType === FuType.jmp.U)
1341  XSPerfAccumulate("waitCsrCycle", deqNotWritebacked && deqHeadInfo.fuType === FuType.csr.U)
1342  XSPerfAccumulate("waitFenCycle", deqNotWritebacked && deqHeadInfo.fuType === FuType.fence.U)
1343  XSPerfAccumulate("waitBkuCycle", deqNotWritebacked && deqHeadInfo.fuType === FuType.bku.U)
1344  XSPerfAccumulate("waitLduCycle", deqNotWritebacked && deqHeadInfo.fuType === FuType.ldu.U)
1345  XSPerfAccumulate("waitStuCycle", deqNotWritebacked && deqHeadInfo.fuType === FuType.stu.U)
1346  XSPerfAccumulate("waitStaCycle", deqUopNotWritebacked && deqHeadInfo.fuType === FuType.stu.U)
1347  XSPerfAccumulate("waitStdCycle", deqStdNotWritebacked && deqHeadInfo.fuType === FuType.stu.U)
1348  XSPerfAccumulate("waitAtmCycle", deqStdNotWritebacked && deqHeadInfo.fuType === FuType.mou.U)
1349
1350  XSPerfAccumulate("waitVfaluCycle", deqStdNotWritebacked && deqHeadInfo.fuType === FuType.vfalu.U)
1351  XSPerfAccumulate("waitVfmaCycle", deqStdNotWritebacked && deqHeadInfo.fuType === FuType.vfma.U)
1352  XSPerfAccumulate("waitVfdivCycle", deqStdNotWritebacked && deqHeadInfo.fuType === FuType.vfdiv.U)
1353
1354  val vfalufuop = Seq(VfaluType.vfadd, VfaluType.vfwadd, VfaluType.vfwadd_w, VfaluType.vfsub, VfaluType.vfwsub, VfaluType.vfwsub_w, VfaluType.vfmin, VfaluType.vfmax,
1355    VfaluType.vfmerge, VfaluType.vfmv, VfaluType.vfsgnj, VfaluType.vfsgnjn, VfaluType.vfsgnjx, VfaluType.vfeq, VfaluType.vfne, VfaluType.vflt, VfaluType.vfle, VfaluType.vfgt,
1356    VfaluType.vfge, VfaluType.vfclass, VfaluType.vfmv_f_s, VfaluType.vfmv_s_f, VfaluType.vfredusum, VfaluType.vfredmax, VfaluType.vfredmin, VfaluType.vfredosum, VfaluType.vfwredosum)
1357
1358  vfalufuop.zipWithIndex.map{
1359    case(fuoptype,i) =>  XSPerfAccumulate(s"waitVfalu_${i}Cycle", deqStdNotWritebacked && deqHeadInfo.fuOpType === fuoptype && deqHeadInfo.fuType === FuType.vfalu.U)
1360  }
1361
1362
1363
1364  XSPerfAccumulate("waitNormalCycle", deqNotWritebacked && deqUopCommitType === CommitType.NORMAL)
1365  XSPerfAccumulate("waitBranchCycle", deqNotWritebacked && deqUopCommitType === CommitType.BRANCH)
1366  XSPerfAccumulate("waitLoadCycle", deqNotWritebacked && deqUopCommitType === CommitType.LOAD)
1367  XSPerfAccumulate("waitStoreCycle", deqNotWritebacked && deqUopCommitType === CommitType.STORE)
1368  XSPerfAccumulate("robHeadPC", io.commits.info(0).debug_pc.getOrElse(0.U))
1369  XSPerfAccumulate("commitCompressCntAll", PopCount(io.commits.commitValid.zip(io.commits.info).map { case (valid, info) => io.commits.isCommit && valid && info.instrSize > 1.U }))
1370  (2 to RenameWidth).foreach(i =>
1371    XSPerfAccumulate(s"commitCompressCnt${i}", PopCount(io.commits.commitValid.zip(io.commits.info).map { case (valid, info) => io.commits.isCommit && valid && info.instrSize === i.U }))
1372  )
1373  XSPerfAccumulate("compressSize", io.commits.commitValid.zip(io.commits.info).map { case (valid, info) => Mux(io.commits.isCommit && valid && info.instrSize > 1.U, info.instrSize, 0.U) }.reduce(_ +& _))
1374  val dispatchLatency = commitDebugUop.map(uop => uop.debugInfo.dispatchTime - uop.debugInfo.renameTime)
1375  val enqRsLatency = commitDebugUop.map(uop => uop.debugInfo.enqRsTime - uop.debugInfo.dispatchTime)
1376  val selectLatency = commitDebugUop.map(uop => uop.debugInfo.selectTime - uop.debugInfo.enqRsTime)
1377  val issueLatency = commitDebugUop.map(uop => uop.debugInfo.issueTime - uop.debugInfo.selectTime)
1378  val executeLatency = commitDebugUop.map(uop => uop.debugInfo.writebackTime - uop.debugInfo.issueTime)
1379  val rsFuLatency = commitDebugUop.map(uop => uop.debugInfo.writebackTime - uop.debugInfo.enqRsTime)
1380  val commitLatency = commitDebugUop.map(uop => timer - uop.debugInfo.writebackTime)
1381
1382  def latencySum(cond: Seq[Bool], latency: Seq[UInt]): UInt = {
1383    cond.zip(latency).map(x => Mux(x._1, x._2, 0.U)).reduce(_ +& _)
1384  }
1385
1386  for (fuType <- FuType.functionNameMap.keys) {
1387    val fuName = FuType.functionNameMap(fuType)
1388    val commitIsFuType = io.commits.commitValid.zip(commitDebugUop).map(x => x._1 && x._2.fuType === fuType.U)
1389    XSPerfRolling(s"ipc_futype_${fuName}", ifCommit(PopCount(commitIsFuType)), 1000, clock, reset)
1390    XSPerfAccumulate(s"${fuName}_instr_cnt", ifCommit(PopCount(commitIsFuType)))
1391    XSPerfAccumulate(s"${fuName}_latency_dispatch", ifCommit(latencySum(commitIsFuType, dispatchLatency)))
1392    XSPerfAccumulate(s"${fuName}_latency_enq_rs", ifCommit(latencySum(commitIsFuType, enqRsLatency)))
1393    XSPerfAccumulate(s"${fuName}_latency_select", ifCommit(latencySum(commitIsFuType, selectLatency)))
1394    XSPerfAccumulate(s"${fuName}_latency_issue", ifCommit(latencySum(commitIsFuType, issueLatency)))
1395    XSPerfAccumulate(s"${fuName}_latency_execute", ifCommit(latencySum(commitIsFuType, executeLatency)))
1396    XSPerfAccumulate(s"${fuName}_latency_enq_rs_execute", ifCommit(latencySum(commitIsFuType, rsFuLatency)))
1397    XSPerfAccumulate(s"${fuName}_latency_commit", ifCommit(latencySum(commitIsFuType, commitLatency)))
1398  }
1399  XSPerfAccumulate(s"redirect_use_snapshot", io.redirect.valid && io.snpt.useSnpt)
1400
1401  // top-down info
1402  io.debugTopDown.toCore.robHeadVaddr.valid := debug_lsTopdownInfo(deqPtr.value).s1.vaddr_valid
1403  io.debugTopDown.toCore.robHeadVaddr.bits := debug_lsTopdownInfo(deqPtr.value).s1.vaddr_bits
1404  io.debugTopDown.toCore.robHeadPaddr.valid := debug_lsTopdownInfo(deqPtr.value).s2.paddr_valid
1405  io.debugTopDown.toCore.robHeadPaddr.bits := debug_lsTopdownInfo(deqPtr.value).s2.paddr_bits
1406  io.debugTopDown.toDispatch.robTrueCommit := ifCommitReg(trueCommitCnt)
1407  io.debugTopDown.toDispatch.robHeadLsIssue := debug_lsIssue(deqPtr.value)
1408  io.debugTopDown.robHeadLqIdx.valid := debug_lqIdxValid(deqPtr.value)
1409  io.debugTopDown.robHeadLqIdx.bits := debug_microOp(deqPtr.value).lqIdx
1410
1411  // rolling
1412  io.debugRolling.robTrueCommit := ifCommitReg(trueCommitCnt)
1413
1414  /**
1415   * DataBase info:
1416   * log trigger is at writeback valid
1417   * */
1418  if (!env.FPGAPlatform) {
1419    val instTableName = "InstTable" + p(XSCoreParamsKey).HartId.toString
1420    val instSiteName = "Rob" + p(XSCoreParamsKey).HartId.toString
1421    val debug_instTable = ChiselDB.createTable(instTableName, new InstInfoEntry)
1422    for (wb <- exuWBs) {
1423      when(wb.valid) {
1424        val debug_instData = Wire(new InstInfoEntry)
1425        val idx = wb.bits.robIdx.value
1426        debug_instData.robIdx := idx
1427        debug_instData.dvaddr := wb.bits.debug.vaddr
1428        debug_instData.dpaddr := wb.bits.debug.paddr
1429        debug_instData.issueTime := wb.bits.debugInfo.issueTime
1430        debug_instData.writebackTime := wb.bits.debugInfo.writebackTime
1431        debug_instData.dispatchLatency := wb.bits.debugInfo.dispatchTime - wb.bits.debugInfo.renameTime
1432        debug_instData.enqRsLatency := wb.bits.debugInfo.enqRsTime - wb.bits.debugInfo.dispatchTime
1433        debug_instData.selectLatency := wb.bits.debugInfo.selectTime - wb.bits.debugInfo.enqRsTime
1434        debug_instData.issueLatency := wb.bits.debugInfo.issueTime - wb.bits.debugInfo.selectTime
1435        debug_instData.executeLatency := wb.bits.debugInfo.writebackTime - wb.bits.debugInfo.issueTime
1436        debug_instData.rsFuLatency := wb.bits.debugInfo.writebackTime - wb.bits.debugInfo.enqRsTime
1437        debug_instData.tlbLatency := wb.bits.debugInfo.tlbRespTime - wb.bits.debugInfo.tlbFirstReqTime
1438        debug_instData.exceptType := Cat(wb.bits.exceptionVec.getOrElse(ExceptionVec(false.B)))
1439        debug_instData.lsInfo := debug_lsInfo(idx)
1440        // debug_instData.globalID := wb.bits.uop.ctrl.debug_globalID
1441        // debug_instData.instType := wb.bits.uop.ctrl.fuType
1442        // debug_instData.ivaddr := wb.bits.uop.cf.pc
1443        // debug_instData.mdpInfo.ssid := wb.bits.uop.cf.ssid
1444        // debug_instData.mdpInfo.waitAllStore := wb.bits.uop.cf.loadWaitStrict && wb.bits.uop.cf.loadWaitBit
1445        debug_instTable.log(
1446          data = debug_instData,
1447          en = wb.valid,
1448          site = instSiteName,
1449          clock = clock,
1450          reset = reset
1451        )
1452      }
1453    }
1454  }
1455
1456  val debug_VecOtherPdest = RegInit(VecInit.fill(RobSize)(VecInit.fill(8)(0.U(PhyRegIdxWidth.W))))
1457
1458  vldWBs.map{ vldWb =>
1459    val vldWbPdest  = vldWb.bits.pdest
1460    val vldWbRobIdx = vldWb.bits.robIdx.value
1461    val vldWbvdIdx  = vldWb.bits.vls.get.vdIdx
1462    when (vldWb.fire && robEntries(vldWbRobIdx).valid && (vldWb.bits.vecWen.get || vldWb.bits.v0Wen.get)) {
1463      debug_VecOtherPdest(vldWbRobIdx)(vldWbvdIdx) := vldWbPdest
1464    }
1465  }
1466
1467  //difftest signals
1468  val firstValidCommit = (deqPtr + PriorityMux(io.commits.commitValid, VecInit(List.tabulate(CommitWidth)(_.U(log2Up(CommitWidth).W))))).value
1469
1470  val wdata = Wire(Vec(CommitWidth, UInt(XLEN.W)))
1471  val wpc = Wire(Vec(CommitWidth, UInt(XLEN.W)))
1472
1473  for (i <- 0 until CommitWidth) {
1474    val idx = deqPtrVec(i).value
1475    wdata(i) := debug_exuData(idx)
1476    wpc(i) := SignExt(commitDebugUop(i).pc, XLEN)
1477  }
1478
1479  if (env.EnableDifftest || env.AlwaysBasicDiff) {
1480    // These are the structures used by difftest only and should be optimized after synthesis.
1481    val dt_eliminatedMove = Mem(RobSize, Bool())
1482    val dt_isRVC = Mem(RobSize, Bool())
1483    val dt_exuDebug = Reg(Vec(RobSize, new DebugBundle))
1484    for (i <- 0 until RenameWidth) {
1485      when(canEnqueue(i)) {
1486        dt_eliminatedMove(allocatePtrVec(i).value) := io.enq.req(i).bits.eliminatedMove
1487        dt_isRVC(allocatePtrVec(i).value) := io.enq.req(i).bits.preDecodeInfo.isRVC
1488      }
1489    }
1490    for (wb <- exuWBs) {
1491      when(wb.valid) {
1492        val wbIdx = wb.bits.robIdx.value
1493        dt_exuDebug(wbIdx) := wb.bits.debug
1494      }
1495    }
1496    // Always instantiate basic difftest modules.
1497    for (i <- 0 until CommitWidth) {
1498      val uop = commitDebugUop(i)
1499      val commitInfo = io.commits.info(i)
1500      val ptr = deqPtrVec(i).value
1501      val exuOut = dt_exuDebug(ptr)
1502      val eliminatedMove = dt_eliminatedMove(ptr)
1503      val isRVC = dt_isRVC(ptr)
1504      val instr = uop.instr.asTypeOf(new XSInstBitFields)
1505      val isVLoad = instr.isVecLoad
1506
1507      val difftest = DifftestModule(new DiffInstrCommit(MaxPhyRegs), delay = 3, dontCare = true)
1508      val dt_skip = Mux(eliminatedMove, false.B, exuOut.isSkipDiff)
1509      difftest.coreid := io.hartId
1510      difftest.index := i.U
1511      difftest.valid := io.commits.commitValid(i) && io.commits.isCommit
1512      difftest.skip := dt_skip
1513      difftest.isRVC := isRVC
1514      difftest.rfwen := io.commits.commitValid(i) && commitInfo.rfWen && commitInfo.debug_ldest.get =/= 0.U
1515      difftest.fpwen := io.commits.commitValid(i) && uop.fpWen
1516      difftest.vecwen := io.commits.commitValid(i) && uop.vecWen
1517      difftest.v0wen := io.commits.commitValid(i) && (uop.v0Wen || isVLoad && instr.VD === 0.U)
1518      difftest.wpdest := commitInfo.debug_pdest.get
1519      difftest.wdest := Mux(isVLoad, instr.VD, commitInfo.debug_ldest.get)
1520      difftest.otherwpdest := debug_VecOtherPdest(ptr)
1521      difftest.nFused := CommitType.isFused(commitInfo.commitType).asUInt + commitInfo.instrSize - 1.U
1522      when(difftest.valid) {
1523        assert(CommitType.isFused(commitInfo.commitType).asUInt + commitInfo.instrSize >= 1.U)
1524      }
1525      if (env.EnableDifftest) {
1526        val uop = commitDebugUop(i)
1527        difftest.pc := SignExt(uop.pc, XLEN)
1528        difftest.instr := uop.instr
1529        difftest.robIdx := ZeroExt(ptr, 10)
1530        difftest.lqIdx := ZeroExt(uop.lqIdx.value, 7)
1531        difftest.sqIdx := ZeroExt(uop.sqIdx.value, 7)
1532        difftest.isLoad := io.commits.info(i).commitType === CommitType.LOAD
1533        difftest.isStore := io.commits.info(i).commitType === CommitType.STORE
1534        // Check LoadEvent only when isAmo or isLoad and skip MMIO
1535        val difftestLoadEvent = DifftestModule(new DiffLoadEvent, delay = 3)
1536        difftestLoadEvent.coreid := io.hartId
1537        difftestLoadEvent.index := i.U
1538        val loadCheck = (FuType.isAMO(uop.fuType) || FuType.isLoad(uop.fuType) || isVLoad) && !dt_skip
1539        difftestLoadEvent.valid    := io.commits.commitValid(i) && io.commits.isCommit && loadCheck
1540        difftestLoadEvent.paddr    := exuOut.paddr
1541        difftestLoadEvent.opType   := uop.fuOpType
1542        difftestLoadEvent.isAtomic := FuType.isAMO(uop.fuType)
1543        difftestLoadEvent.isLoad   := FuType.isLoad(uop.fuType)
1544        difftestLoadEvent.isVLoad  := isVLoad
1545      }
1546    }
1547  }
1548
1549  if (env.EnableDifftest || env.AlwaysBasicDiff) {
1550    val dt_isXSTrap = Mem(RobSize, Bool())
1551    for (i <- 0 until RenameWidth) {
1552      when(canEnqueue(i)) {
1553        dt_isXSTrap(allocatePtrVec(i).value) := io.enq.req(i).bits.isXSTrap
1554      }
1555    }
1556    val trapVec = io.commits.commitValid.zip(deqPtrVec).map { case (v, d) =>
1557      io.commits.isCommit && v && dt_isXSTrap(d.value)
1558    }
1559    val hitTrap = trapVec.reduce(_ || _)
1560    val difftest = DifftestModule(new DiffTrapEvent, dontCare = true)
1561    difftest.coreid := io.hartId
1562    difftest.hasTrap := hitTrap
1563    difftest.cycleCnt := timer
1564    difftest.instrCnt := instrCnt
1565    difftest.hasWFI := hasWFI
1566
1567    if (env.EnableDifftest) {
1568      val trapCode = PriorityMux(wdata.zip(trapVec).map(x => x._2 -> x._1))
1569      val trapPC = SignExt(PriorityMux(wpc.zip(trapVec).map(x => x._2 -> x._1)), XLEN)
1570      difftest.code := trapCode
1571      difftest.pc := trapPC
1572    }
1573  }
1574
1575  //store evetn difftest information
1576  io.storeDebugInfo := DontCare
1577  if (env.EnableDifftest) {
1578    io.storeDebugInfo.map{port =>
1579      port.pc := debug_microOp(port.robidx.value).pc
1580    }
1581  }
1582
1583  val brhMispred = PopCount(branchWBs.map(wb => wb.valid & wb.bits.redirect.get.valid))
1584  val jmpMispred = PopCount(jmpWBs.map(wb => wb.valid && wb.bits.redirect.get.valid))
1585  val misPred = brhMispred +& jmpMispred
1586
1587  XSPerfAccumulate("br_mis_pred", misPred)
1588
1589  val commitLoadVec = VecInit(commitLoadValid)
1590  val commitBranchVec = VecInit(commitBranchValid)
1591  val commitStoreVec = VecInit(io.commits.commitValid.zip(commitIsStore).map { case (v, t) => v && t })
1592  val perfEvents = Seq(
1593    ("rob_interrupt_num      ", io.flushOut.valid && intrEnable),
1594    ("rob_exception_num      ", io.flushOut.valid && deqHasException),
1595    ("rob_flush_pipe_num     ", io.flushOut.valid && isFlushPipe),
1596    ("rob_replay_inst_num    ", io.flushOut.valid && isFlushPipe && deqHasReplayInst),
1597    ("rob_commitUop          ", ifCommit(commitCnt)),
1598    ("rob_commitInstr        ", ifCommitReg(trueCommitCnt)),
1599    ("rob_commitInstrFused   ", ifCommitReg(fuseCommitCnt)),
1600    ("rob_commitInstrLoad    ", ifCommitReg(PopCount(RegEnable(commitLoadVec, isCommit)))),
1601    ("rob_commitInstrBranch  ", ifCommitReg(PopCount(RegEnable(commitBranchVec, isCommit)))),
1602    ("rob_commitInstrStore   ", ifCommitReg(PopCount(RegEnable(commitStoreVec, isCommit)))),
1603    ("rob_walkInstr          ", Mux(io.commits.isWalk, PopCount(io.commits.walkValid), 0.U)),
1604    ("rob_walkCycle          ", (state === s_walk)),
1605    ("rob_1_4_valid          ", numValidEntries <= (RobSize / 4).U),
1606    ("rob_2_4_valid          ", numValidEntries > (RobSize / 4).U && numValidEntries <= (RobSize / 2).U),
1607    ("rob_3_4_valid          ", numValidEntries > (RobSize / 2).U && numValidEntries <= (RobSize * 3 / 4).U),
1608    ("rob_4_4_valid          ", numValidEntries > (RobSize * 3 / 4).U),
1609    ("BR_MIS_PRED            ", misPred),
1610    ("TOTAL_FLUSH            ", io.flushOut.valid)
1611  )
1612  generatePerfEvent()
1613
1614  // max commit-stuck cycle
1615  val deqismmio = Mux(robEntries(deqPtr.value).valid, robEntries(deqPtr.value).mmio, false.B)
1616  val commitStuck = (!io.commits.commitValid.reduce(_ || _) || !io.commits.isCommit) && !deqismmio
1617  val commitStuckCycle = RegInit(0.U(log2Up(maxCommitStuck).W))
1618  when(commitStuck) {
1619    commitStuckCycle := commitStuckCycle + 1.U
1620  }.elsewhen(!commitStuck && RegNext(commitStuck)) {
1621    commitStuckCycle := 0.U
1622  }
1623  // check if stuck > 2^maxCommitStuckCycle
1624  val commitStuck_overflow = commitStuckCycle.andR
1625  val criticalErrors = Seq(
1626    ("rob_commit_stuck  ", commitStuck_overflow),
1627  )
1628  generateCriticalErrors()
1629
1630
1631  // dontTouch for debug
1632  if (backendParams.debugEn) {
1633    dontTouch(enqPtrVec)
1634    dontTouch(deqPtrVec)
1635    dontTouch(robEntries)
1636    dontTouch(robDeqGroup)
1637    dontTouch(robBanks)
1638    dontTouch(robBanksRaddrThisLine)
1639    dontTouch(robBanksRaddrNextLine)
1640    dontTouch(robBanksRdataThisLine)
1641    dontTouch(robBanksRdataNextLine)
1642    dontTouch(robBanksRdataThisLineUpdate)
1643    dontTouch(robBanksRdataNextLineUpdate)
1644    dontTouch(needUpdate)
1645    val exceptionWBsVec = MixedVecInit(exceptionWBs)
1646    dontTouch(exceptionWBsVec)
1647    dontTouch(commit_wDeqGroup)
1648    dontTouch(commit_vDeqGroup)
1649    dontTouch(commitSizeSumSeq)
1650    dontTouch(walkSizeSumSeq)
1651    dontTouch(commitSizeSumCond)
1652    dontTouch(walkSizeSumCond)
1653    dontTouch(commitSizeSum)
1654    dontTouch(walkSizeSum)
1655    dontTouch(realDestSizeSeq)
1656    dontTouch(walkDestSizeSeq)
1657    dontTouch(io.commits)
1658    dontTouch(commitIsVTypeVec)
1659    dontTouch(walkIsVTypeVec)
1660    dontTouch(commitValidThisLine)
1661    dontTouch(commitReadAddr_next)
1662    dontTouch(donotNeedWalk)
1663    dontTouch(walkPtrVec_next)
1664    dontTouch(walkPtrVec)
1665    dontTouch(deqPtrVec_next)
1666    dontTouch(deqPtrVecForWalk)
1667    dontTouch(snapPtrReadBank)
1668    dontTouch(snapPtrVecForWalk)
1669    dontTouch(shouldWalkVec)
1670    dontTouch(walkFinished)
1671    dontTouch(changeBankAddrToDeqPtr)
1672  }
1673  if (env.EnableDifftest) {
1674    io.commits.info.map(info => dontTouch(info.debug_pc.get))
1675  }
1676}
1677