1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{GTimer, GatedValidRegNext, HasCircularQueuePtrHelper, SelectOne, XSPerfAccumulate, XSPerfHistogram} 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.issue.EntryBundles._ 11import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD} 12import xiangshan.backend.datapath.DataConfig._ 13import xiangshan.backend.datapath.DataSource 14import xiangshan.backend.fu.{FuConfig, FuType} 15import xiangshan.backend.rob.RobPtr 16import xiangshan.backend.datapath.NewPipelineConnect 17import xiangshan.backend.fu.vector.Bundles.VSew 18import xiangshan.mem.{LqPtr, SqPtr} 19import xiangshan.mem.Bundles.MemWaitUpdateReq 20 21class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 22 override def shouldBeInlined: Boolean = false 23 24 implicit val iqParams: IssueBlockParams = params 25 lazy val module: IssueQueueImp = iqParams.schdType match { 26 case IntScheduler() => new IssueQueueIntImp(this) 27 case FpScheduler() => new IssueQueueFpImp(this) 28 case VfScheduler() => new IssueQueueVfImp(this) 29 case MemScheduler() => 30 if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this) 31 else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this) 32 else new IssueQueueIntImp(this) 33 case _ => null 34 } 35} 36 37class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle { 38 val empty = Output(Bool()) 39 val full = Output(Bool()) 40 val validCnt = Output(UInt(log2Ceil(numEntries + 1).W)) 41 val leftVec = Output(Vec(numEnq + 1, Bool())) 42} 43 44class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle 45 46class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 47 // Inputs 48 val flush = Flipped(ValidIO(new Redirect)) 49 val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst))) 50 51 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 52 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 53 val og2Resp = Option.when(params.needOg2Resp)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 54 val finalIssueResp = Option.when(params.LdExuCnt > 0 || params.VlduCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 55 val memAddrIssueResp = Option.when(params.LdExuCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 56 val vecLoadIssueResp = Option.when(params.VlduCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 57 val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle) 58 val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle) 59 val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 60 val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 61 val wakeupFromWBDelayed: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 62 val wakeupFromIQDelayed: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 63 val vlFromIntIsZero = Input(Bool()) 64 val vlFromIntIsVlmax = Input(Bool()) 65 val vlFromVfIsZero = Input(Bool()) 66 val vlFromVfIsVlmax = Input(Bool()) 67 val og0Cancel = Input(ExuVec()) 68 val og1Cancel = Input(ExuVec()) 69 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 70 val replaceRCIdx = Option.when(params.needWriteRegCache)(Vec(params.numDeq, Input(UInt(RegCacheIdxWidth.W)))) 71 72 // Outputs 73 val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle 74 val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries)) 75 val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W))) 76 // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq)) 77 78 val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType 79 def allWakeUp = wakeupFromWB ++ wakeupFromIQ 80} 81 82class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams) 83 extends LazyModuleImp(wrapper) 84 with HasXSParameter { 85 86 override def desiredName: String = s"${params.getIQName}" 87 88 println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " + 89 s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " + 90 s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " + 91 s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " + 92 s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " + 93 s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}") 94 95 require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports") 96 require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports") 97 require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq") 98 require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq") 99 100 val deqFuCfgs : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs) 101 val allDeqFuCfgs : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs) 102 val fuCfgsCnt : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) } 103 val commonFuCfgs : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq 104 val wakeupFuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.wakeUpFuLatencyMap) 105 106 println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${wakeupFuLatencyMaps}") 107 println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}") 108 if (params.hasIQWakeUp) { 109 val exuSourcesEncodeString = params.wakeUpSourceExuIdx.map(x => 1 << x).reduce(_ + _).toBinaryString 110 println(s"[IssueQueueImp] ${params.getIQName} exuSourcesWidth: ${ExuSource().value.getWidth}, " + 111 s"exuSourcesEncodeMask: ${"0" * (p(XSCoreParamsKey).backendParams.numExu - exuSourcesEncodeString.length) + exuSourcesEncodeString}") 112 } 113 114 lazy val io = IO(new IssueQueueIO()) 115 116 // Modules 117 val entries = Module(new Entries) 118 val fuBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.latencyValMax > 0)(Module(new FuBusyTableWrite(x.fuLatencyMap))) } 119 val fuBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.latencyValMax > 0)(Module(new FuBusyTableRead(x.fuLatencyMap))) } 120 val intWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.intLatencyCertain)(Module(new FuBusyTableWrite(x.intFuLatencyMap))) } 121 val intWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.intLatencyCertain)(Module(new FuBusyTableRead(x.intFuLatencyMap))) } 122 val fpWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.fpLatencyCertain)(Module(new FuBusyTableWrite(x.fpFuLatencyMap))) } 123 val fpWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.fpLatencyCertain)(Module(new FuBusyTableRead(x.fpFuLatencyMap))) } 124 val vfWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.vfLatencyCertain)(Module(new FuBusyTableWrite(x.vfFuLatencyMap))) } 125 val vfWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.vfLatencyCertain)(Module(new FuBusyTableRead(x.vfFuLatencyMap))) } 126 val v0WbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.v0LatencyCertain)(Module(new FuBusyTableWrite(x.v0FuLatencyMap))) } 127 val v0WbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.v0LatencyCertain)(Module(new FuBusyTableRead(x.v0FuLatencyMap))) } 128 val vlWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.vlLatencyCertain)(Module(new FuBusyTableWrite(x.vlFuLatencyMap))) } 129 val vlWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.vlLatencyCertain)(Module(new FuBusyTableRead(x.vlFuLatencyMap))) } 130 131 class WakeupQueueFlush extends Bundle { 132 val redirect = ValidIO(new Redirect) 133 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO) 134 val og0Fail = Output(Bool()) 135 val og1Fail = Output(Bool()) 136 } 137 138 private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = { 139 val redirectFlush = exuInput.robIdx.needFlush(flush.redirect) 140 val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel) 141 val ogFailFlush = stage match { 142 case 1 => flush.og0Fail 143 case 2 => flush.og1Fail 144 case _ => false.B 145 } 146 redirectFlush || loadDependencyFlush || ogFailFlush 147 } 148 149 private def modificationFunc(exuInput: ExuInput): ExuInput = { 150 val newExuInput = WireDefault(exuInput) 151 newExuInput.loadDependency match { 152 case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1) 153 case None => 154 } 155 newExuInput 156 } 157 158 private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = { 159 val lastExuInput = WireDefault(exuInput) 160 val newExuInput = WireDefault(newInput) 161 newExuInput.elements.foreach { case (name, data) => 162 if (lastExuInput.elements.contains(name)) { 163 data := lastExuInput.elements(name) 164 } 165 } 166 if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) { 167 newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest) 168 } 169 if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) { 170 newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 171 } 172 if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) { 173 newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get) 174 } 175 if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) { 176 newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.vecWen.get) 177 } 178 if (newExuInput.v0WenCopy.nonEmpty && !lastExuInput.v0WenCopy.nonEmpty) { 179 newExuInput.v0WenCopy.get.foreach(_ := lastExuInput.v0Wen.get) 180 } 181 if (newExuInput.vlWenCopy.nonEmpty && !lastExuInput.vlWenCopy.nonEmpty) { 182 newExuInput.vlWenCopy.get.foreach(_ := lastExuInput.vlWen.get) 183 } 184 if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) { 185 newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get) 186 } 187 newExuInput 188 } 189 190 val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => Option.when(x.isIQWakeUpSource && !x.hasLoadExu)(Module( 191 new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc) 192 ))} 193 val deqBeforeDly = Wire(params.genIssueDecoupledBundle) 194 195 val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable) 196 val fpWbBusyTableIn = io.wbBusyTableRead.map(_.fpWbBusyTable) 197 val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable) 198 val v0WbBusyTableIn = io.wbBusyTableRead.map(_.v0WbBusyTable) 199 val vlWbBusyTableIn = io.wbBusyTableRead.map(_.vlWbBusyTable) 200 201 val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable) 202 val fpWbBusyTableOut = io.wbBusyTableWrite.map(_.fpWbBusyTable) 203 val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable) 204 val v0WbBusyTableOut = io.wbBusyTableWrite.map(_.v0WbBusyTable) 205 val vlWbBusyTableOut = io.wbBusyTableWrite.map(_.vlWbBusyTable) 206 207 val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet) 208 val fpDeqRespSetOut = io.wbBusyTableWrite.map(_.fpDeqRespSet) 209 val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet) 210 val v0DeqRespSetOut = io.wbBusyTableWrite.map(_.v0DeqRespSet) 211 val vlDeqRespSetOut = io.wbBusyTableWrite.map(_.vlDeqRespSet) 212 213 val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 214 val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 215 val fpWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 216 val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 217 val v0WbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 218 val vlWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 219 220 val s0_enqValidVec = io.enq.map(_.valid) 221 val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool())) 222 val s0_enqNotFlush = !io.flush.valid 223 val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits))) 224 val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady 225 226 227 val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool())) 228 val finalDeqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 229 230 val validVec = VecInit(entries.io.valid.asBools) 231 val issuedVec = VecInit(entries.io.issued.asBools) 232 val requestForTrans = VecInit(validVec.zip(issuedVec).map(x => x._1 && !x._2)) 233 val canIssueVec = VecInit(entries.io.canIssue.asBools) 234 dontTouch(canIssueVec) 235 val deqFirstIssueVec = entries.io.isFirstIssue 236 237 val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources 238 val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources))) 239 val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency 240 val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency))) 241 // (entryIdx)(srcIdx) 242 val exuSources: Option[Vec[Vec[ExuSource]]] = entries.io.exuSources 243 // (deqIdx)(srcIdx) 244 val finalExuSources: Option[Vec[Vec[ExuSource]]] = exuSources.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 245 246 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 247 val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 248 val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 249 val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 250 251 //deq 252 val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W)))) 253 val simpEntryOldestSel = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W))))) 254 val compEntryOldestSel = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W))))) 255 val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W)))) 256 val deqSelValidVec = Wire(Vec(params.numDeq, Bool())) 257 val deqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 258 val cancelDeqVec = Wire(Vec(params.numDeq, Bool())) 259 260 val subDeqSelValidVec = Option.when(params.deqFuSame)(Wire(Vec(params.numDeq, Bool()))) 261 val subDeqSelOHVec = Option.when(params.deqFuSame)(Wire(Vec(params.numDeq, UInt(params.numEntries.W)))) 262 val subDeqRequest = Option.when(params.deqFuSame)(Wire(UInt(params.numEntries.W))) 263 264 //trans 265 val simpEntryEnqSelVec = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numEnq, UInt(params.numSimp.W)))) 266 val compEntryEnqSelVec = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numEnq, UInt(params.numComp.W)))) 267 val othersEntryEnqSelVec = Option.when(params.isAllComp || params.isAllSimp)(Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W)))) 268 val simpAgeDetectRequest = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W)))) 269 simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get)) 270 271 // when vf exu (with og2) wake up int/mem iq (without og2), the wakeup signals should delay 1 cycle 272 // as vf exu's min latency is 1, we do not need consider og0cancel 273 val wakeupFromIQ = Wire(chiselTypeOf(io.wakeupFromIQ)) 274 wakeupFromIQ.zip(io.wakeupFromIQ).foreach { case (w, w_src) => 275 if (!params.inVfSchd && params.readVfRf && params.hasWakeupFromVf && w_src.bits.params.isVfExeUnit) { 276 val noCancel = !LoadShouldCancel(Some(w_src.bits.loadDependency), io.ldCancel) 277 w := RegNext(Mux(noCancel, w_src, 0.U.asTypeOf(w))) 278 w.bits.loadDependency.zip(w_src.bits.loadDependency).foreach{ case (ld, ld_src) => ld := RegNext(Mux(noCancel, ld_src << 1, 0.U.asTypeOf(ld))) } 279 } else { 280 w := w_src 281 } 282 } 283 val wakeupFromIQDelayed = Wire(chiselTypeOf(io.wakeupFromIQDelayed)) 284 wakeupFromIQDelayed.zip(io.wakeupFromIQDelayed).foreach { case (w, w_src) => 285 if (!params.inVfSchd && params.readVfRf && params.hasWakeupFromVf && w_src.bits.params.isVfExeUnit) { 286 val noCancel = !LoadShouldCancel(Some(w_src.bits.loadDependency), io.ldCancel) 287 w := RegNext(Mux(noCancel, w_src, 0.U.asTypeOf(w))) 288 w.bits.loadDependency.zip(w_src.bits.loadDependency).foreach { case (ld, ld_src) => ld := RegNext(Mux(noCancel, ld_src << 1, 0.U.asTypeOf(ld))) } 289 } else { 290 w := w_src 291 } 292 } 293 294 /** 295 * Connection of [[entries]] 296 */ 297 entries.io match { case entriesIO: EntriesIO => 298 entriesIO.flush := io.flush 299 entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) => 300 enq.valid := s0_doEnqSelValidVec(enqIdx) 301 enq.bits.status.robIdx := s0_enqBits(enqIdx).robIdx 302 enq.bits.status.fuType := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType)) 303 val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size) 304 for(j <- 0 until numLsrc) { 305 enq.bits.status.srcStatus(j).psrc := s0_enqBits(enqIdx).psrc(j) 306 enq.bits.status.srcStatus(j).srcType := s0_enqBits(enqIdx).srcType(j) 307 enq.bits.status.srcStatus(j).srcState := (if (j < 3) { 308 Mux(SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U), 309 SrcState.rdy, 310 s0_enqBits(enqIdx).srcState(j)) 311 } else { 312 s0_enqBits(enqIdx).srcState(j) 313 }) 314 enq.bits.status.srcStatus(j).dataSources.value := (if (j < 3) { 315 MuxCase(DataSource.reg, Seq( 316 (SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U)) -> DataSource.zero, 317 SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)) -> DataSource.imm, 318 (SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U)) -> DataSource.v0, 319 )) 320 } else { 321 MuxCase(DataSource.reg, Seq( 322 SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)) -> DataSource.imm, 323 )) 324 }) 325 enq.bits.status.srcStatus(j).srcLoadDependency := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x << 1)) 326 enq.bits.status.srcStatus(j).exuSources.foreach(_ := 0.U.asTypeOf(ExuSource())) 327 enq.bits.status.srcStatus(j).useRegCache.foreach(_ := s0_enqBits(enqIdx).useRegCache(j)) 328 enq.bits.status.srcStatus(j).regCacheIdx.foreach(_ := s0_enqBits(enqIdx).regCacheIdx(j)) 329 } 330 enq.bits.status.blocked := false.B 331 enq.bits.status.issued := false.B 332 enq.bits.status.firstIssue := false.B 333 enq.bits.status.issueTimer := "b11".U 334 enq.bits.status.deqPortIdx := 0.U 335 enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm) 336 enq.bits.payload := s0_enqBits(enqIdx) 337 } 338 entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) => 339 og0Resp := io.og0Resp(i) 340 } 341 entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) => 342 og1Resp := io.og1Resp(i) 343 } 344 if (params.needOg2Resp) { 345 entriesIO.og2Resp.get.zipWithIndex.foreach { case (og2Resp, i) => 346 og2Resp := io.og2Resp.get(i) 347 } 348 } 349 if (params.isLdAddrIQ || params.isHyAddrIQ) { 350 entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) => 351 finalIssueResp := io.finalIssueResp.get(i) 352 } 353 entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) => 354 memAddrIssueResp := io.memAddrIssueResp.get(i) 355 } 356 } 357 if (params.isVecLduIQ) { 358 entriesIO.vecLdIn.get.finalIssueResp.zipWithIndex.foreach { case (resp, i) => 359 resp := io.finalIssueResp.get(i) 360 } 361 entriesIO.vecLdIn.get.resp.zipWithIndex.foreach { case (resp, i) => 362 resp := io.vecLoadIssueResp.get(i) 363 } 364 } 365 for(deqIdx <- 0 until params.numDeq) { 366 entriesIO.deqReady(deqIdx) := deqBeforeDly(deqIdx).ready 367 entriesIO.deqSelOH(deqIdx).valid := deqSelValidVec(deqIdx) 368 entriesIO.deqSelOH(deqIdx).bits := deqSelOHVec(deqIdx) 369 entriesIO.enqEntryOldestSel(deqIdx) := enqEntryOldestSel(deqIdx) 370 entriesIO.simpEntryOldestSel.foreach(_(deqIdx) := simpEntryOldestSel.get(deqIdx)) 371 entriesIO.compEntryOldestSel.foreach(_(deqIdx) := compEntryOldestSel.get(deqIdx)) 372 entriesIO.othersEntryOldestSel.foreach(_(deqIdx) := othersEntryOldestSel(deqIdx)) 373 entriesIO.subDeqRequest.foreach(_(deqIdx) := subDeqRequest.get) 374 entriesIO.subDeqSelOH.foreach(_(deqIdx) := subDeqSelOHVec.get(deqIdx)) 375 } 376 entriesIO.wakeUpFromWB := io.wakeupFromWB 377 entriesIO.wakeUpFromIQ := wakeupFromIQ 378 entriesIO.wakeUpFromWBDelayed := io.wakeupFromWBDelayed 379 entriesIO.wakeUpFromIQDelayed := wakeupFromIQDelayed 380 entriesIO.vlFromIntIsZero := io.vlFromIntIsZero 381 entriesIO.vlFromIntIsVlmax := io.vlFromIntIsVlmax 382 entriesIO.vlFromVfIsZero := io.vlFromVfIsZero 383 entriesIO.vlFromVfIsVlmax := io.vlFromVfIsVlmax 384 entriesIO.og0Cancel := io.og0Cancel 385 entriesIO.og1Cancel := io.og1Cancel 386 entriesIO.ldCancel := io.ldCancel 387 entriesIO.simpEntryDeqSelVec.foreach(_ := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits))) 388 //output 389 fuTypeVec := entriesIO.fuType 390 deqEntryVec := entriesIO.deqEntry 391 cancelDeqVec := entriesIO.cancelDeqVec 392 simpEntryEnqSelVec.foreach(_ := entriesIO.simpEntryEnqSelVec.get) 393 compEntryEnqSelVec.foreach(_ := entriesIO.compEntryEnqSelVec.get) 394 othersEntryEnqSelVec.foreach(_ := entriesIO.othersEntryEnqSelVec.get) 395 } 396 397 398 s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready} 399 400 protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType => 401 FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType)) 402 ).reverse) 403 404 // if deq port can accept the uop 405 protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 406 Cat(fuTypeVec.map(fuType => 407 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)) 408 ).reverse) 409 } 410 411 protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 412 fuTypeVec.map(fuType => 413 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 414 } 415 416 canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) => 417 val mergeFuBusy = { 418 if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i)) 419 else canIssueVec.asUInt 420 } 421 val mergeIntWbBusy = { 422 if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i)) 423 else mergeFuBusy 424 } 425 val mergefpWbBusy = { 426 if (fpWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~fpWbBusyTableMask(i)) 427 else mergeIntWbBusy 428 } 429 val mergeVfWbBusy = { 430 if (vfWbBusyTableRead(i).nonEmpty) mergefpWbBusy & (~vfWbBusyTableMask(i)) 431 else mergefpWbBusy 432 } 433 val mergeV0WbBusy = { 434 if (v0WbBusyTableRead(i).nonEmpty) mergeVfWbBusy & (~v0WbBusyTableMask(i)) 435 else mergeVfWbBusy 436 } 437 val mergeVlWbBusy = { 438 if (vlWbBusyTableRead(i).nonEmpty) mergeV0WbBusy & (~vlWbBusyTableMask(i)) 439 else mergeV0WbBusy 440 } 441 merge := mergeVlWbBusy 442 } 443 444 deqCanIssue.zipWithIndex.foreach { case (req, i) => 445 req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt 446 } 447 dontTouch(fuTypeVec) 448 dontTouch(canIssueMergeAllBusy) 449 dontTouch(deqCanIssue) 450 451 if (params.numDeq == 2) { 452 require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different") 453 } 454 455 if (params.numDeq == 2 && params.deqFuSame) { 456 val subDeqPolicy = Module(new DeqPolicy()) 457 458 enqEntryOldestSel := DontCare 459 460 if (params.isAllComp || params.isAllSimp) { 461 othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq, 462 enq = othersEntryEnqSelVec.get, 463 canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq) 464 ) 465 othersEntryOldestSel(1) := DontCare 466 467 subDeqPolicy.io.request := subDeqRequest.get 468 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 469 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits) 470 } 471 else { 472 simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq) 473 simpAgeDetectRequest.get(1) := DontCare 474 simpAgeDetectRequest.get(params.numDeq) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt 475 if (params.numEnq == 2) { 476 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 477 } 478 479 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 480 enq = simpEntryEnqSelVec.get, 481 canIssue = simpAgeDetectRequest.get 482 ) 483 484 compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp, 485 enq = compEntryEnqSelVec.get, 486 canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp) 487 ) 488 compEntryOldestSel.get(1) := DontCare 489 490 othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid 491 othersEntryOldestSel(0).bits := Cat( 492 compEntryOldestSel.get(0).bits, 493 Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits, 494 ) 495 othersEntryOldestSel(1) := DontCare 496 497 subDeqPolicy.io.request := Reverse(subDeqRequest.get) 498 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 499 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits)) 500 } 501 502 subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)) 503 504 deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1) 505 deqSelValidVec(1) := subDeqSelValidVec.get(0) 506 deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid, 507 Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)), 508 subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0) 509 deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1) 510 511 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 512 selValid := deqValid && deqOH.orR 513 selOH := deqOH 514 } 515 } 516 else { 517 enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq, 518 enq = VecInit(s0_doEnqSelValidVec), 519 canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0))) 520 ) 521 522 if (params.isAllComp || params.isAllSimp) { 523 othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq, 524 enq = othersEntryEnqSelVec.get, 525 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq))) 526 ) 527 528 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 529 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 530 selValid := false.B 531 selOH := 0.U.asTypeOf(selOH) 532 } else { 533 selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid 534 selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits) 535 } 536 } 537 } 538 else { 539 othersEntryOldestSel := DontCare 540 541 deqCanIssue.zipWithIndex.foreach { case (req, i) => 542 simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq) 543 } 544 simpAgeDetectRequest.get(params.numDeq) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt 545 if (params.numEnq == 2) { 546 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 547 } 548 549 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 550 enq = simpEntryEnqSelVec.get, 551 canIssue = simpAgeDetectRequest.get 552 ) 553 554 compEntryOldestSel.get := AgeDetector(numEntries = params.numComp, 555 enq = compEntryEnqSelVec.get, 556 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp))) 557 ) 558 559 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 560 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 561 selValid := false.B 562 selOH := 0.U.asTypeOf(selOH) 563 } else { 564 selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid 565 selOH := Cat( 566 compEntryOldestSel.get(i).bits, 567 Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits, 568 Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits 569 ) 570 } 571 } 572 } 573 574 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 575 selValid := deqValid 576 selOH := deqOH 577 } 578 } 579 580 val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle))) 581 582 toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) => 583 deqResp.valid := deqBeforeDly(i).valid 584 deqResp.bits.resp := RespType.success 585 deqResp.bits.robIdx := DontCare 586 deqResp.bits.sqIdx.foreach(_ := DontCare) 587 deqResp.bits.lqIdx.foreach(_ := DontCare) 588 deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType 589 deqResp.bits.uopIdx.foreach(_ := DontCare) 590 } 591 592 //fuBusyTable 593 fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) => 594 if(busyTableWrite.nonEmpty) { 595 val btwr = busyTableWrite.get 596 val btrd = busyTableRead.get 597 btwr.io.in.deqResp := toBusyTableDeqResp(i) 598 btwr.io.in.og0Resp := io.og0Resp(i) 599 btwr.io.in.og1Resp := io.og1Resp(i) 600 btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable 601 btrd.io.in.fuTypeRegVec := fuTypeVec 602 fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask 603 } 604 else { 605 fuBusyTableMask(i) := 0.U(params.numEntries.W) 606 } 607 } 608 609 //wbfuBusyTable write 610 intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 611 if(busyTableWrite.nonEmpty) { 612 val btwr = busyTableWrite.get 613 val bt = busyTable.get 614 val dq = deqResp.get 615 btwr.io.in.deqResp := toBusyTableDeqResp(i) 616 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.rfWen.getOrElse(false.B) 617 btwr.io.in.og0Resp := io.og0Resp(i) 618 btwr.io.in.og1Resp := io.og1Resp(i) 619 bt := btwr.io.out.fuBusyTable 620 dq := btwr.io.out.deqRespSet 621 } 622 } 623 624 fpWbBusyTableWrite.zip(fpWbBusyTableOut).zip(fpDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 625 if (busyTableWrite.nonEmpty) { 626 val btwr = busyTableWrite.get 627 val bt = busyTable.get 628 val dq = deqResp.get 629 btwr.io.in.deqResp := toBusyTableDeqResp(i) 630 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.fpWen.getOrElse(false.B) 631 btwr.io.in.og0Resp := io.og0Resp(i) 632 btwr.io.in.og1Resp := io.og1Resp(i) 633 bt := btwr.io.out.fuBusyTable 634 dq := btwr.io.out.deqRespSet 635 } 636 } 637 638 vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 639 if (busyTableWrite.nonEmpty) { 640 val btwr = busyTableWrite.get 641 val bt = busyTable.get 642 val dq = deqResp.get 643 btwr.io.in.deqResp := toBusyTableDeqResp(i) 644 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.vecWen.getOrElse(false.B) 645 btwr.io.in.og0Resp := io.og0Resp(i) 646 btwr.io.in.og1Resp := io.og1Resp(i) 647 bt := btwr.io.out.fuBusyTable 648 dq := btwr.io.out.deqRespSet 649 } 650 } 651 652 v0WbBusyTableWrite.zip(v0WbBusyTableOut).zip(v0DeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 653 if (busyTableWrite.nonEmpty) { 654 val btwr = busyTableWrite.get 655 val bt = busyTable.get 656 val dq = deqResp.get 657 btwr.io.in.deqResp := toBusyTableDeqResp(i) 658 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.v0Wen.getOrElse(false.B) 659 btwr.io.in.og0Resp := io.og0Resp(i) 660 btwr.io.in.og1Resp := io.og1Resp(i) 661 bt := btwr.io.out.fuBusyTable 662 dq := btwr.io.out.deqRespSet 663 } 664 } 665 666 vlWbBusyTableWrite.zip(vlWbBusyTableOut).zip(vlDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 667 if (busyTableWrite.nonEmpty) { 668 val btwr = busyTableWrite.get 669 val bt = busyTable.get 670 val dq = deqResp.get 671 btwr.io.in.deqResp := toBusyTableDeqResp(i) 672 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.vlWen.getOrElse(false.B) 673 btwr.io.in.og0Resp := io.og0Resp(i) 674 btwr.io.in.og1Resp := io.og1Resp(i) 675 bt := btwr.io.out.fuBusyTable 676 dq := btwr.io.out.deqRespSet 677 } 678 } 679 680 //wbfuBusyTable read 681 intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 682 if(busyTableRead.nonEmpty) { 683 val btrd = busyTableRead.get 684 val bt = busyTable.get 685 btrd.io.in.fuBusyTable := bt 686 btrd.io.in.fuTypeRegVec := fuTypeVec 687 intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 688 } 689 else { 690 intWbBusyTableMask(i) := 0.U(params.numEntries.W) 691 } 692 } 693 fpWbBusyTableRead.zip(fpWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 694 if (busyTableRead.nonEmpty) { 695 val btrd = busyTableRead.get 696 val bt = busyTable.get 697 btrd.io.in.fuBusyTable := bt 698 btrd.io.in.fuTypeRegVec := fuTypeVec 699 fpWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 700 } 701 else { 702 fpWbBusyTableMask(i) := 0.U(params.numEntries.W) 703 } 704 } 705 vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 706 if (busyTableRead.nonEmpty) { 707 val btrd = busyTableRead.get 708 val bt = busyTable.get 709 btrd.io.in.fuBusyTable := bt 710 btrd.io.in.fuTypeRegVec := fuTypeVec 711 vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 712 } 713 else { 714 vfWbBusyTableMask(i) := 0.U(params.numEntries.W) 715 } 716 } 717 v0WbBusyTableRead.zip(v0WbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 718 if (busyTableRead.nonEmpty) { 719 val btrd = busyTableRead.get 720 val bt = busyTable.get 721 btrd.io.in.fuBusyTable := bt 722 btrd.io.in.fuTypeRegVec := fuTypeVec 723 v0WbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 724 } 725 else { 726 v0WbBusyTableMask(i) := 0.U(params.numEntries.W) 727 } 728 } 729 vlWbBusyTableRead.zip(vlWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 730 if (busyTableRead.nonEmpty) { 731 val btrd = busyTableRead.get 732 val bt = busyTable.get 733 btrd.io.in.fuBusyTable := bt 734 btrd.io.in.fuTypeRegVec := fuTypeVec 735 vlWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 736 } 737 else { 738 vlWbBusyTableMask(i) := 0.U(params.numEntries.W) 739 } 740 } 741 742 wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) => 743 wakeUpQueueOption.foreach { 744 wakeUpQueue => 745 val flush = Wire(new WakeupQueueFlush) 746 flush.redirect := io.flush 747 flush.ldCancel := io.ldCancel 748 flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp) 749 flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp) 750 wakeUpQueue.io.flush := flush 751 wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid 752 wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common 753 wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U) 754 wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType) 755 } 756 } 757 758 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 759 deq.valid := finalDeqSelValidVec(i) && !cancelDeqVec(i) 760 deq.bits.addrOH := finalDeqSelOHVec(i) 761 deq.bits.common.isFirstIssue := deqFirstIssueVec(i) 762 deq.bits.common.iqIdx := OHToUInt(finalDeqSelOHVec(i)) 763 deq.bits.common.fuType := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 764 deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType 765 deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen) 766 deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen) 767 deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen) 768 deq.bits.common.v0Wen.foreach(_ := deqEntryVec(i).bits.payload.v0Wen) 769 deq.bits.common.vlWen.foreach(_ := deqEntryVec(i).bits.payload.vlWen) 770 deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe) 771 deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest 772 deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx 773 774 require(deq.bits.common.dataSources.size <= finalDataSources(i).size) 775 deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source} 776 deq.bits.common.exuSources.foreach(_.zip(finalExuSources.get(i)).foreach { case (sink, source) => sink := source}) 777 deq.bits.common.srcTimer.foreach(_ := DontCare) 778 deq.bits.common.loadDependency.foreach(_.zip(finalLoadDependency(i)).foreach { case (sink, source) => sink := source}) 779 deq.bits.common.src := DontCare 780 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 781 782 deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) => 783 // psrc in status array can be pregIdx of IntRegFile or VfRegFile 784 rf.foreach(_.addr := psrc) 785 rf.foreach(_.srcType := srcType) 786 } 787 deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) => 788 sink := source 789 } 790 deq.bits.immType := deqEntryVec(i).bits.payload.selImm 791 deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U) 792 deq.bits.common.nextPcOffset.foreach(_ := 0.U) 793 deq.bits.rcIdx.foreach(_ := deqEntryVec(i).bits.status.srcStatus.map(_.regCacheIdx.get)) 794 795 deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo 796 deq.bits.common.perfDebugInfo.selectTime := GTimer() 797 deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U 798 } 799 800 val deqDelay = Reg(params.genIssueValidBundle) 801 deqDelay.zip(deqBeforeDly).foreach { case (deqDly, deq) => 802 deqDly.valid := deq.valid 803 when(validVec.asUInt.orR) { 804 deqDly.bits := deq.bits 805 } 806 // deqBeforeDly.ready is always true 807 deq.ready := true.B 808 } 809 io.deqDelay.zip(deqDelay).foreach { case (sink, source) => 810 sink.valid := source.valid 811 sink.bits := source.bits 812 } 813 if(backendParams.debugEn) { 814 dontTouch(deqDelay) 815 dontTouch(io.deqDelay) 816 dontTouch(deqBeforeDly) 817 } 818 io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) => 819 if (wakeUpQueues(i).nonEmpty) { 820 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 821 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits) 822 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 823 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 824 wakeup.bits.rcDest.foreach(_ := io.replaceRCIdx.get(i)) 825 } else { 826 wakeup.valid := false.B 827 wakeup.bits := 0.U.asTypeOf(wakeup.bits) 828 } 829 if (wakeUpQueues(i).nonEmpty) { 830 wakeup.bits.rfWen := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B) 831 wakeup.bits.fpWen := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B) 832 wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B) 833 wakeup.bits.v0Wen := (if (wakeUpQueues(i).get.io.deq.bits.v0Wen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.v0Wen.get else false.B) 834 wakeup.bits.vlWen := (if (wakeUpQueues(i).get.io.deq.bits.vlWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vlWen.get else false.B) 835 } 836 837 if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){ 838 wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get 839 } 840 if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) { 841 wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get 842 } 843 if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) { 844 wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get 845 } 846 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) { 847 wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get 848 } 849 if (wakeUpQueues(i).nonEmpty && wakeup.bits.v0WenCopy.nonEmpty) { 850 wakeup.bits.v0WenCopy.get := wakeUpQueues(i).get.io.deq.bits.v0WenCopy.get 851 } 852 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vlWenCopy.nonEmpty) { 853 wakeup.bits.vlWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vlWenCopy.get 854 } 855 if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) { 856 wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get 857 } 858 } 859 860 // Todo: better counter implementation 861 private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _) 862 private val enqHasIssued = validVec.zip(issuedVec).take(params.numEnq).map(x => x._1 & x._2).reduce(_ | _) 863 private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq)) 864 private val othersValidCnt = PopCount(validVec.drop(params.numEnq)) 865 private val enqEntryValidCntDeq0 = PopCount( 866 validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b } 867 ) 868 private val othersValidCntDeq0 = PopCount( 869 validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b } 870 ) 871 private val enqEntryValidCntDeq1 = PopCount( 872 validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b } 873 ) 874 private val othersValidCntDeq1 = PopCount( 875 validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b } 876 ) 877 protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 878 io.enq.map(_.bits.fuType).map(fuType => 879 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 880 } 881 protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b }) 882 protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b }) 883 io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0) 884 io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1) 885 io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _) 886 for (i <- 0 until params.numEnq) { 887 io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U 888 } 889 private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W))) 890 othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 891 leftone := ~(1.U((params.numEntries - params.numEnq).W) << i) 892 } 893 private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _) 894 private val othersCanotIn = Wire(Bool()) 895 othersCanotIn := othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _) 896 // if has simp Entry, othersCanotIn will be simpCanotIn 897 if (params.numSimp > 0) { 898 val simpLeftOneCaseVec = Wire(Vec(params.numSimp, UInt((params.numSimp).W))) 899 simpLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 900 leftone := ~(1.U((params.numSimp).W) << i) 901 } 902 val simpLeftOne = simpLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt).reduce(_ | _) 903 val simpCanotIn = simpLeftOne || validVec.drop(params.numEnq).take(params.numSimp).reduce(_ & _) 904 othersCanotIn := simpCanotIn 905 } 906 io.enq.foreach(_.ready := (!othersCanotIn || !enqHasValid) && !enqHasIssued) 907 io.status.empty := !Cat(validVec).orR 908 io.status.full := othersCanotIn 909 io.status.validCnt := PopCount(validVec) 910 911 protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = { 912 Mux1H(wakeupFuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) }) 913 } 914 915 // issue perf counter 916 // enq count 917 XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire))) 918 XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire))) 919 XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) })) 920 XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) })) 921 XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire)) 922 XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire)) 923 // valid count 924 XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1) 925 XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1) 926 XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1) 927 // only split when more than 1 func type 928 if (params.getFuCfgs.size > 0) { 929 for (t <- FuType.functionNameMap.keys) { 930 val fuName = FuType.functionNameMap(t) 931 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 932 XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1) 933 } 934 } 935 } 936 // ready instr count 937 private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2)) 938 XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1) 939 // only split when more than 1 func type 940 if (params.getFuCfgs.size > 0) { 941 for (t <- FuType.functionNameMap.keys) { 942 val fuName = FuType.functionNameMap(t) 943 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 944 XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1) 945 } 946 } 947 } 948 949 // deq instr count 950 XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid))) 951 XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 952 XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid))) 953 XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 954 955 // deq instr data source count 956 XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq => 957 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 958 }.reduce(_ +& _)) 959 XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq => 960 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 961 }.reduce(_ +& _)) 962 XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq => 963 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 964 }.reduce(_ +& _)) 965 XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq => 966 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 967 }.reduce(_ +& _)) 968 969 XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq => 970 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 971 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 972 XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq => 973 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 974 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 975 XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq => 976 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 977 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 978 XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq => 979 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 980 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 981 982 // deq instr data source count for each futype 983 for (t <- FuType.functionNameMap.keys) { 984 val fuName = FuType.functionNameMap(t) 985 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 986 XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq => 987 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 988 }.reduce(_ +& _)) 989 XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq => 990 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 991 }.reduce(_ +& _)) 992 XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq => 993 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 994 }.reduce(_ +& _)) 995 XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq => 996 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 997 }.reduce(_ +& _)) 998 999 XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 1000 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 1001 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 1002 XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq => 1003 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 1004 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 1005 XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq => 1006 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 1007 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 1008 XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 1009 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 1010 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 1011 } 1012 } 1013} 1014 1015class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle { 1016 val fastMatch = UInt(backendParams.LduCnt.W) 1017 val fastImm = UInt(12.W) 1018} 1019 1020class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO 1021 1022class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 1023 extends IssueQueueImp(wrapper) 1024{ 1025 io.suggestName("none") 1026 override lazy val io = IO(new IssueQueueIntIO).suggestName("io") 1027 1028 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 1029 deq.bits.common.pc.foreach(_ := DontCare) 1030 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 1031 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 1032 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 1033 deq.bits.common.predictInfo.foreach(x => { 1034 x.target := DontCare 1035 x.taken := deqEntryVec(i).bits.payload.pred_taken 1036 }) 1037 // for std 1038 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 1039 // for i2f 1040 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1041 }} 1042} 1043 1044class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 1045 extends IssueQueueImp(wrapper) 1046{ 1047 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 1048 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1049 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1050 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1051 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1052 }} 1053} 1054 1055class IssueQueueFpImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 1056 extends IssueQueueImp(wrapper) 1057{ 1058 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 1059 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1060 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1061 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1062 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1063 }} 1064} 1065 1066class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 1067 val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO(params.isVecMemIQ))) 1068 1069 // TODO: is still needed? 1070 val checkWait = new Bundle { 1071 val stIssuePtr = Input(new SqPtr) 1072 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 1073 } 1074 val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle)) 1075 1076 // load wakeup 1077 val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst()))) 1078 1079 // vector 1080 val sqDeqPtr = Option.when(params.isVecMemIQ)(Input(new SqPtr)) 1081 val lqDeqPtr = Option.when(params.isVecMemIQ)(Input(new LqPtr)) 1082} 1083 1084class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO { 1085 val memIO = Some(new IssueQueueMemBundle) 1086} 1087 1088class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 1089 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 1090 1091 require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " + 1092 s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 1093 println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 1094 1095 io.suggestName("none") 1096 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 1097 private val memIO = io.memIO.get 1098 1099 memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed? 1100 1101 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1102 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1103 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1104 slowResp.bits.sqIdx.foreach( _ := memIO.feedbackIO(i).feedbackSlow.bits.sqIdx) 1105 slowResp.bits.lqIdx.foreach( _ := memIO.feedbackIO(i).feedbackSlow.bits.lqIdx) 1106 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1107 slowResp.bits.fuType := DontCare 1108 } 1109 1110 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1111 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1112 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1113 fastResp.bits.sqIdx.foreach( _ := memIO.feedbackIO(i).feedbackFast.bits.sqIdx) 1114 fastResp.bits.lqIdx.foreach( _ := memIO.feedbackIO(i).feedbackFast.bits.lqIdx) 1115 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1116 fastResp.bits.fuType := DontCare 1117 } 1118 1119 // load wakeup 1120 val loadWakeUpIter = memIO.loadWakeUp.iterator 1121 io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) => 1122 if (param.hasLoadExu) { 1123 require(wakeUpQueues(i).isEmpty) 1124 val uop = loadWakeUpIter.next() 1125 1126 wakeup.valid := GatedValidRegNext(uop.fire) 1127 wakeup.bits.rfWen := (if (params.writeIntRf) GatedValidRegNext(uop.bits.rfWen && uop.fire) else false.B) 1128 wakeup.bits.fpWen := (if (params.writeFpRf) GatedValidRegNext(uop.bits.fpWen && uop.fire) else false.B) 1129 wakeup.bits.vecWen := (if (params.writeVecRf) GatedValidRegNext(uop.bits.vecWen && uop.fire) else false.B) 1130 wakeup.bits.v0Wen := (if (params.writeV0Rf) GatedValidRegNext(uop.bits.v0Wen && uop.fire) else false.B) 1131 wakeup.bits.vlWen := (if (params.writeVlRf) GatedValidRegNext(uop.bits.vlWen && uop.fire) else false.B) 1132 wakeup.bits.pdest := RegEnable(uop.bits.pdest, uop.fire) 1133 wakeup.bits.rcDest.foreach(_ := io.replaceRCIdx.get(i)) 1134 wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only 1135 1136 wakeup.bits.rfWenCopy .foreach(_.foreach(_ := (if (params.writeIntRf) GatedValidRegNext(uop.bits.rfWen && uop.fire) else false.B))) 1137 wakeup.bits.fpWenCopy .foreach(_.foreach(_ := (if (params.writeFpRf) GatedValidRegNext(uop.bits.fpWen && uop.fire) else false.B))) 1138 wakeup.bits.vecWenCopy.foreach(_.foreach(_ := (if (params.writeVecRf) GatedValidRegNext(uop.bits.vecWen && uop.fire) else false.B))) 1139 wakeup.bits.v0WenCopy .foreach(_.foreach(_ := (if (params.writeV0Rf) GatedValidRegNext(uop.bits.v0Wen && uop.fire) else false.B))) 1140 wakeup.bits.vlWenCopy .foreach(_.foreach(_ := (if (params.writeVlRf) GatedValidRegNext(uop.bits.vlWen && uop.fire) else false.B))) 1141 wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegEnable(uop.bits.pdest, uop.fire))) 1142 wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only 1143 1144 wakeup.bits.is0Lat := 0.U 1145 } 1146 } 1147 require(!loadWakeUpIter.hasNext) 1148 1149 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1150 deq.bits.common.pc.foreach(_ := 0.U) 1151 deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit) 1152 deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx) 1153 deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit) 1154 deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict) 1155 deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid) 1156 deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx 1157 deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx 1158 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 1159 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 1160 } 1161} 1162 1163class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 1164 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 1165 1166 require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ") 1167 println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}") 1168 1169 io.suggestName("none") 1170 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 1171 private val memIO = io.memIO.get 1172 1173 require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports") 1174 1175 for (i <- entries.io.enq.indices) { 1176 entries.io.enq(i).bits.status match { case enqData => 1177 enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx 1178 enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx 1179 // MemAddrIQ also handle vector insts 1180 enqData.vecMem.get.numLsElem := s0_enqBits(i).numLsElem 1181 1182 val isFirstLoad = s0_enqBits(i).lqIdx <= memIO.lqDeqPtr.get 1183 val isVleff = s0_enqBits(i).vpu.isVleff 1184 enqData.blocked := !isFirstLoad && isVleff 1185 } 1186 } 1187 1188 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1189 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1190 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1191 slowResp.bits.sqIdx.get := memIO.feedbackIO(i).feedbackSlow.bits.sqIdx 1192 slowResp.bits.lqIdx.get := memIO.feedbackIO(i).feedbackSlow.bits.lqIdx 1193 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1194 slowResp.bits.fuType := DontCare 1195 slowResp.bits.uopIdx.get := DontCare 1196 } 1197 1198 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1199 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1200 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1201 fastResp.bits.sqIdx.get := memIO.feedbackIO(i).feedbackFast.bits.sqIdx 1202 fastResp.bits.lqIdx.get := memIO.feedbackIO(i).feedbackFast.bits.lqIdx 1203 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1204 fastResp.bits.fuType := DontCare 1205 fastResp.bits.uopIdx.get := DontCare 1206 } 1207 1208 entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get 1209 entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get 1210 1211 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1212 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx) 1213 deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx) 1214 deq.bits.common.numLsElem.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.numLsElem) 1215 if (params.isVecLduIQ) { 1216 deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr 1217 deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset 1218 } 1219 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1220 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1221 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1222 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1223 } 1224 1225 io.vecLoadIssueResp.foreach(dontTouch(_)) 1226} 1227