1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package system 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import device.{DebugModule, TLPMA, TLPMAIO, AXI4MemEncrypt} 23import freechips.rocketchip.amba.axi4._ 24import freechips.rocketchip.devices.debug.DebugModuleKey 25import freechips.rocketchip.devices.tilelink._ 26import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes} 27import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple} 28import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup} 29import freechips.rocketchip.tilelink._ 30import freechips.rocketchip.util.AsyncQueueParams 31import huancun._ 32import top.BusPerfMonitor 33import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger} 34import xiangshan.backend.fu.{MemoryRange, PMAConfigEntry, PMAConst} 35import xiangshan.{DebugOptionsKey, PMParameKey, XSTileKey} 36import coupledL2.{EnableCHI, L2Param} 37import coupledL2.tl2chi.CHIIssue 38import openLLC.OpenLLCParam 39 40case object SoCParamsKey extends Field[SoCParameters] 41case object CVMParamskey extends Field[CVMParameters] 42 43case class CVMParameters 44( 45 MEMENCRange: AddressSet = AddressSet(0x38030000L, 0xfff), 46 KeyIDBits: Int = 0, 47 MemencPipes: Int = 4, 48 HasMEMencryption: Boolean = false, 49 HasDelayNoencryption: Boolean = false, // Test specific 50) 51 52case class SoCParameters 53( 54 EnableILA: Boolean = false, 55 PAddrBits: Int = 48, 56 PmemRanges: Seq[MemoryRange] = Seq(MemoryRange(0x80000000L, 0x80000000000L)), 57 PMAConfigs: Seq[PMAConfigEntry] = Seq( 58 PMAConfigEntry(0x0L, range = 0x1000000000000L, a = 3), 59 PMAConfigEntry(0x80000000000L, c = true, atomic = true, a = 1, x = true, w = true, r = true), 60 PMAConfigEntry(0x80000000L, a = 1, w = true, r = true), 61 PMAConfigEntry(0x3A000000L, a = 1), 62 PMAConfigEntry(0x39002000L, a = 1, w = true, r = true), 63 PMAConfigEntry(0x39000000L, a = 1, w = true, r = true), 64 PMAConfigEntry(0x38022000L, a = 1, w = true, r = true), 65 PMAConfigEntry(0x38021000L, a = 1, x = true, w = true, r = true), 66 PMAConfigEntry(0x38020000L, a = 1, w = true, r = true), 67 PMAConfigEntry(0x30050000L, a = 1, w = true, r = true), // FIXME: GPU space is cacheable? 68 PMAConfigEntry(0x30010000L, a = 1, w = true, r = true), 69 PMAConfigEntry(0x20000000L, a = 1, x = true, w = true, r = true), 70 PMAConfigEntry(0x10000000L, a = 1, w = true, r = true), 71 PMAConfigEntry(0) 72 ), 73 CLINTRange: AddressSet = AddressSet(0x38000000L, CLINTConsts.size - 1), 74 BEURange: AddressSet = AddressSet(0x38010000L, 0xfff), 75 PLICRange: AddressSet = AddressSet(0x3c000000L, PLICConsts.size(PLICConsts.maxMaxHarts) - 1), 76 PLLRange: AddressSet = AddressSet(0x3a000000L, 0xfff), 77 UARTLiteForDTS: Boolean = true, // should be false in SimMMIO 78 extIntrs: Int = 64, 79 L3NBanks: Int = 4, 80 L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 81 name = "L3", 82 level = 3, 83 ways = 8, 84 sets = 2048 // 1MB per bank 85 )), 86 OpenLLCParamsOpt: Option[OpenLLCParam] = None, 87 XSTopPrefix: Option[String] = None, 88 NodeIDWidthList: Map[String, Int] = Map( 89 "B" -> 7, 90 "C" -> 9, 91 "E.b" -> 11 92 ), 93 NumHart: Int = 64, 94 NumIRFiles: Int = 7, 95 NumIRSrc: Int = 256, 96 UseXSNoCTop: Boolean = false, 97 UseXSNoCDiffTop: Boolean = false, 98 UseXSTileDiffTop: Boolean = false, 99 IMSICBusType: device.IMSICBusType.Value = device.IMSICBusType.AXI, 100 IMSICParams: aia.IMSICParams = aia.IMSICParams( 101 imsicIntSrcWidth = 8, 102 mAddr = 0x3A800000, 103 sgAddr = 0x3B000000, 104 geilen = 5, 105 vgeinWidth = 6, 106 iselectWidth = 12, 107 EnableImsicAsyncBridge = true, 108 HasTEEIMSIC = false 109 ), 110 SeperateDMBus: Boolean = false, 111 EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 16, sync = 3, safe = false)), 112 EnableClintAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false)), 113 EnableDMAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false)) 114){ 115 require( 116 L3CacheParamsOpt.isDefined ^ OpenLLCParamsOpt.isDefined || L3CacheParamsOpt.isEmpty && OpenLLCParamsOpt.isEmpty, 117 "Atmost one of L3CacheParamsOpt and OpenLLCParamsOpt should be defined" 118 ) 119 // L3 configurations 120 val L3InnerBusWidth = 256 121 val L3BlockSize = 64 122 // on chip network configurations 123 val L3OuterBusWidth = 256 124 val UARTLiteRange = AddressSet(0x40600000, if (UARTLiteForDTS) 0x3f else 0xf) 125} 126 127trait HasSoCParameter { 128 implicit val p: Parameters 129 130 val soc = p(SoCParamsKey) 131 val cvm = p(CVMParamskey) 132 val debugOpts = p(DebugOptionsKey) 133 val tiles = p(XSTileKey) 134 val enableCHI = p(EnableCHI) 135 val issue = p(CHIIssue) 136 137 val NumCores = tiles.size 138 val EnableILA = soc.EnableILA 139 140 // Parameters for trace extension 141 val TraceTraceGroupNum = tiles.head.traceParams.TraceGroupNum 142 val TraceCauseWidth = tiles.head.XLEN 143 val TraceTvalWidth = tiles.head.traceParams.IaddrWidth 144 val TracePrivWidth = tiles.head.traceParams.PrivWidth 145 val TraceIaddrWidth = tiles.head.traceParams.IaddrWidth 146 val TraceItypeWidth = tiles.head.traceParams.ItypeWidth 147 val TraceIretireWidthCompressed = log2Up(tiles.head.RenameWidth * tiles.head.CommitWidth * 2) 148 val TraceIlastsizeWidth = tiles.head.traceParams.IlastsizeWidth 149 150 // L3 configurations 151 val L3InnerBusWidth = soc.L3InnerBusWidth 152 val L3BlockSize = soc.L3BlockSize 153 val L3NBanks = soc.L3NBanks 154 155 // on chip network configurations 156 val L3OuterBusWidth = soc.L3OuterBusWidth 157 158 val NrExtIntr = soc.extIntrs 159 160 val SetIpNumValidSize = soc.NumHart * soc.NumIRFiles 161 162 val NumIRSrc = soc.NumIRSrc 163 164 val SeperateDMBus = soc.SeperateDMBus 165 166 val EnableCHIAsyncBridge = if (enableCHI && soc.EnableCHIAsyncBridge.isDefined) 167 soc.EnableCHIAsyncBridge else None 168 val EnableClintAsyncBridge = soc.EnableClintAsyncBridge 169 val EnableDMAsyncBridge = if (SeperateDMBus && soc.EnableDMAsyncBridge.isDefined) 170 soc.EnableDMAsyncBridge else None 171 172 def HasMEMencryption = cvm.HasMEMencryption 173 require((cvm.HasMEMencryption && (cvm.KeyIDBits > 0)) || (!cvm.HasMEMencryption && (cvm.KeyIDBits == 0)), 174 "HasMEMencryption most set with KeyIDBits > 0") 175} 176 177trait HasPeripheralRanges { 178 implicit val p: Parameters 179 180 private def cvm = p(CVMParamskey) 181 private def soc = p(SoCParamsKey) 182 private def dm = p(DebugModuleKey) 183 private def pmParams = p(PMParameKey) 184 185 private def mmpma = pmParams.mmpma 186 187 def onChipPeripheralRanges: Map[String, AddressSet] = Map( 188 "CLINT" -> soc.CLINTRange, 189 "BEU" -> soc.BEURange, 190 "PLIC" -> soc.PLICRange, 191 "PLL" -> soc.PLLRange, 192 "UART" -> soc.UARTLiteRange, 193 "DEBUG" -> dm.get.address, 194 "MMPMA" -> AddressSet(mmpma.address, mmpma.mask) 195 ) ++ ( 196 if (soc.L3CacheParamsOpt.map(_.ctrl.isDefined).getOrElse(false)) 197 Map("L3CTL" -> AddressSet(soc.L3CacheParamsOpt.get.ctrl.get.address, 0xffff)) 198 else 199 Map() 200 ) ++ ( 201 if (cvm.HasMEMencryption) 202 Map("MEMENC" -> cvm.MEMENCRange) 203 else 204 Map() 205 ) 206 207 def peripheralRange = onChipPeripheralRanges.values.foldLeft(Seq(AddressSet(0x0, 0x7fffffffL))) { (acc, x) => 208 acc.flatMap(_.subtract(x)) 209 } 210} 211 212class ILABundle extends Bundle {} 213 214 215abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter with HasPeripheralRanges { 216 val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize)) 217 val peripheralXbar = Option.when(!enableCHI)(TLXbar()) 218 val l3_xbar = Option.when(!enableCHI)(TLXbar()) 219 val l3_banked_xbar = Option.when(!enableCHI)(TLXbar()) 220 221 val soc_xbar = Option.when(enableCHI)(AXI4Xbar()) 222} 223 224// We adapt the following three traits from rocket-chip. 225// Source: rocket-chip/src/main/scala/subsystem/Ports.scala 226trait HaveSlaveAXI4Port { 227 this: BaseSoC => 228 229 val idBits = 14 230 231 val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters( 232 Seq(AXI4MasterParameters( 233 name = "dma", 234 id = IdRange(0, 1 << idBits) 235 )) 236 ))) 237 238 if (l3_xbar.isDefined) { 239 val errorDevice = LazyModule(new TLError( 240 params = DevNullParams( 241 address = Seq(AddressSet(0x0, 0x7fffffffL)), 242 maxAtomic = 8, 243 maxTransfer = 64), 244 beatBytes = L3InnerBusWidth / 8 245 )) 246 errorDevice.node := 247 l3_xbar.get := 248 TLFIFOFixer() := 249 TLWidthWidget(32) := 250 AXI4ToTL() := 251 AXI4UserYanker(Some(1)) := 252 AXI4Fragmenter() := 253 AXI4Buffer() := 254 AXI4Buffer() := 255 AXI4IdIndexer(1) := 256 l3FrontendAXI4Node 257 } 258 259 val dma = InModuleBody { 260 l3FrontendAXI4Node.makeIOs() 261 } 262} 263 264trait HaveAXI4MemPort { 265 this: BaseSoC => 266 val device = new MemoryDevice 267 // 48-bit physical address 268 val memRange = AddressSet(0x00000000L, 0xffffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL)) 269 val memAXI4SlaveNode = AXI4SlaveNode(Seq( 270 AXI4SlavePortParameters( 271 slaves = Seq( 272 AXI4SlaveParameters( 273 address = memRange, 274 regionType = RegionType.UNCACHED, 275 executable = true, 276 supportsRead = TransferSizes(1, L3BlockSize), 277 supportsWrite = TransferSizes(1, L3BlockSize), 278 interleavedId = Some(0), 279 resources = device.reg("mem") 280 ) 281 ), 282 beatBytes = L3OuterBusWidth / 8, 283 requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey), 284 ) 285 )) 286 287 val mem_xbar = TLXbar() 288 val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true) 289 val axi4mem_node = AXI4IdentityNode() 290 291 if (enableCHI) { 292 axi4mem_node := 293 soc_xbar.get 294 } else { 295 mem_xbar :=* 296 TLBuffer.chainNode(2) := 297 TLCacheCork() := 298 l3_mem_pmu := 299 TLClientsMerger() := 300 TLXbar() :=* 301 bankedNode.get 302 303 mem_xbar := 304 TLWidthWidget(8) := 305 TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) := 306 peripheralXbar.get 307 308 axi4mem_node := 309 TLToAXI4() := 310 TLSourceShrinker(64) := 311 TLWidthWidget(L3OuterBusWidth / 8) := 312 TLBuffer.chainNode(2) := 313 mem_xbar 314 } 315 val axi4memencrpty = Option.when(HasMEMencryption)(LazyModule(new AXI4MemEncrypt(cvm.MEMENCRange))) 316 if (HasMEMencryption) { 317 memAXI4SlaveNode := 318 AXI4Buffer() := 319 AXI4Buffer() := 320 AXI4Buffer() := 321 AXI4IdIndexer(idBits = 14) := 322 AXI4UserYanker() := 323 axi4memencrpty.get.node 324 325 axi4memencrpty.get.node := 326 AXI4Deinterleaver(L3BlockSize) := 327 axi4mem_node 328 } else { 329 memAXI4SlaveNode := 330 AXI4Buffer() := 331 AXI4Buffer() := 332 AXI4Buffer() := 333 AXI4IdIndexer(idBits = 14) := 334 AXI4UserYanker() := 335 AXI4Deinterleaver(L3BlockSize) := 336 axi4mem_node 337 } 338 339 340 val memory = InModuleBody { 341 memAXI4SlaveNode.makeIOs() 342 } 343} 344 345trait HaveAXI4PeripheralPort { this: BaseSoC => 346 val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite")) 347 val uartParams = AXI4SlaveParameters( 348 address = Seq(soc.UARTLiteRange), 349 regionType = RegionType.UNCACHED, 350 supportsRead = TransferSizes(1, 32), 351 supportsWrite = TransferSizes(1, 32), 352 resources = uartDevice.reg 353 ) 354 val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters( 355 Seq(AXI4SlaveParameters( 356 address = peripheralRange, 357 regionType = RegionType.UNCACHED, 358 supportsRead = TransferSizes(1, 32), 359 supportsWrite = TransferSizes(1, 32), 360 interleavedId = Some(0) 361 ), uartParams), 362 beatBytes = 8 363 ))) 364 365 val axi4peripheral_node = AXI4IdentityNode() 366 val error_xbar = Option.when(enableCHI)(TLXbar()) 367 368 peripheralNode := 369 AXI4UserYanker() := 370 AXI4IdIndexer(idBits = 2) := 371 AXI4Buffer() := 372 AXI4Buffer() := 373 AXI4Buffer() := 374 AXI4Buffer() := 375 AXI4UserYanker() := 376 // AXI4Deinterleaver(8) := 377 axi4peripheral_node 378 379 if (enableCHI) { 380 val error = LazyModule(new TLError( 381 params = DevNullParams( 382 address = Seq(AddressSet(0x1000000000000L, 0xffffffffffffL)), 383 maxAtomic = 8, 384 maxTransfer = 64), 385 beatBytes = 8 386 )) 387 error.node := error_xbar.get 388 axi4peripheral_node := 389 AXI4Deinterleaver(8) := 390 TLToAXI4() := 391 error_xbar.get := 392 TLBuffer.chainNode(2, Some("llc_to_peripheral_buffer")) := 393 TLFIFOFixer() := 394 TLWidthWidget(L3OuterBusWidth / 8) := 395 AXI4ToTL() := 396 AXI4UserYanker() := 397 soc_xbar.get 398 } else { 399 axi4peripheral_node := 400 AXI4Deinterleaver(8) := 401 TLToAXI4() := 402 TLBuffer.chainNode(3) := 403 peripheralXbar.get 404 } 405 406 val peripheral = InModuleBody { 407 peripheralNode.makeIOs() 408 } 409 410} 411 412class MemMisc()(implicit p: Parameters) extends BaseSoC 413 with HaveAXI4MemPort 414 with PMAConst 415 with HaveAXI4PeripheralPort 416{ 417 418 val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() }) 419 val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() }) 420 421 val l3_in = TLTempNode() 422 val l3_out = TLTempNode() 423 424 val device_xbar = Option.when(enableCHI)(TLXbar()) 425 device_xbar.foreach(_ := error_xbar.get) 426 427 if (l3_banked_xbar.isDefined) { 428 l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar.get 429 l3_banked_xbar.get := TLBuffer.chainNode(2) := l3_xbar.get 430 } 431 bankedNode match { 432 case Some(bankBinder) => 433 bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out 434 case None => 435 } 436 437 if(soc.L3CacheParamsOpt.isEmpty){ 438 l3_out :*= l3_in 439 } 440 441 if (!enableCHI) { 442 for (port <- peripheral_ports.get) { 443 peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port 444 } 445 } 446 447 core_to_l3_ports.foreach { case _ => 448 for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){ 449 l3_banked_xbar.get :=* 450 TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=* 451 TLBuffer() := 452 core_out 453 } 454 } 455 456 val clint = LazyModule(new CLINT(CLINTParams(soc.CLINTRange.base), 8)) 457 if (enableCHI) { clint.node := device_xbar.get } 458 else { clint.node := peripheralXbar.get } 459 460 class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule { 461 val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1)) 462 class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 463 val in = IO(Input(Vec(num, Bool()))) 464 in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i } 465 } 466 lazy val module = new IntSourceNodeToModuleImp(this) 467 } 468 469 val plic = LazyModule(new TLPLIC(PLICParams(soc.PLICRange.base), 8)) 470 val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr)) 471 472 plic.intnode := plicSource.sourceNode 473 if (enableCHI) { plic.node := device_xbar.get } 474 else { plic.node := peripheralXbar.get } 475 476 val pll_node = TLRegisterNode( 477 address = Seq(soc.PLLRange), 478 device = new SimpleDevice("pll_ctrl", Seq()), 479 beatBytes = 8, 480 concurrency = 1 481 ) 482 if (enableCHI) { pll_node := device_xbar.get } 483 else { pll_node := peripheralXbar.get } 484 485 val debugModule = LazyModule(new DebugModule(NumCores)(p)) 486 val debugModuleXbarOpt = Option.when(SeperateDMBus)(TLXbar()) 487 if (enableCHI) { 488 if (SeperateDMBus) { 489 debugModule.debug.node := debugModuleXbarOpt.get 490 } else { 491 debugModule.debug.node := device_xbar.get 492 } 493 debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl => 494 error_xbar.get := sb2tl.node 495 } 496 } else { 497 if (SeperateDMBus) { 498 debugModule.debug.node := debugModuleXbarOpt.get 499 } else { 500 debugModule.debug.node := peripheralXbar.get 501 } 502 debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl => 503 l3_xbar.get := TLBuffer() := TLWidthWidget(1) := sb2tl.node 504 } 505 } 506 507 val pma = LazyModule(new TLPMA) 508 if (enableCHI) { 509 pma.node := TLBuffer.chainNode(4) := device_xbar.get 510 if (HasMEMencryption) { 511 axi4memencrpty.get.ctrl_node := TLToAPB() := device_xbar.get 512 } 513 } else { 514 pma.node := TLBuffer.chainNode(4) := peripheralXbar.get 515 if (HasMEMencryption) { 516 axi4memencrpty.get.ctrl_node := TLToAPB() := peripheralXbar.get 517 } 518 } 519 520 class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 521 522 val debug_module_io = IO(new debugModule.DebugModuleIO) 523 val ext_intrs = IO(Input(UInt(NrExtIntr.W))) 524 val rtc_clock = IO(Input(Bool())) 525 val pll0_lock = IO(Input(Bool())) 526 val pll0_ctrl = IO(Output(Vec(6, UInt(32.W)))) 527 val cacheable_check = IO(new TLPMAIO) 528 val clintTime = IO(Output(ValidIO(UInt(64.W)))) 529 530 debugModule.module.io <> debug_module_io 531 532 // sync external interrupts 533 require(plicSource.module.in.length == ext_intrs.getWidth) 534 for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) { 535 val ext_intr_sync = RegInit(0.U(3.W)) 536 ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt) 537 plic_in := ext_intr_sync(2) 538 } 539 540 pma.module.io <> cacheable_check 541 542 if (HasMEMencryption) { 543 val cnt = Counter(true.B, 8)._1 544 axi4memencrpty.get.module.io.random_val := axi4memencrpty.get.module.io.random_req && cnt(2).asBool 545 axi4memencrpty.get.module.io.random_data := cnt(0).asBool 546 } 547 // positive edge sampling of the lower-speed rtc_clock 548 val rtcTick = RegInit(0.U(3.W)) 549 rtcTick := Cat(rtcTick(1, 0), rtc_clock) 550 clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2) 551 552 val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) } 553 val pll_lock = RegNext(next = pll0_lock, init = false.B) 554 555 clintTime := clint.module.io.time 556 557 pll0_ctrl <> VecInit(pll_ctrl_regs) 558 559 pll_node.regmap( 560 0x000 -> RegFieldGroup( 561 "Pll", Some("PLL ctrl regs"), 562 pll_ctrl_regs.zipWithIndex.map{ 563 case (r, i) => RegField(32, r, RegFieldDesc( 564 s"PLL_ctrl_$i", 565 desc = s"PLL ctrl register #$i" 566 )) 567 } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc( 568 "PLL_lock", 569 "PLL lock register" 570 )) 571 ) 572 ) 573 } 574 575 lazy val module = new SoCMiscImp(this) 576} 577 578class SoCMisc()(implicit p: Parameters) extends MemMisc 579 with HaveSlaveAXI4Port 580 581