1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package system 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import device.{DebugModule, TLPMA, TLPMAIO, AXI4MemEncrypt} 23import freechips.rocketchip.amba.axi4._ 24import freechips.rocketchip.devices.debug.DebugModuleKey 25import freechips.rocketchip.devices.tilelink._ 26import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes} 27import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple} 28import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup} 29import freechips.rocketchip.tilelink._ 30import freechips.rocketchip.util.AsyncQueueParams 31import huancun._ 32import top.BusPerfMonitor 33import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger} 34import xiangshan.backend.fu.{MemoryRange, PMAConfigEntry, PMAConst} 35import xiangshan.{DebugOptionsKey, PMParameKey, XSTileKey} 36import coupledL2.{EnableCHI, L2Param} 37import coupledL2.tl2chi.CHIIssue 38import openLLC.OpenLLCParam 39 40case object SoCParamsKey extends Field[SoCParameters] 41case object CVMParamskey extends Field[CVMParameters] 42 43case class CVMParameters 44( 45 MEMENCRange: AddressSet = AddressSet(0x38030000L, 0xfff), 46 KeyIDBits: Int = 0, 47 MemencPipes: Int = 4, 48 HasMEMencryption: Boolean = false, 49 HasDelayNoencryption: Boolean = false, // Test specific 50) 51 52case class SoCParameters 53( 54 EnableILA: Boolean = false, 55 PAddrBits: Int = 48, 56 PmemRanges: Seq[MemoryRange] = Seq(MemoryRange(0x80000000L, 0x80000000000L)), 57 PMAConfigs: Seq[PMAConfigEntry] = Seq( 58 PMAConfigEntry(0x0L, range = 0x1000000000000L, a = 3), 59 PMAConfigEntry(0x80000000000L, c = true, atomic = true, a = 1, x = true, w = true, r = true), 60 PMAConfigEntry(0x80000000L, a = 1, w = true, r = true), 61 PMAConfigEntry(0x3A000000L, a = 1), 62 PMAConfigEntry(0x39002000L, a = 1, w = true, r = true), 63 PMAConfigEntry(0x39000000L, a = 1, w = true, r = true), 64 PMAConfigEntry(0x38022000L, a = 1, w = true, r = true), 65 PMAConfigEntry(0x38021000L, a = 1, x = true, w = true, r = true), 66 PMAConfigEntry(0x38020000L, a = 1, w = true, r = true), 67 PMAConfigEntry(0x30050000L, a = 1, w = true, r = true), // FIXME: GPU space is cacheable? 68 PMAConfigEntry(0x30010000L, a = 1, w = true, r = true), 69 PMAConfigEntry(0x20000000L, a = 1, x = true, w = true, r = true), 70 PMAConfigEntry(0x10000000L, a = 1, w = true, r = true), 71 PMAConfigEntry(0) 72 ), 73 CLINTRange: AddressSet = AddressSet(0x38000000L, CLINTConsts.size - 1), 74 BEURange: AddressSet = AddressSet(0x38010000L, 0xfff), 75 PLICRange: AddressSet = AddressSet(0x3c000000L, PLICConsts.size(PLICConsts.maxMaxHarts) - 1), 76 PLLRange: AddressSet = AddressSet(0x3a000000L, 0xfff), 77 UARTLiteForDTS: Boolean = true, // should be false in SimMMIO 78 extIntrs: Int = 64, 79 L3NBanks: Int = 4, 80 L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 81 name = "L3", 82 level = 3, 83 ways = 8, 84 sets = 2048 // 1MB per bank 85 )), 86 OpenLLCParamsOpt: Option[OpenLLCParam] = None, 87 XSTopPrefix: Option[String] = None, 88 NodeIDWidthList: Map[String, Int] = Map( 89 "B" -> 7, 90 "C" -> 9, 91 "E.b" -> 11 92 ), 93 NumHart: Int = 64, 94 NumIRFiles: Int = 7, 95 NumIRSrc: Int = 256, 96 UseXSNoCTop: Boolean = false, 97 UseXSNoCDiffTop: Boolean = false, 98 UseXSTileDiffTop: Boolean = false, 99 IMSICUseTL: Boolean = false, 100 SeperateTLBus: Boolean = false, 101 SeperateDM: Boolean = false, // for non-XSNoCTop only, should work with SeperateTLBus 102 SeperateTLBusRanges: Seq[AddressSet] = Seq(), 103 EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 16, sync = 3, safe = false)), 104 EnableClintAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false)), 105 SeperateTLAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false)), 106 WFIClockGate: Boolean = false, 107 EnablePowerDown: Boolean = false 108){ 109 require( 110 L3CacheParamsOpt.isDefined ^ OpenLLCParamsOpt.isDefined || L3CacheParamsOpt.isEmpty && OpenLLCParamsOpt.isEmpty, 111 "Atmost one of L3CacheParamsOpt and OpenLLCParamsOpt should be defined" 112 ) 113 // L3 configurations 114 val L3InnerBusWidth = 256 115 val L3BlockSize = 64 116 // on chip network configurations 117 val L3OuterBusWidth = 256 118 val UARTLiteRange = AddressSet(0x40600000, if (UARTLiteForDTS) 0x3f else 0xf) 119} 120 121trait HasSoCParameter { 122 implicit val p: Parameters 123 124 val soc = p(SoCParamsKey) 125 val cvm = p(CVMParamskey) 126 val debugOpts = p(DebugOptionsKey) 127 val tiles = p(XSTileKey) 128 val enableCHI = p(EnableCHI) 129 val issue = p(CHIIssue) 130 131 val NumCores = tiles.size 132 val EnableILA = soc.EnableILA 133 134 // Parameters for trace extension 135 val TraceTraceGroupNum = tiles.head.traceParams.TraceGroupNum 136 val TraceCauseWidth = tiles.head.XLEN 137 val TraceTvalWidth = tiles.head.traceParams.IaddrWidth 138 val TracePrivWidth = tiles.head.traceParams.PrivWidth 139 val TraceIaddrWidth = tiles.head.traceParams.IaddrWidth 140 val TraceItypeWidth = tiles.head.traceParams.ItypeWidth 141 val TraceIretireWidthCompressed = log2Up(tiles.head.RenameWidth * tiles.head.CommitWidth * 2) 142 val TraceIlastsizeWidth = tiles.head.traceParams.IlastsizeWidth 143 144 // L3 configurations 145 val L3InnerBusWidth = soc.L3InnerBusWidth 146 val L3BlockSize = soc.L3BlockSize 147 val L3NBanks = soc.L3NBanks 148 149 // on chip network configurations 150 val L3OuterBusWidth = soc.L3OuterBusWidth 151 152 val NrExtIntr = soc.extIntrs 153 154 val SetIpNumValidSize = soc.NumHart * soc.NumIRFiles 155 156 val NumIRSrc = soc.NumIRSrc 157 158 val SeperateDM = soc.SeperateDM 159 val SeperateTLBus = soc.SeperateTLBus 160 val SeperateTLBusRanges = soc.SeperateTLBusRanges 161 162 val EnableCHIAsyncBridge = if (enableCHI && soc.EnableCHIAsyncBridge.isDefined) 163 soc.EnableCHIAsyncBridge else None 164 val EnableClintAsyncBridge = soc.EnableClintAsyncBridge 165 val SeperateTLAsyncBridge = if (SeperateTLBus && soc.SeperateTLAsyncBridge.isDefined) 166 soc.SeperateTLAsyncBridge else None 167 168 // seperate TL bus 169 val EnableSeperateTLAsync = SeperateTLAsyncBridge.isDefined 170 171 val WFIClockGate = soc.WFIClockGate 172 val EnablePowerDown = soc.EnablePowerDown 173 174 def HasMEMencryption = cvm.HasMEMencryption 175 require((cvm.HasMEMencryption && (cvm.KeyIDBits > 0)) || (!cvm.HasMEMencryption && (cvm.KeyIDBits == 0)), 176 "HasMEMencryption most set with KeyIDBits > 0") 177} 178 179trait HasPeripheralRanges { 180 implicit val p: Parameters 181 182 private def cvm = p(CVMParamskey) 183 private def soc = p(SoCParamsKey) 184 private def dm = p(DebugModuleKey) 185 private def pmParams = p(PMParameKey) 186 187 private def mmpma = pmParams.mmpma 188 189 def onChipPeripheralRanges: Map[String, AddressSet] = Map( 190 "CLINT" -> soc.CLINTRange, 191 "BEU" -> soc.BEURange, 192 "PLIC" -> soc.PLICRange, 193 "PLL" -> soc.PLLRange, 194 "UART" -> soc.UARTLiteRange, 195 "DEBUG" -> dm.get.address, 196 "MMPMA" -> AddressSet(mmpma.address, mmpma.mask) 197 ) ++ ( 198 if (soc.L3CacheParamsOpt.map(_.ctrl.isDefined).getOrElse(false)) 199 Map("L3CTL" -> AddressSet(soc.L3CacheParamsOpt.get.ctrl.get.address, 0xffff)) 200 else 201 Map() 202 ) ++ ( 203 if (cvm.HasMEMencryption) 204 Map("MEMENC" -> cvm.MEMENCRange) 205 else 206 Map() 207 ) 208 209 def peripheralRange = onChipPeripheralRanges.values.foldLeft(Seq(AddressSet(0x0, 0x7fffffffL))) { (acc, x) => 210 acc.flatMap(_.subtract(x)) 211 } 212} 213 214class ILABundle extends Bundle {} 215 216 217abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter with HasPeripheralRanges { 218 val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize)) 219 val peripheralXbar = Option.when(!enableCHI)(TLXbar()) 220 val l3_xbar = Option.when(!enableCHI)(TLXbar()) 221 val l3_banked_xbar = Option.when(!enableCHI)(TLXbar()) 222 223 val soc_xbar = Option.when(enableCHI)(AXI4Xbar()) 224} 225 226// We adapt the following three traits from rocket-chip. 227// Source: rocket-chip/src/main/scala/subsystem/Ports.scala 228trait HaveSlaveAXI4Port { 229 this: BaseSoC => 230 231 val idBits = 14 232 233 val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters( 234 Seq(AXI4MasterParameters( 235 name = "dma", 236 id = IdRange(0, 1 << idBits) 237 )) 238 ))) 239 240 if (l3_xbar.isDefined) { 241 val errorDevice = LazyModule(new TLError( 242 params = DevNullParams( 243 address = Seq(AddressSet(0x0, 0x7fffffffL)), 244 maxAtomic = 8, 245 maxTransfer = 64), 246 beatBytes = L3InnerBusWidth / 8 247 )) 248 errorDevice.node := 249 l3_xbar.get := 250 TLFIFOFixer() := 251 TLWidthWidget(32) := 252 AXI4ToTL() := 253 AXI4UserYanker(Some(1)) := 254 AXI4Fragmenter() := 255 AXI4Buffer() := 256 AXI4Buffer() := 257 AXI4IdIndexer(1) := 258 l3FrontendAXI4Node 259 } 260 261 val dma = InModuleBody { 262 l3FrontendAXI4Node.makeIOs() 263 } 264} 265 266trait HaveAXI4MemPort { 267 this: BaseSoC => 268 val device = new MemoryDevice 269 // 48-bit physical address 270 val memRange = AddressSet(0x00000000L, 0xffffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL)) 271 val memAXI4SlaveNode = AXI4SlaveNode(Seq( 272 AXI4SlavePortParameters( 273 slaves = Seq( 274 AXI4SlaveParameters( 275 address = memRange, 276 regionType = RegionType.UNCACHED, 277 executable = true, 278 supportsRead = TransferSizes(1, L3BlockSize), 279 supportsWrite = TransferSizes(1, L3BlockSize), 280 interleavedId = Some(0), 281 resources = device.reg("mem") 282 ) 283 ), 284 beatBytes = L3OuterBusWidth / 8, 285 requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey), 286 ) 287 )) 288 289 val mem_xbar = TLXbar() 290 val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true) 291 val axi4mem_node = AXI4IdentityNode() 292 293 if (enableCHI) { 294 axi4mem_node := 295 soc_xbar.get 296 } else { 297 mem_xbar :=* 298 TLBuffer.chainNode(2) := 299 TLCacheCork() := 300 l3_mem_pmu := 301 TLClientsMerger() := 302 TLXbar() :=* 303 bankedNode.get 304 305 mem_xbar := 306 TLWidthWidget(8) := 307 TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) := 308 peripheralXbar.get 309 310 axi4mem_node := 311 TLToAXI4() := 312 TLSourceShrinker(64) := 313 TLWidthWidget(L3OuterBusWidth / 8) := 314 TLBuffer.chainNode(2) := 315 mem_xbar 316 } 317 val axi4memencrpty = Option.when(HasMEMencryption)(LazyModule(new AXI4MemEncrypt(cvm.MEMENCRange))) 318 if (HasMEMencryption) { 319 memAXI4SlaveNode := 320 AXI4Buffer() := 321 AXI4Buffer() := 322 AXI4Buffer() := 323 AXI4IdIndexer(idBits = 14) := 324 AXI4UserYanker() := 325 axi4memencrpty.get.node 326 327 axi4memencrpty.get.node := 328 AXI4Deinterleaver(L3BlockSize) := 329 axi4mem_node 330 } else { 331 memAXI4SlaveNode := 332 AXI4Buffer() := 333 AXI4Buffer() := 334 AXI4Buffer() := 335 AXI4IdIndexer(idBits = 14) := 336 AXI4UserYanker() := 337 AXI4Deinterleaver(L3BlockSize) := 338 axi4mem_node 339 } 340 341 342 val memory = InModuleBody { 343 memAXI4SlaveNode.makeIOs() 344 } 345} 346 347trait HaveAXI4PeripheralPort { this: BaseSoC => 348 val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite")) 349 val uartParams = AXI4SlaveParameters( 350 address = Seq(soc.UARTLiteRange), 351 regionType = RegionType.UNCACHED, 352 supportsRead = TransferSizes(1, 32), 353 supportsWrite = TransferSizes(1, 32), 354 resources = uartDevice.reg 355 ) 356 val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters( 357 Seq(AXI4SlaveParameters( 358 address = peripheralRange, 359 regionType = RegionType.UNCACHED, 360 supportsRead = TransferSizes(1, 32), 361 supportsWrite = TransferSizes(1, 32), 362 interleavedId = Some(0) 363 ), uartParams), 364 beatBytes = 8 365 ))) 366 367 val axi4peripheral_node = AXI4IdentityNode() 368 val error_xbar = Option.when(enableCHI)(TLXbar()) 369 370 peripheralNode := 371 AXI4UserYanker() := 372 AXI4IdIndexer(idBits = 2) := 373 AXI4Buffer() := 374 AXI4Buffer() := 375 AXI4Buffer() := 376 AXI4Buffer() := 377 AXI4UserYanker() := 378 // AXI4Deinterleaver(8) := 379 axi4peripheral_node 380 381 if (enableCHI) { 382 val error = LazyModule(new TLError( 383 params = DevNullParams( 384 address = Seq(AddressSet(0x1000000000000L, 0xffffffffffffL)), 385 maxAtomic = 8, 386 maxTransfer = 64), 387 beatBytes = 8 388 )) 389 error.node := error_xbar.get 390 axi4peripheral_node := 391 AXI4Deinterleaver(8) := 392 TLToAXI4() := 393 error_xbar.get := 394 TLBuffer.chainNode(2, Some("llc_to_peripheral_buffer")) := 395 TLFIFOFixer() := 396 TLWidthWidget(L3OuterBusWidth / 8) := 397 AXI4ToTL() := 398 AXI4UserYanker() := 399 soc_xbar.get 400 } else { 401 axi4peripheral_node := 402 AXI4Deinterleaver(8) := 403 TLToAXI4() := 404 TLBuffer.chainNode(3) := 405 peripheralXbar.get 406 } 407 408 val peripheral = InModuleBody { 409 peripheralNode.makeIOs() 410 } 411 412} 413 414class MemMisc()(implicit p: Parameters) extends BaseSoC 415 with HaveAXI4MemPort 416 with PMAConst 417 with HaveAXI4PeripheralPort 418{ 419 420 val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() }) 421 val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() }) 422 423 val l3_in = TLTempNode() 424 val l3_out = TLTempNode() 425 426 val device_xbar = Option.when(enableCHI)(TLXbar()) 427 device_xbar.foreach(_ := error_xbar.get) 428 429 if (l3_banked_xbar.isDefined) { 430 l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar.get 431 l3_banked_xbar.get := TLBuffer.chainNode(2) := l3_xbar.get 432 } 433 bankedNode match { 434 case Some(bankBinder) => 435 bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out 436 case None => 437 } 438 439 if(soc.L3CacheParamsOpt.isEmpty){ 440 l3_out :*= l3_in 441 } 442 443 if (!enableCHI) { 444 for (port <- peripheral_ports.get) { 445 peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port 446 } 447 } 448 449 core_to_l3_ports.foreach { case _ => 450 for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){ 451 l3_banked_xbar.get :=* 452 TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=* 453 TLBuffer() := 454 core_out 455 } 456 } 457 458 val clint = LazyModule(new CLINT(CLINTParams(soc.CLINTRange.base), 8)) 459 if (enableCHI) { clint.node := device_xbar.get } 460 else { clint.node := peripheralXbar.get } 461 462 class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule { 463 val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1)) 464 class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 465 val in = IO(Input(Vec(num, Bool()))) 466 in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i } 467 } 468 lazy val module = new IntSourceNodeToModuleImp(this) 469 } 470 471 val plic = LazyModule(new TLPLIC(PLICParams(soc.PLICRange.base), 8)) 472 val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr)) 473 474 plic.intnode := plicSource.sourceNode 475 if (enableCHI) { plic.node := device_xbar.get } 476 else { plic.node := peripheralXbar.get } 477 478 val pll_node = TLRegisterNode( 479 address = Seq(soc.PLLRange), 480 device = new SimpleDevice("pll_ctrl", Seq()), 481 beatBytes = 8, 482 concurrency = 1 483 ) 484 if (enableCHI) { pll_node := device_xbar.get } 485 else { pll_node := peripheralXbar.get } 486 487 val debugModule = LazyModule(new DebugModule(NumCores)(p)) 488 val debugModuleXbarOpt = Option.when(SeperateDM)(TLXbar()) 489 if (enableCHI) { 490 if (SeperateDM) { 491 debugModule.debug.node := debugModuleXbarOpt.get 492 } else { 493 debugModule.debug.node := device_xbar.get 494 } 495 debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl => 496 error_xbar.get := sb2tl.node 497 } 498 } else { 499 if (SeperateDM) { 500 debugModule.debug.node := debugModuleXbarOpt.get 501 } else { 502 debugModule.debug.node := peripheralXbar.get 503 } 504 debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl => 505 l3_xbar.get := TLBuffer() := TLWidthWidget(1) := sb2tl.node 506 } 507 } 508 509 val pma = LazyModule(new TLPMA) 510 if (enableCHI) { 511 pma.node := TLBuffer.chainNode(4) := device_xbar.get 512 if (HasMEMencryption) { 513 axi4memencrpty.get.ctrl_node := TLToAPB() := device_xbar.get 514 } 515 } else { 516 pma.node := TLBuffer.chainNode(4) := peripheralXbar.get 517 if (HasMEMencryption) { 518 axi4memencrpty.get.ctrl_node := TLToAPB() := peripheralXbar.get 519 } 520 } 521 522 class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 523 524 val debug_module_io = IO(new debugModule.DebugModuleIO) 525 val ext_intrs = IO(Input(UInt(NrExtIntr.W))) 526 val rtc_clock = IO(Input(Bool())) 527 val pll0_lock = IO(Input(Bool())) 528 val pll0_ctrl = IO(Output(Vec(6, UInt(32.W)))) 529 val cacheable_check = IO(new TLPMAIO) 530 val clintTime = IO(Output(ValidIO(UInt(64.W)))) 531 532 debugModule.module.io <> debug_module_io 533 534 // sync external interrupts 535 require(plicSource.module.in.length == ext_intrs.getWidth) 536 for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) { 537 val ext_intr_sync = RegInit(0.U(3.W)) 538 ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt) 539 plic_in := ext_intr_sync(2) 540 } 541 542 pma.module.io <> cacheable_check 543 544 if (HasMEMencryption) { 545 val cnt = Counter(true.B, 8)._1 546 axi4memencrpty.get.module.io.random_val := axi4memencrpty.get.module.io.random_req && cnt(2).asBool 547 axi4memencrpty.get.module.io.random_data := cnt(0).asBool 548 } 549 // positive edge sampling of the lower-speed rtc_clock 550 val rtcTick = RegInit(0.U(3.W)) 551 rtcTick := Cat(rtcTick(1, 0), rtc_clock) 552 clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2) 553 554 val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) } 555 val pll_lock = RegNext(next = pll0_lock, init = false.B) 556 557 clintTime := clint.module.io.time 558 559 pll0_ctrl <> VecInit(pll_ctrl_regs) 560 561 pll_node.regmap( 562 0x000 -> RegFieldGroup( 563 "Pll", Some("PLL ctrl regs"), 564 pll_ctrl_regs.zipWithIndex.map{ 565 case (r, i) => RegField(32, r, RegFieldDesc( 566 s"PLL_ctrl_$i", 567 desc = s"PLL ctrl register #$i" 568 )) 569 } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc( 570 "PLL_lock", 571 "PLL lock register" 572 )) 573 ) 574 ) 575 } 576 577 lazy val module = new SoCMiscImp(this) 578} 579 580class SoCMisc()(implicit p: Parameters) extends MemMisc 581 with HaveSlaveAXI4Port 582 583