1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.backend.trace._ 33import xiangshan.cache.DCacheParameters 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39import freechips.rocketchip.diplomacy.AddressSet 40import freechips.rocketchip.tile.MaxHartIdBits 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import coupledL2.tl2chi._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.{max, min, pow} 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 PAddrBitsMax: Int = 56, // The bits of physical address from Sv39/Sv48/Sv57 virtual address translation. 72 VAddrBitsSv39: Int = 39, 73 GPAddrBitsSv39x4: Int = 41, 74 VAddrBitsSv48: Int = 48, 75 GPAddrBitsSv48x4: Int = 50, 76 HasFPU: Boolean = true, 77 HasVPU: Boolean = true, 78 HasCustomCSRCacheOp: Boolean = true, 79 FetchWidth: Int = 8, 80 AsidLength: Int = 16, 81 VmidLength: Int = 14, 82 EnableBPU: Boolean = true, 83 EnableBPD: Boolean = true, 84 EnableRAS: Boolean = true, 85 EnableLB: Boolean = false, 86 EnableLoop: Boolean = true, 87 EnableSC: Boolean = true, 88 EnbaleTlbDebug: Boolean = false, 89 EnableClockGate: Boolean = true, 90 EnableJal: Boolean = false, 91 EnableFauFTB: Boolean = true, 92 EnableSv48: Boolean = true, 93 UbtbGHRLength: Int = 4, 94 // HistoryLength: Int = 512, 95 EnableGHistDiff: Boolean = true, 96 EnableCommitGHistDiff: Boolean = true, 97 UbtbSize: Int = 256, 98 FtbSize: Int = 2048, 99 FtbWays: Int = 4, 100 FtbTagLength: Int = 20, 101 RasSize: Int = 16, 102 RasSpecSize: Int = 32, 103 RasCtrSize: Int = 3, 104 CacheLineSize: Int = 512, 105 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 106 // Sets Hist Tag 107 Seq(( 4096, 8, 8), 108 ( 4096, 13, 8), 109 ( 4096, 32, 8), 110 ( 4096, 119, 8)), 111 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 112 // Sets Hist Tag 113 Seq(( 256, 4, 9), 114 ( 256, 8, 9), 115 ( 512, 13, 9), 116 ( 512, 16, 9), 117 ( 512, 32, 9)), 118 SCNRows: Int = 512, 119 SCNTables: Int = 4, 120 SCCtrBits: Int = 6, 121 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 122 numBr: Int = 2, 123 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 124 (resp_in: BranchPredictionResp, p: Parameters) => { 125 val ftb = Module(new FTB()(p)) 126 val uftb = Module(new FauFTB()(p)) 127 val tage = Module(new Tage_SC()(p)) 128 val ras = Module(new RAS()(p)) 129 val ittage = Module(new ITTage()(p)) 130 val preds = Seq(uftb, tage, ftb, ittage, ras) 131 preds.map(_.io := DontCare) 132 133 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 134 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 135 136 uftb.io.in.bits.resp_in(0) := resp_in 137 tage.io.in.bits.resp_in(0) := uftb.io.out 138 ftb.io.in.bits.resp_in(0) := tage.io.out 139 ittage.io.in.bits.resp_in(0) := ftb.io.out 140 ras.io.in.bits.resp_in(0) := ittage.io.out 141 142 (preds, ras.io.out) 143 }, 144 ICacheForceMetaECCError: Boolean = false, 145 ICacheForceDataECCError: Boolean = false, 146 IBufSize: Int = 48, 147 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 148 DecodeWidth: Int = 6, 149 RenameWidth: Int = 6, 150 CommitWidth: Int = 8, 151 RobCommitWidth: Int = 8, 152 RabCommitWidth: Int = 6, 153 MaxUopSize: Int = 65, 154 EnableRenameSnapshot: Boolean = true, 155 RenameSnapshotNum: Int = 4, 156 FtqSize: Int = 64, 157 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 158 IntLogicRegs: Int = 32, 159 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 160 VecLogicRegs: Int = 32 + 15, // 15: tmp 161 V0LogicRegs: Int = 1, // V0 162 VlLogicRegs: Int = 1, // Vl 163 V0_IDX: Int = 0, 164 Vl_IDX: Int = 0, 165 NRPhyRegs: Int = 192, 166 VirtualLoadQueueSize: Int = 72, 167 LoadQueueRARSize: Int = 72, 168 LoadQueueRAWSize: Int = 32, // NOTE: make sure that LoadQueueRAWSize is power of 2. 169 RollbackGroupSize: Int = 8, 170 LoadQueueReplaySize: Int = 72, 171 LoadUncacheBufferSize: Int = 4, 172 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 173 StoreQueueSize: Int = 56, 174 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 175 StoreQueueForwardWithMask: Boolean = true, 176 VlsQueueSize: Int = 8, 177 RobSize: Int = 160, 178 RabSize: Int = 256, 179 VTypeBufferSize: Int = 64, // used to reorder vtype 180 IssueQueueSize: Int = 24, 181 IssueQueueCompEntrySize: Int = 16, 182 dpParams: DispatchParameters = DispatchParameters( 183 IntDqSize = 16, 184 FpDqSize = 16, 185 LsDqSize = 18, 186 IntDqDeqWidth = 8, 187 FpDqDeqWidth = 6, 188 VecDqDeqWidth = 6, 189 LsDqDeqWidth = 6, 190 ), 191 intPreg: PregParams = IntPregParams( 192 numEntries = 224, 193 numRead = None, 194 numWrite = None, 195 ), 196 fpPreg: PregParams = FpPregParams( 197 numEntries = 192, 198 numRead = None, 199 numWrite = None, 200 ), 201 vfPreg: VfPregParams = VfPregParams( 202 numEntries = 128, 203 numRead = None, 204 numWrite = None, 205 ), 206 v0Preg: V0PregParams = V0PregParams( 207 numEntries = 22, 208 numRead = None, 209 numWrite = None, 210 ), 211 vlPreg: VlPregParams = VlPregParams( 212 numEntries = 32, 213 numRead = None, 214 numWrite = None, 215 ), 216 IntRegCacheSize: Int = 16, 217 MemRegCacheSize: Int = 12, 218 intSchdVlWbPort: Int = 0, 219 vfSchdVlWbPort: Int = 1, 220 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 221 IfuRedirectNum: Int = 1, 222 LoadPipelineWidth: Int = 3, 223 StorePipelineWidth: Int = 2, 224 VecLoadPipelineWidth: Int = 2, 225 VecStorePipelineWidth: Int = 2, 226 VecMemSrcInWidth: Int = 2, 227 VecMemInstWbWidth: Int = 1, 228 VecMemDispatchWidth: Int = 1, 229 VecMemDispatchMaxNumber: Int = 16, 230 VecMemUnitStrideMaxFlowNum: Int = 2, 231 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 16, 16, 16, 16, 16), 232 StoreBufferSize: Int = 16, 233 StoreBufferThreshold: Int = 7, 234 EnsbufferWidth: Int = 2, 235 LoadDependencyWidth: Int = 2, 236 // ============ VLSU ============ 237 VlMergeBufferSize: Int = 16, 238 VsMergeBufferSize: Int = 16, 239 UopWritebackWidth: Int = 2, 240 VLUopWritebackWidth: Int = 2, 241 VSUopWritebackWidth: Int = 1, 242 VSegmentBufferSize: Int = 8, 243 VFOFBufferSize: Int = 8, 244 VLFOFWritebackWidth: Int = 1, 245 // ============================== 246 UncacheBufferSize: Int = 4, 247 EnableLoadToLoadForward: Boolean = false, 248 EnableFastForward: Boolean = true, 249 EnableLdVioCheckAfterReset: Boolean = true, 250 EnableSoftPrefetchAfterReset: Boolean = true, 251 EnableCacheErrorAfterReset: Boolean = true, 252 EnableAccurateLoadError: Boolean = false, 253 EnableUncacheWriteOutstanding: Boolean = false, 254 EnableHardwareStoreMisalign: Boolean = true, 255 EnableHardwareLoadMisalign: Boolean = true, 256 EnableStorePrefetchAtIssue: Boolean = false, 257 EnableStorePrefetchAtCommit: Boolean = false, 258 EnableAtCommitMissTrigger: Boolean = true, 259 EnableStorePrefetchSMS: Boolean = false, 260 EnableStorePrefetchSPB: Boolean = false, 261 HasCMO: Boolean = true, 262 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 263 MMUVmidLen: Int = 14, 264 ReSelectLen: Int = 7, // load replay queue replay select counter len 265 iwpuParameters: WPUParameters = WPUParameters( 266 enWPU = false, 267 algoName = "mmru", 268 isICache = true, 269 ), 270 dwpuParameters: WPUParameters = WPUParameters( 271 enWPU = false, 272 algoName = "mmru", 273 enCfPred = false, 274 isICache = false, 275 ), 276 itlbParameters: TLBParameters = TLBParameters( 277 name = "itlb", 278 fetchi = true, 279 useDmode = false, 280 NWays = 48, 281 ), 282 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 283 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 284 ldtlbParameters: TLBParameters = TLBParameters( 285 name = "ldtlb", 286 NWays = 48, 287 outReplace = false, 288 partialStaticPMP = true, 289 outsideRecvFlush = true, 290 saveLevel = false, 291 lgMaxSize = 4 292 ), 293 sttlbParameters: TLBParameters = TLBParameters( 294 name = "sttlb", 295 NWays = 48, 296 outReplace = false, 297 partialStaticPMP = true, 298 outsideRecvFlush = true, 299 saveLevel = false, 300 lgMaxSize = 4 301 ), 302 hytlbParameters: TLBParameters = TLBParameters( 303 name = "hytlb", 304 NWays = 48, 305 outReplace = false, 306 partialStaticPMP = true, 307 outsideRecvFlush = true, 308 saveLevel = false, 309 lgMaxSize = 4 310 ), 311 pftlbParameters: TLBParameters = TLBParameters( 312 name = "pftlb", 313 NWays = 48, 314 outReplace = false, 315 partialStaticPMP = true, 316 outsideRecvFlush = true, 317 saveLevel = false, 318 lgMaxSize = 4 319 ), 320 l2ToL1tlbParameters: TLBParameters = TLBParameters( 321 name = "l2tlb", 322 NWays = 48, 323 outReplace = false, 324 partialStaticPMP = true, 325 outsideRecvFlush = true, 326 saveLevel = false 327 ), 328 refillBothTlb: Boolean = false, 329 btlbParameters: TLBParameters = TLBParameters( 330 name = "btlb", 331 NWays = 48, 332 ), 333 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 334 NumPerfCounters: Int = 16, 335 icacheParameters: ICacheParameters = ICacheParameters( 336 tagECC = Some("parity"), 337 dataECC = Some("parity"), 338 replacer = Some("setplru"), 339 cacheCtrlAddressOpt = Some(AddressSet(0x38022080, 0x7f)) 340 ), 341 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 342 tagECC = Some("secded"), 343 dataECC = Some("secded"), 344 replacer = Some("setplru"), 345 nMissEntries = 16, 346 nProbeEntries = 8, 347 nReleaseEntries = 18, 348 nMaxPrefetchEntry = 6, 349 enableTagEcc = true, 350 enableDataEcc = true, 351 cacheCtrlAddressOpt = Some(AddressSet(0x38022000, 0x7f)) 352 )), 353 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 354 name = "l2", 355 ways = 8, 356 sets = 1024, // default 512KB L2 357 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 358 coupledL2.prefetch.TPParameters()), 359 )), 360 L2NBanks: Int = 1, 361 usePTWRepeater: Boolean = false, 362 softTLB: Boolean = false, // dpi-c l1tlb debug only 363 softPTW: Boolean = false, // dpi-c l2tlb debug only 364 softPTWDelay: Int = 1 365){ 366 def ISABase = "rv64i" 367 def ISAExtensions = Seq( 368 // single letter extensions, in canonical order 369 "i", "m", "a", "f", "d", "c", /* "b", */ "v", "h", 370 // multi-letter extensions, sorted alphanumerically 371 "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", 372 "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", 373 "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", 374 "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", 375 "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", 376 "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", 377 "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", 378 "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", 379 "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b" 380 ) 381 382 def vlWidth = log2Up(VLEN) + 1 383 384 /** 385 * the minimum element length of vector elements 386 */ 387 val minVecElen: Int = 8 388 389 /** 390 * the maximum number of elements in vector register 391 */ 392 val maxElemPerVreg: Int = VLEN / minVecElen 393 394 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 395 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 396 397 val RegCacheSize = IntRegCacheSize + MemRegCacheSize 398 val RegCacheIdxWidth = log2Up(RegCacheSize) 399 400 val intSchdParams = { 401 implicit val schdType: SchedulerType = IntScheduler() 402 SchdBlockParams(Seq( 403 IssueBlockParams(Seq( 404 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 405 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1))), true, 2), 406 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 407 IssueBlockParams(Seq( 408 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 409 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1))), true, 2), 410 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 411 IssueBlockParams(Seq( 412 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 413 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = intSchdVlWbPort, 0), FpWB(port = 2, 1)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 414 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 415 IssueBlockParams(Seq( 416 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 417 ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 418 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 419 ), 420 numPregs = intPreg.numEntries, 421 numDeqOutside = 0, 422 schdType = schdType, 423 rfDataWidth = intPreg.dataCfg.dataWidth, 424 numUopIn = dpParams.IntDqDeqWidth, 425 ) 426 } 427 428 val fpSchdParams = { 429 implicit val schdType: SchedulerType = FpScheduler() 430 SchdBlockParams(Seq( 431 IssueBlockParams(Seq( 432 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 433 ExeUnitParams("FEX1", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 434 ), numEntries = 18, numEnq = 2, numComp = 14), 435 IssueBlockParams(Seq( 436 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 437 ExeUnitParams("FEX3", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(9, 1)))), 438 ), numEntries = 18, numEnq = 2, numComp = 14), 439 IssueBlockParams(Seq( 440 ExeUnitParams("FEX4", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 1)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 441 ), numEntries = 18, numEnq = 2, numComp = 14), 442 ), 443 numPregs = fpPreg.numEntries, 444 numDeqOutside = 0, 445 schdType = schdType, 446 rfDataWidth = fpPreg.dataCfg.dataWidth, 447 numUopIn = dpParams.FpDqDeqWidth, 448 ) 449 } 450 451 val vfSchdParams = { 452 implicit val schdType: SchedulerType = VfScheduler() 453 SchdBlockParams(Seq( 454 IssueBlockParams(Seq( 455 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 456 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = vfSchdVlWbPort, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 457 ), numEntries = 16, numEnq = 2, numComp = 12), 458 IssueBlockParams(Seq( 459 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 460 ExeUnitParams("VFEX3", Seq(VfaluCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 461 ), numEntries = 16, numEnq = 2, numComp = 12), 462 IssueBlockParams(Seq( 463 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 464 ), numEntries = 10, numEnq = 2, numComp = 6), 465 ), 466 numPregs = vfPreg.numEntries, 467 numDeqOutside = 0, 468 schdType = schdType, 469 rfDataWidth = vfPreg.dataCfg.dataWidth, 470 numUopIn = dpParams.VecDqDeqWidth, 471 ) 472 } 473 474 val memSchdParams = { 475 implicit val schdType: SchedulerType = MemScheduler() 476 val rfDataWidth = 64 477 478 SchdBlockParams(Seq( 479 IssueBlockParams(Seq( 480 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(7, 2)))), 481 ), numEntries = 16, numEnq = 2, numComp = 12), 482 IssueBlockParams(Seq( 483 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(6, 2)))), 484 ), numEntries = 16, numEnq = 2, numComp = 12), 485 IssueBlockParams(Seq( 486 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(3, 0)), Seq(Seq(IntRD(8, 0))), true, 2), 487 ), numEntries = 16, numEnq = 2, numComp = 12), 488 IssueBlockParams(Seq( 489 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(4, 0)), Seq(Seq(IntRD(9, 0))), true, 2), 490 ), numEntries = 16, numEnq = 2, numComp = 12), 491 IssueBlockParams(Seq( 492 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(5, 0)), Seq(Seq(IntRD(10, 0))), true, 2), 493 ), numEntries = 16, numEnq = 2, numComp = 12), 494 IssueBlockParams(Seq( 495 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0), VlWB(port = 2, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 496 ), numEntries = 16, numEnq = 2, numComp = 12), 497 IssueBlockParams(Seq( 498 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0), VlWB(port = 3, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 499 ), numEntries = 16, numEnq = 2, numComp = 12), 500 IssueBlockParams(Seq( 501 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(9, 0)))), 502 ), numEntries = 16, numEnq = 2, numComp = 12), 503 IssueBlockParams(Seq( 504 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(10, 0)))), 505 ), numEntries = 16, numEnq = 2, numComp = 12), 506 ), 507 numPregs = intPreg.numEntries max vfPreg.numEntries, 508 numDeqOutside = 0, 509 schdType = schdType, 510 rfDataWidth = rfDataWidth, 511 numUopIn = dpParams.LsDqDeqWidth, 512 ) 513 } 514 515 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 516 517 def iqWakeUpParams = { 518 Seq( 519 WakeUpConfig( 520 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 521 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 522 ), 523 // TODO: add load -> fp slow wakeup 524 WakeUpConfig( 525 Seq("FEX0", "FEX2", "FEX4") -> 526 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4") 527 ), 528 ).flatten 529 } 530 531 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 532 533 val backendParams: BackendParams = backend.BackendParams( 534 Map( 535 IntScheduler() -> intSchdParams, 536 FpScheduler() -> fpSchdParams, 537 VfScheduler() -> vfSchdParams, 538 MemScheduler() -> memSchdParams, 539 ), 540 Seq( 541 intPreg, 542 fpPreg, 543 vfPreg, 544 v0Preg, 545 vlPreg, 546 fakeIntPreg 547 ), 548 iqWakeUpParams, 549 ) 550 551 // Parameters for trace extension. 552 // Trace parameters is useful for XSTOP. 553 val traceParams: TraceParams = new TraceParams( 554 TraceGroupNum = 3, 555 IaddrWidth = GPAddrBitsSv48x4, 556 PrivWidth = 3, 557 ItypeWidth = 4, 558 IlastsizeWidth = 1, 559 ) 560} 561 562case object DebugOptionsKey extends Field[DebugOptions] 563 564case class DebugOptions 565( 566 FPGAPlatform: Boolean = false, 567 ResetGen: Boolean = false, 568 EnableDifftest: Boolean = false, 569 AlwaysBasicDiff: Boolean = true, 570 EnableDebug: Boolean = false, 571 EnablePerfDebug: Boolean = true, 572 PerfLevel: String = "VERBOSE", 573 UseDRAMSim: Boolean = false, 574 EnableConstantin: Boolean = false, 575 EnableChiselDB: Boolean = false, 576 AlwaysBasicDB: Boolean = true, 577 EnableRollingDB: Boolean = false 578) 579 580trait HasXSParameter { 581 582 implicit val p: Parameters 583 584 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 585 def PmemRanges = p(SoCParamsKey).PmemRanges 586 final val PageOffsetWidth = 12 587 def NodeIDWidth = p(SoCParamsKey).NodeIDWidthList(p(CHIIssue)) // NodeID width among NoC 588 589 def coreParams = p(XSCoreParamsKey) 590 def env = p(DebugOptionsKey) 591 592 def ISABase = coreParams.ISABase 593 def ISAExtensions = coreParams.ISAExtensions 594 def XLEN = coreParams.XLEN 595 def VLEN = coreParams.VLEN 596 def ELEN = coreParams.ELEN 597 def HSXLEN = coreParams.HSXLEN 598 val minFLen = 32 599 val fLen = 64 600 def hartIdLen = p(MaxHartIdBits) 601 val xLen = XLEN 602 603 def HasMExtension = coreParams.HasMExtension 604 def HasCExtension = coreParams.HasCExtension 605 def HasHExtension = coreParams.HasHExtension 606 def EnableSv48 = coreParams.EnableSv48 607 def HasDiv = coreParams.HasDiv 608 def HasIcache = coreParams.HasICache 609 def HasDcache = coreParams.HasDCache 610 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 611 def PAddrBitsMax = coreParams.PAddrBitsMax 612 def GPAddrBitsSv39x4 = coreParams.GPAddrBitsSv39x4 613 def GPAddrBitsSv48x4 = coreParams.GPAddrBitsSv48x4 614 def GPAddrBits = { 615 if (EnableSv48) 616 coreParams.GPAddrBitsSv48x4 617 else 618 coreParams.GPAddrBitsSv39x4 619 } 620 def VAddrBits = { 621 if (HasHExtension) { 622 if (EnableSv48) 623 coreParams.GPAddrBitsSv48x4 624 else 625 coreParams.GPAddrBitsSv39x4 626 } else { 627 if (EnableSv48) 628 coreParams.VAddrBitsSv48 629 else 630 coreParams.VAddrBitsSv39 631 } 632 } // VAddrBits is Virtual Memory addr bits 633 634 def VAddrMaxBits = { 635 if(EnableSv48) { 636 coreParams.VAddrBitsSv48 max coreParams.GPAddrBitsSv48x4 637 } else { 638 coreParams.VAddrBitsSv39 max coreParams.GPAddrBitsSv39x4 639 } 640 } 641 642 def AsidLength = coreParams.AsidLength 643 def VmidLength = coreParams.VmidLength 644 def ReSelectLen = coreParams.ReSelectLen 645 def AddrBytes = AddrBits / 8 // unused 646 def DataBits = XLEN 647 def DataBytes = DataBits / 8 648 def QuadWordBits = DataBits * 2 649 def QuadWordBytes = QuadWordBits / 8 650 def VDataBytes = VLEN / 8 651 def HasFPU = coreParams.HasFPU 652 def HasVPU = coreParams.HasVPU 653 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 654 def FetchWidth = coreParams.FetchWidth 655 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 656 def EnableBPU = coreParams.EnableBPU 657 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 658 def EnableRAS = coreParams.EnableRAS 659 def EnableLB = coreParams.EnableLB 660 def EnableLoop = coreParams.EnableLoop 661 def EnableSC = coreParams.EnableSC 662 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 663 def HistoryLength = coreParams.HistoryLength 664 def EnableGHistDiff = coreParams.EnableGHistDiff 665 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 666 def EnableClockGate = coreParams.EnableClockGate 667 def UbtbGHRLength = coreParams.UbtbGHRLength 668 def UbtbSize = coreParams.UbtbSize 669 def EnableFauFTB = coreParams.EnableFauFTB 670 def FtbSize = coreParams.FtbSize 671 def FtbWays = coreParams.FtbWays 672 def FtbTagLength = coreParams.FtbTagLength 673 def RasSize = coreParams.RasSize 674 def RasSpecSize = coreParams.RasSpecSize 675 def RasCtrSize = coreParams.RasCtrSize 676 677 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 678 coreParams.branchPredictor(resp_in, p) 679 } 680 def numBr = coreParams.numBr 681 def TageTableInfos = coreParams.TageTableInfos 682 def TageBanks = coreParams.numBr 683 def SCNRows = coreParams.SCNRows 684 def SCCtrBits = coreParams.SCCtrBits 685 def SCHistLens = coreParams.SCHistLens 686 def SCNTables = coreParams.SCNTables 687 688 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 689 case ((n, cb), h) => (n, cb, h) 690 } 691 def ITTageTableInfos = coreParams.ITTageTableInfos 692 type FoldedHistoryInfo = Tuple2[Int, Int] 693 def foldedGHistInfos = 694 (TageTableInfos.map{ case (nRows, h, t) => 695 if (h > 0) 696 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 697 else 698 Set[FoldedHistoryInfo]() 699 }.reduce(_++_).toSet ++ 700 SCTableInfos.map{ case (nRows, _, h) => 701 if (h > 0) 702 Set((h, min(log2Ceil(nRows/TageBanks), h))) 703 else 704 Set[FoldedHistoryInfo]() 705 }.reduce(_++_).toSet ++ 706 ITTageTableInfos.map{ case (nRows, h, t) => 707 if (h > 0) 708 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 709 else 710 Set[FoldedHistoryInfo]() 711 }.reduce(_++_) ++ 712 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 713 ).toList 714 715 716 717 def CacheLineSize = coreParams.CacheLineSize 718 def CacheLineHalfWord = CacheLineSize / 16 719 def ExtHistoryLength = HistoryLength + 64 720 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 721 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 722 def IBufSize = coreParams.IBufSize 723 def IBufNBank = coreParams.IBufNBank 724 def backendParams: BackendParams = coreParams.backendParams 725 def DecodeWidth = coreParams.DecodeWidth 726 def RenameWidth = coreParams.RenameWidth 727 def CommitWidth = coreParams.CommitWidth 728 def RobCommitWidth = coreParams.RobCommitWidth 729 def RabCommitWidth = coreParams.RabCommitWidth 730 def MaxUopSize = coreParams.MaxUopSize 731 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 732 def RenameSnapshotNum = coreParams.RenameSnapshotNum 733 def FtqSize = coreParams.FtqSize 734 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 735 def IntLogicRegs = coreParams.IntLogicRegs 736 def FpLogicRegs = coreParams.FpLogicRegs 737 def VecLogicRegs = coreParams.VecLogicRegs 738 def V0LogicRegs = coreParams.V0LogicRegs 739 def VlLogicRegs = coreParams.VlLogicRegs 740 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 741 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 742 def V0_IDX = coreParams.V0_IDX 743 def Vl_IDX = coreParams.Vl_IDX 744 def IntPhyRegs = coreParams.intPreg.numEntries 745 def FpPhyRegs = coreParams.fpPreg.numEntries 746 def VfPhyRegs = coreParams.vfPreg.numEntries 747 def V0PhyRegs = coreParams.v0Preg.numEntries 748 def VlPhyRegs = coreParams.vlPreg.numEntries 749 def MaxPhyRegs = Seq(IntPhyRegs, FpPhyRegs, VfPhyRegs, V0PhyRegs, VlPhyRegs).max 750 def IntPhyRegIdxWidth = log2Up(IntPhyRegs) 751 def FpPhyRegIdxWidth = log2Up(FpPhyRegs) 752 def VfPhyRegIdxWidth = log2Up(VfPhyRegs) 753 def V0PhyRegIdxWidth = log2Up(V0PhyRegs) 754 def VlPhyRegIdxWidth = log2Up(VlPhyRegs) 755 def PhyRegIdxWidth = Seq(IntPhyRegIdxWidth, FpPhyRegIdxWidth, VfPhyRegIdxWidth, V0PhyRegIdxWidth, VlPhyRegIdxWidth).max 756 def RobSize = coreParams.RobSize 757 def RabSize = coreParams.RabSize 758 def VTypeBufferSize = coreParams.VTypeBufferSize 759 def IntRegCacheSize = coreParams.IntRegCacheSize 760 def MemRegCacheSize = coreParams.MemRegCacheSize 761 def RegCacheSize = coreParams.RegCacheSize 762 def RegCacheIdxWidth = coreParams.RegCacheIdxWidth 763 /** 764 * the minimum element length of vector elements 765 */ 766 def minVecElen: Int = coreParams.minVecElen 767 768 /** 769 * the maximum number of elements in vector register 770 */ 771 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 772 773 def IntRefCounterWidth = log2Ceil(RobSize) 774 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 775 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 776 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 777 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 778 def LoadQueueRARSize = coreParams.LoadQueueRARSize 779 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 780 def RollbackGroupSize = coreParams.RollbackGroupSize 781 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 782 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 783 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 784 def StoreQueueSize = coreParams.StoreQueueSize 785 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 786 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 787 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 788 def VlsQueueSize = coreParams.VlsQueueSize 789 def dpParams = coreParams.dpParams 790 791 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 792 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 793 794 def NumRedirect = backendParams.numRedirect 795 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 796 def FtqRedirectAheadNum = NumRedirect 797 def IfuRedirectNum = coreParams.IfuRedirectNum 798 def LoadPipelineWidth = coreParams.LoadPipelineWidth 799 def StorePipelineWidth = coreParams.StorePipelineWidth 800 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 801 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 802 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 803 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 804 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 805 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 806 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 807 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 808 def StoreBufferSize = coreParams.StoreBufferSize 809 def StoreBufferThreshold = coreParams.StoreBufferThreshold 810 def EnsbufferWidth = coreParams.EnsbufferWidth 811 def LoadDependencyWidth = coreParams.LoadDependencyWidth 812 def VlMergeBufferSize = coreParams.VlMergeBufferSize 813 def VsMergeBufferSize = coreParams.VsMergeBufferSize 814 def UopWritebackWidth = coreParams.UopWritebackWidth 815 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 816 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 817 def VSegmentBufferSize = coreParams.VSegmentBufferSize 818 def VFOFBufferSize = coreParams.VFOFBufferSize 819 def UncacheBufferSize = coreParams.UncacheBufferSize 820 def UncacheBufferIndexWidth = log2Up(UncacheBufferSize) 821 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 822 def EnableFastForward = coreParams.EnableFastForward 823 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 824 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 825 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 826 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 827 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 828 def EnableHardwareStoreMisalign = coreParams.EnableHardwareStoreMisalign 829 def EnableHardwareLoadMisalign = coreParams.EnableHardwareLoadMisalign 830 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 831 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 832 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 833 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 834 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 835 def HasCMO = coreParams.HasCMO && p(EnableCHI) 836 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 837 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 838 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 839 def asidLen = coreParams.MMUAsidLen 840 def vmidLen = coreParams.MMUVmidLen 841 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 842 def refillBothTlb = coreParams.refillBothTlb 843 def iwpuParam = coreParams.iwpuParameters 844 def dwpuParam = coreParams.dwpuParameters 845 def itlbParams = coreParams.itlbParameters 846 def ldtlbParams = coreParams.ldtlbParameters 847 def sttlbParams = coreParams.sttlbParameters 848 def hytlbParams = coreParams.hytlbParameters 849 def pftlbParams = coreParams.pftlbParameters 850 def l2ToL1Params = coreParams.l2ToL1tlbParameters 851 def btlbParams = coreParams.btlbParameters 852 def l2tlbParams = coreParams.l2tlbParameters 853 def NumPerfCounters = coreParams.NumPerfCounters 854 855 def instBytes = if (HasCExtension) 2 else 4 856 def instOffsetBits = log2Ceil(instBytes) 857 858 def icacheParameters = coreParams.icacheParameters 859 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 860 861 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 862 // for constrained LR/SC loop 863 def LRSCCycles = 64 864 // for lr storm 865 def LRSCBackOff = 8 866 867 // cache hierarchy configurations 868 def l1BusDataWidth = 256 869 870 // load violation predict 871 def ResetTimeMax2Pow = 20 //1078576 872 def ResetTimeMin2Pow = 10 //1024 873 // wait table parameters 874 def WaitTableSize = 1024 875 def MemPredPCWidth = log2Up(WaitTableSize) 876 def LWTUse2BitCounter = true 877 // store set parameters 878 def SSITSize = WaitTableSize 879 def LFSTSize = 32 880 def SSIDWidth = log2Up(LFSTSize) 881 def LFSTWidth = 4 882 def StoreSetEnable = true // LWT will be disabled if SS is enabled 883 def LFSTEnable = true 884 885 def PCntIncrStep: Int = 6 886 def numPCntHc: Int = 12 887 def numPCntPtw: Int = 19 888 889 def numCSRPCntFrontend = 8 890 def numCSRPCntCtrl = 8 891 def numCSRPCntLsu = 8 892 def numCSRPCntHc = 5 893 def printEventCoding = true 894 def printCriticalError = false 895 def maxCommitStuck = pow(2, 21).toInt 896 897 // Vector load exception 898 def maxMergeNumPerCycle = 4 899 900 // Parameters for Sdtrig extension 901 protected def TriggerNum = 4 902 protected def TriggerChainMaxLength = 2 903 904 // Parameters for Trace extension 905 def TraceGroupNum = coreParams.traceParams.TraceGroupNum 906 def CauseWidth = XLEN 907 def TvalWidth = coreParams.traceParams.IaddrWidth 908 def PrivWidth = coreParams.traceParams.PrivWidth 909 def IaddrWidth = coreParams.traceParams.IaddrWidth 910 def ItypeWidth = coreParams.traceParams.ItypeWidth 911 def IretireWidthInPipe = log2Up(RenameWidth * 2) 912 def IretireWidthCompressed = log2Up(RenameWidth * CommitWidth * 2) 913 def IlastsizeWidth = coreParams.traceParams.IlastsizeWidth 914} 915