1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, SchedulerType} 19import xiangshan.backend.issue.EntryBundles._ 20import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 21import xiangshan.backend.rob.RobPtr 22import xiangshan.frontend._ 23import xiangshan.mem.{LqPtr, SqPtr} 24import yunsuan.vector.VIFuParam 25import xiangshan.backend.trace._ 26 27object Bundles { 28 /** 29 * Connect Same Name Port like bundleSource := bundleSinkBudle. 30 * 31 * There is no limit to the number of ports on both sides. 32 * 33 * Don't forget to connect the remaining ports! 34 */ 35 def connectSamePort (bundleSource: Bundle, bundleSink: Bundle):Unit = { 36 bundleSource.elements.foreach { case (name, data) => 37 if (bundleSink.elements.contains(name)) 38 data := bundleSink.elements(name) 39 } 40 } 41 // frontend -> backend 42 class StaticInst(implicit p: Parameters) extends XSBundle { 43 val instr = UInt(32.W) 44 val pc = UInt(VAddrBits.W) 45 val foldpc = UInt(MemPredPCWidth.W) 46 val exceptionVec = ExceptionVec() 47 val isFetchMalAddr = Bool() 48 val trigger = TriggerAction() 49 val preDecodeInfo = new PreDecodeInfo 50 val pred_taken = Bool() 51 val crossPageIPFFix = Bool() 52 val ftqPtr = new FtqPtr 53 val ftqOffset = UInt(log2Up(PredictWidth).W) 54 val isLastInFtqEntry = Bool() 55 56 def connectCtrlFlow(source: CtrlFlow): Unit = { 57 this.instr := source.instr 58 this.pc := source.pc 59 this.foldpc := source.foldpc 60 this.exceptionVec := source.exceptionVec 61 this.isFetchMalAddr := source.backendException 62 this.trigger := source.trigger 63 this.preDecodeInfo := source.pd 64 this.pred_taken := source.pred_taken 65 this.crossPageIPFFix := source.crossPageIPFFix 66 this.ftqPtr := source.ftqPtr 67 this.ftqOffset := source.ftqOffset 68 this.isLastInFtqEntry := source.isLastInFtqEntry 69 } 70 } 71 72 // StaticInst --[Decode]--> DecodedInst 73 class DecodedInst(implicit p: Parameters) extends XSBundle { 74 def numSrc = backendParams.numSrc 75 // passed from StaticInst 76 val instr = UInt(32.W) 77 val pc = UInt(VAddrBits.W) 78 val foldpc = UInt(MemPredPCWidth.W) 79 val exceptionVec = ExceptionVec() 80 val isFetchMalAddr = Bool() 81 val trigger = TriggerAction() 82 val preDecodeInfo = new PreDecodeInfo 83 val pred_taken = Bool() 84 val crossPageIPFFix = Bool() 85 val ftqPtr = new FtqPtr 86 val ftqOffset = UInt(log2Up(PredictWidth).W) 87 // decoded 88 val srcType = Vec(numSrc, SrcType()) 89 val lsrc = Vec(numSrc, UInt(LogicRegsWidth.W)) 90 val ldest = UInt(LogicRegsWidth.W) 91 val fuType = FuType() 92 val fuOpType = FuOpType() 93 val rfWen = Bool() 94 val fpWen = Bool() 95 val vecWen = Bool() 96 val v0Wen = Bool() 97 val vlWen = Bool() 98 val isXSTrap = Bool() 99 val waitForward = Bool() // no speculate execution 100 val blockBackward = Bool() 101 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 102 val canRobCompress = Bool() 103 val selImm = SelImm() 104 val imm = UInt(ImmUnion.maxLen.W) 105 val fpu = new FPUCtrlSignals 106 val vpu = new VPUCtrlSignals 107 val vlsInstr = Bool() 108 val wfflags = Bool() 109 val isMove = Bool() 110 val uopIdx = UopIdx() 111 val uopSplitType = UopSplitType() 112 val isVset = Bool() 113 val firstUop = Bool() 114 val lastUop = Bool() 115 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 116 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 117 val commitType = CommitType() // Todo: remove it 118 val needFrm = new NeedFrmBundle 119 120 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 121 122 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 123 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 124 125 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 126 val decoder: Seq[UInt] = ListLookup( 127 inst, XDecode.decodeDefault.map(bitPatToUInt), 128 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 129 ) 130 allSignals zip decoder foreach { case (s, d) => s := d } 131 debug_fuType.foreach(_ := fuType) 132 this 133 } 134 135 def isSoftPrefetch: Bool = { 136 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 137 } 138 139 def connectStaticInst(source: StaticInst): Unit = { 140 for ((name, data) <- this.elements) { 141 if (source.elements.contains(name)) { 142 data := source.elements(name) 143 } 144 } 145 } 146 } 147 148 class TrapInstInfo(implicit p: Parameters) extends XSBundle { 149 val instr = UInt(32.W) 150 val ftqPtr = new FtqPtr 151 val ftqOffset = UInt(log2Up(PredictWidth).W) 152 153 def needFlush(ftqPtr: FtqPtr, ftqOffset: UInt): Bool ={ 154 val sameFlush = this.ftqPtr === ftqPtr && this.ftqOffset > ftqOffset 155 sameFlush || isAfter(this.ftqPtr, ftqPtr) 156 } 157 158 def fromDecodedInst(decodedInst: DecodedInst): this.type = { 159 this.instr := decodedInst.instr 160 this.ftqPtr := decodedInst.ftqPtr 161 this.ftqOffset := decodedInst.ftqOffset 162 this 163 } 164 } 165 166 // DecodedInst --[Rename]--> DynInst 167 class DynInst(implicit p: Parameters) extends XSBundle { 168 def numSrc = backendParams.numSrc 169 // passed from StaticInst 170 val instr = UInt(32.W) 171 val pc = UInt(VAddrBits.W) 172 val foldpc = UInt(MemPredPCWidth.W) 173 val exceptionVec = ExceptionVec() 174 val isFetchMalAddr = Bool() 175 val hasException = Bool() 176 val trigger = TriggerAction() 177 val preDecodeInfo = new PreDecodeInfo 178 val pred_taken = Bool() 179 val crossPageIPFFix = Bool() 180 val ftqPtr = new FtqPtr 181 val ftqOffset = UInt(log2Up(PredictWidth).W) 182 // passed from DecodedInst 183 val srcType = Vec(numSrc, SrcType()) 184 val ldest = UInt(LogicRegsWidth.W) 185 val fuType = FuType() 186 val fuOpType = FuOpType() 187 val rfWen = Bool() 188 val fpWen = Bool() 189 val vecWen = Bool() 190 val v0Wen = Bool() 191 val vlWen = Bool() 192 val isXSTrap = Bool() 193 val waitForward = Bool() // no speculate execution 194 val blockBackward = Bool() 195 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 196 val canRobCompress = Bool() 197 val selImm = SelImm() 198 val imm = UInt(32.W) 199 val fpu = new FPUCtrlSignals 200 val vpu = new VPUCtrlSignals 201 val vlsInstr = Bool() 202 val wfflags = Bool() 203 val isMove = Bool() 204 val uopIdx = UopIdx() 205 val isVset = Bool() 206 val firstUop = Bool() 207 val lastUop = Bool() 208 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 209 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 210 val commitType = CommitType() 211 // rename 212 val srcState = Vec(numSrc, SrcState()) 213 val srcLoadDependency = Vec(numSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 214 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 215 val pdest = UInt(PhyRegIdxWidth.W) 216 // reg cache 217 val useRegCache = Vec(backendParams.numIntRegSrc, Bool()) 218 val regCacheIdx = Vec(backendParams.numIntRegSrc, UInt(RegCacheIdxWidth.W)) 219 val robIdx = new RobPtr 220 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 221 val dirtyFs = Bool() 222 val dirtyVs = Bool() 223 val traceBlockInPipe = new TracePipe(IretireWidthInPipe) 224 225 val eliminatedMove = Bool() 226 // Take snapshot at this CFI inst 227 val snapshot = Bool() 228 val debugInfo = new PerfDebugInfo 229 val storeSetHit = Bool() // inst has been allocated an store set 230 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 231 // Load wait is needed 232 // load inst will not be executed until former store (predicted by mdp) addr calcuated 233 val loadWaitBit = Bool() 234 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 235 // load inst will not be executed until ALL former store addr calcuated 236 val loadWaitStrict = Bool() 237 val ssid = UInt(SSIDWidth.W) 238 // Todo 239 val lqIdx = new LqPtr 240 val sqIdx = new SqPtr 241 // debug module 242 val singleStep = Bool() 243 // schedule 244 val replayInst = Bool() 245 246 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 247 248 val numLsElem = NumLsElem() 249 250 def getDebugFuType: UInt = debug_fuType.getOrElse(fuType) 251 252 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 253 def isLUI32: Bool = this.selImm === SelImm.IMM_LUI32 254 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 255 256 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 257 def isSvinval(flush: Bool) = FuType.isFence(fuType) && 258 Cat(Seq(FenceOpType.sfence, FenceOpType.hfence_v, FenceOpType.hfence_g).map(_ === fuOpType)).orR && !flush 259 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 260 def isNotSvinval = !FuType.isFence(fuType) 261 262 def isHls: Bool = { 263 fuType === FuType.ldu.U && LSUOpType.isHlv(fuOpType) || fuType === FuType.stu.U && LSUOpType.isHsv(fuOpType) 264 } 265 266 def isAMOCAS: Bool = FuType.isAMO(fuType) && LSUOpType.isAMOCAS(fuOpType) 267 268 def srcIsReady: Vec[Bool] = { 269 VecInit(this.srcType.zip(this.srcState).map { 270 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 271 }) 272 } 273 274 def clearExceptions( 275 exceptionBits: Seq[Int] = Seq(), 276 flushPipe : Boolean = false, 277 replayInst : Boolean = false 278 ): DynInst = { 279 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 280 if (!flushPipe) { this.flushPipe := false.B } 281 if (!replayInst) { this.replayInst := false.B } 282 this 283 } 284 285 def needWriteRf: Bool = rfWen || fpWen || vecWen || v0Wen || vlWen 286 } 287 288 trait BundleSource { 289 var wakeupSource = "undefined" 290 var idx = 0 291 } 292 293 /** 294 * 295 * @param pregIdxWidth index width of preg 296 * @param exuIndices exu indices of wakeup bundle 297 */ 298 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int])(implicit p: Parameters) extends XSBundle { 299 val rfWen = Bool() 300 val fpWen = Bool() 301 val vecWen = Bool() 302 val v0Wen = Bool() 303 val vlWen = Bool() 304 val pdest = UInt(pregIdxWidth.W) 305 306 /** 307 * @param successor Seq[(psrc, srcType)] 308 * @return Seq[if wakeup psrc] 309 */ 310 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 311 successor.map { case (thatPsrc, srcType) => 312 val pdestMatch = pdest === thatPsrc 313 pdestMatch && ( 314 SrcType.isFp(srcType) && this.fpWen || 315 SrcType.isXp(srcType) && this.rfWen || 316 SrcType.isVp(srcType) && this.vecWen 317 ) && valid 318 } 319 } 320 def wakeUpV0(successor: (UInt, UInt), valid: Bool): Bool = { 321 val (thatPsrc, srcType) = successor 322 val pdestMatch = pdest === thatPsrc 323 pdestMatch && ( 324 SrcType.isV0(srcType) && this.v0Wen 325 ) && valid 326 } 327 def wakeUpVl(successor: (UInt, UInt), valid: Bool): Bool = { 328 val (thatPsrc, srcType) = successor 329 val pdestMatch = pdest === thatPsrc 330 pdestMatch && ( 331 SrcType.isVp(srcType) && this.vlWen 332 ) && valid 333 } 334 def wakeUpFromIQ(successor: Seq[(UInt, UInt)]): Seq[Bool] = { 335 successor.map { case (thatPsrc, srcType) => 336 val pdestMatch = pdest === thatPsrc 337 pdestMatch && ( 338 SrcType.isFp(srcType) && this.fpWen || 339 SrcType.isXp(srcType) && this.rfWen || 340 SrcType.isVp(srcType) && this.vecWen 341 ) 342 } 343 } 344 def wakeUpV0FromIQ(successor: (UInt, UInt)): Bool = { 345 val (thatPsrc, srcType) = successor 346 val pdestMatch = pdest === thatPsrc 347 pdestMatch && ( 348 SrcType.isV0(srcType) && this.v0Wen 349 ) 350 } 351 def wakeUpVlFromIQ(successor: (UInt, UInt)): Bool = { 352 val (thatPsrc, srcType) = successor 353 val pdestMatch = pdest === thatPsrc 354 pdestMatch && ( 355 SrcType.isVp(srcType) && this.vlWen 356 ) 357 } 358 359 def hasOnlyOneSource: Boolean = exuIndices.size == 1 360 361 def hasMultiSources: Boolean = exuIndices.size > 1 362 363 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 364 365 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 366 367 def exuIdx: Int = { 368 require(hasOnlyOneSource) 369 this.exuIndices.head 370 } 371 } 372 373 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams)(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 374 375 } 376 377 class IssueQueueIQWakeUpBundle( 378 exuIdx: Int, 379 backendParams: BackendParams, 380 copyWakeupOut: Boolean = false, 381 copyNum: Int = 0 382 )(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 383 val loadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 384 val is0Lat = Bool() 385 val params = backendParams.allExuParams.filter(_.exuIdx == exuIdx).head 386 val rcDest = OptionWrapper(params.needWriteRegCache, UInt(RegCacheIdxWidth.W)) 387 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 388 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 389 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 390 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 391 val v0WenCopy = OptionWrapper(copyWakeupOut && params.needV0Wen, Vec(copyNum, Bool())) 392 val vlWenCopy = OptionWrapper(copyWakeupOut && params.needVlWen, Vec(copyNum, Bool())) 393 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 394 395 def fromExuInput(exuInput: ExuInput): Unit = { 396 this.rfWen := exuInput.rfWen.getOrElse(false.B) 397 this.fpWen := exuInput.fpWen.getOrElse(false.B) 398 this.vecWen := exuInput.vecWen.getOrElse(false.B) 399 this.v0Wen := exuInput.v0Wen.getOrElse(false.B) 400 this.vlWen := exuInput.vlWen.getOrElse(false.B) 401 this.pdest := exuInput.pdest 402 } 403 } 404 405 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 406 // vtype 407 val vill = Bool() 408 val vma = Bool() // 1: agnostic, 0: undisturbed 409 val vta = Bool() // 1: agnostic, 0: undisturbed 410 val vsew = VSew() 411 val vlmul = VLmul() // 1/8~8 --> -3~3 412 413 // spec vtype 414 val specVill = Bool() 415 val specVma = Bool() // 1: agnostic, 0: undisturbed 416 val specVta = Bool() // 1: agnostic, 0: undisturbed 417 val specVsew = VSew() 418 val specVlmul = VLmul() // 1/8~8 --> -3~3 419 420 val vm = Bool() // 0: need v0.t 421 val vstart = Vl() 422 423 // float rounding mode 424 val frm = Frm() 425 // scalar float instr and vector float reduction 426 val fpu = Fpu() 427 // vector fix int rounding mode 428 val vxrm = Vxrm() 429 // vector uop index, exclude other non-vector uop 430 val vuopIdx = UopIdx() 431 val lastUop = Bool() 432 // maybe used if data dependancy 433 val vmask = UInt(V0Data().dataWidth.W) 434 val vl = Vl() 435 436 // vector load/store 437 val nf = Nf() 438 val veew = VEew() 439 440 val isReverse = Bool() // vrsub, vrdiv 441 val isExt = Bool() 442 val isNarrow = Bool() 443 val isDstMask = Bool() // vvm, vvvm, mmm 444 val isOpMask = Bool() // vmand, vmnand 445 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 446 447 val isDependOldVd = Bool() // some instruction's computation depends on oldvd 448 val isWritePartVd = Bool() // some instruction's computation writes part of vd, such as vredsum 449 450 val isVleff = Bool() // vleff 451 452 def vtype: VType = { 453 val res = Wire(VType()) 454 res.illegal := this.vill 455 res.vma := this.vma 456 res.vta := this.vta 457 res.vsew := this.vsew 458 res.vlmul := this.vlmul 459 res 460 } 461 462 def specVType: VType = { 463 val res = Wire(VType()) 464 res.illegal := this.specVill 465 res.vma := this.specVma 466 res.vta := this.specVta 467 res.vsew := this.specVsew 468 res.vlmul := this.specVlmul 469 res 470 } 471 472 def vconfig: VConfig = { 473 val res = Wire(VConfig()) 474 res.vtype := this.vtype 475 res.vl := this.vl 476 res 477 } 478 479 def connectVType(source: VType): Unit = { 480 this.vill := source.illegal 481 this.vma := source.vma 482 this.vta := source.vta 483 this.vsew := source.vsew 484 this.vlmul := source.vlmul 485 } 486 } 487 488 class NeedFrmBundle(implicit p: Parameters) extends XSBundle { 489 val scalaNeedFrm = Bool() 490 val vectorNeedFrm = Bool() 491 } 492 493 // DynInst --[IssueQueue]--> DataPath 494 class IssueQueueIssueBundle( 495 iqParams: IssueBlockParams, 496 val exuParams: ExeUnitParams, 497 )(implicit 498 p: Parameters 499 ) extends XSBundle { 500 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 501 502 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 503 rfReadDataCfgSet.map((set: Set[DataConfig]) => 504 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 505 ) 506 )) 507 508 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 509 val rcIdx = OptionWrapper(exuParams.needReadRegCache, Vec(exuParams.numRegSrc, UInt(RegCacheIdxWidth.W))) // used to select regcache data 510 val immType = SelImm() // used to select imm extractor 511 val common = new ExuInput(exuParams) 512 val addrOH = UInt(iqParams.numEntries.W) 513 514 def exuIdx = exuParams.exuIdx 515 def getSource: SchedulerType = exuParams.getWBSource 516 517 def getRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 518 rf.zip(srcType).map { 519 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 520 makeValid(issueValid, rfRd.head) 521 }.toSeq 522 } 523 } 524 525 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 526 val issueQueueParams = this.params 527 val og0resp = Valid(new EntryDeqRespBundle) 528 val og1resp = Valid(new EntryDeqRespBundle) 529 } 530 531 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 532 private val intCertainLat = params.intLatencyCertain 533 private val fpCertainLat = params.fpLatencyCertain 534 private val vfCertainLat = params.vfLatencyCertain 535 private val v0CertainLat = params.v0LatencyCertain 536 private val vlCertainLat = params.vlLatencyCertain 537 private val intLat = params.intLatencyValMax 538 private val fpLat = params.fpLatencyValMax 539 private val vfLat = params.vfLatencyValMax 540 private val v0Lat = params.v0LatencyValMax 541 private val vlLat = params.vlLatencyValMax 542 543 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 544 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 545 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 546 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 547 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 548 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 549 val fpDeqRespSet = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 550 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 551 val v0DeqRespSet = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 552 val vlDeqRespSet = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 553 } 554 555 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 556 private val intCertainLat = params.intLatencyCertain 557 private val fpCertainLat = params.fpLatencyCertain 558 private val vfCertainLat = params.vfLatencyCertain 559 private val v0CertainLat = params.v0LatencyCertain 560 private val vlCertainLat = params.vlLatencyCertain 561 private val intLat = params.intLatencyValMax 562 private val fpLat = params.fpLatencyValMax 563 private val vfLat = params.vfLatencyValMax 564 private val v0Lat = params.v0LatencyValMax 565 private val vlLat = params.vlLatencyValMax 566 567 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 568 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 569 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 570 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 571 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 572 } 573 574 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 575 private val intCertainLat = params.intLatencyCertain 576 private val fpCertainLat = params.fpLatencyCertain 577 private val vfCertainLat = params.vfLatencyCertain 578 private val v0CertainLat = params.v0LatencyCertain 579 private val vlCertainLat = params.vlLatencyCertain 580 581 val intConflict = OptionWrapper(intCertainLat, Bool()) 582 val fpConflict = OptionWrapper(fpCertainLat, Bool()) 583 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 584 val v0Conflict = OptionWrapper(v0CertainLat, Bool()) 585 val vlConflict = OptionWrapper(vlCertainLat, Bool()) 586 } 587 588 class ImmInfo extends Bundle { 589 val imm = UInt(32.W) 590 val immType = SelImm() 591 } 592 593 // DataPath --[ExuInput]--> Exu 594 class ExuInput(val params: ExeUnitParams, copyWakeupOut:Boolean = false, copyNum:Int = 0)(implicit p: Parameters) extends XSBundle { 595 val fuType = FuType() 596 val fuOpType = FuOpType() 597 val src = Vec(params.numRegSrc, UInt(params.srcDataBitsMax.W)) 598 val imm = UInt(32.W) 599 val robIdx = new RobPtr 600 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 601 val isFirstIssue = Bool() // Only used by store yet 602 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 603 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 604 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 605 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 606 val v0WenCopy = OptionWrapper(copyWakeupOut && params.needV0Wen, Vec(copyNum, Bool())) 607 val vlWenCopy = OptionWrapper(copyWakeupOut && params.needVlWen, Vec(copyNum, Bool())) 608 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 609 val pdest = UInt(params.wbPregIdxWidth.W) 610 val rfWen = if (params.needIntWen) Some(Bool()) else None 611 val fpWen = if (params.needFpWen) Some(Bool()) else None 612 val vecWen = if (params.needVecWen) Some(Bool()) else None 613 val v0Wen = if (params.needV0Wen) Some(Bool()) else None 614 val vlWen = if (params.needVlWen) Some(Bool()) else None 615 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 616 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 617 val flushPipe = if (params.flushPipe) Some(Bool()) else None 618 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 619 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 620 val ftqIdx = if (params.needPc || params.replayInst || params.hasStoreAddrFu || params.hasCSR) 621 Some(new FtqPtr) else None 622 val ftqOffset = if (params.needPc || params.replayInst || params.hasStoreAddrFu || params.hasCSR) 623 Some(UInt(log2Up(PredictWidth).W)) else None 624 val predictInfo = if (params.needPdInfo) Some(new Bundle { 625 val target = UInt(VAddrData().dataWidth.W) 626 val taken = Bool() 627 }) else None 628 val loadWaitBit = OptionWrapper(params.hasLoadExu, Bool()) 629 val waitForRobIdx = OptionWrapper(params.hasLoadExu, new RobPtr) // store set predicted previous store robIdx 630 val storeSetHit = OptionWrapper(params.hasLoadExu, Bool()) // inst has been allocated an store set 631 val loadWaitStrict = OptionWrapper(params.hasLoadExu, Bool()) // load inst will not be executed until ALL former store addr calcuated 632 val ssid = OptionWrapper(params.hasLoadExu, UInt(SSIDWidth.W)) 633 // only vector load store need 634 val numLsElem = OptionWrapper(params.hasVecLsFu, NumLsElem()) 635 636 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 637 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 638 val dataSources = Vec(params.numRegSrc, DataSource()) 639 val l1ExuOH = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuVec())) 640 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 641 val loadDependency = OptionWrapper(params.needLoadDependency, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 642 643 val perfDebugInfo = new PerfDebugInfo() 644 645 def exuIdx = this.params.exuIdx 646 647 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = { 648 if (params.isIQWakeUpSink) { 649 require( 650 og0CancelOH.getWidth == l1ExuOH.get.head.getWidth, 651 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}" 652 ) 653 val l1Cancel: Bool = l1ExuOH.get.zip(srcTimer.get).map { 654 case(exuOH: Vec[Bool], srcTimer: UInt) => 655 (exuOH.asUInt & og0CancelOH).orR && srcTimer === 1.U 656 }.reduce(_ | _) 657 l1Cancel 658 } else { 659 false.B 660 } 661 } 662 663 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 664 // src is assigned to rfReadData 665 this.fuType := source.common.fuType 666 this.fuOpType := source.common.fuOpType 667 this.imm := source.common.imm 668 this.robIdx := source.common.robIdx 669 this.pdest := source.common.pdest 670 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 671 this.iqIdx := source.common.iqIdx // Only used by mem feedback 672 this.dataSources := source.common.dataSources 673 this.l1ExuOH .foreach(_ := source.common.l1ExuOH.get) 674 this.rfWen .foreach(_ := source.common.rfWen.get) 675 this.fpWen .foreach(_ := source.common.fpWen.get) 676 this.vecWen .foreach(_ := source.common.vecWen.get) 677 this.v0Wen .foreach(_ := source.common.v0Wen.get) 678 this.vlWen .foreach(_ := source.common.vlWen.get) 679 this.fpu .foreach(_ := source.common.fpu.get) 680 this.vpu .foreach(_ := source.common.vpu.get) 681 this.flushPipe .foreach(_ := source.common.flushPipe.get) 682 this.pc .foreach(_ := source.common.pc.get) 683 this.preDecode .foreach(_ := source.common.preDecode.get) 684 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 685 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 686 this.predictInfo .foreach(_ := source.common.predictInfo.get) 687 this.loadWaitBit .foreach(_ := source.common.loadWaitBit.get) 688 this.waitForRobIdx .foreach(_ := source.common.waitForRobIdx.get) 689 this.storeSetHit .foreach(_ := source.common.storeSetHit.get) 690 this.loadWaitStrict.foreach(_ := source.common.loadWaitStrict.get) 691 this.ssid .foreach(_ := source.common.ssid.get) 692 this.lqIdx .foreach(_ := source.common.lqIdx.get) 693 this.sqIdx .foreach(_ := source.common.sqIdx.get) 694 this.numLsElem .foreach(_ := source.common.numLsElem.get) 695 this.srcTimer .foreach(_ := source.common.srcTimer.get) 696 this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1)) 697 } 698 } 699 700 // ExuInput --[FuncUnit]--> ExuOutput 701 class ExuOutput( 702 val params: ExeUnitParams, 703 )(implicit 704 val p: Parameters 705 ) extends Bundle with BundleSource with HasXSParameter { 706 val data = Vec(params.wbPathNum, UInt(params.destDataBitsMax.W)) 707 val pdest = UInt(params.wbPregIdxWidth.W) 708 val robIdx = new RobPtr 709 val intWen = if (params.needIntWen) Some(Bool()) else None 710 val fpWen = if (params.needFpWen) Some(Bool()) else None 711 val vecWen = if (params.needVecWen) Some(Bool()) else None 712 val v0Wen = if (params.needV0Wen) Some(Bool()) else None 713 val vlWen = if (params.needVlWen) Some(Bool()) else None 714 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 715 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 716 val wflags = if (params.writeFflags) Some(Bool()) else None 717 val vxsat = if (params.writeVxsat) Some(Bool()) else None 718 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 719 val flushPipe = if (params.flushPipe) Some(Bool()) else None 720 val replay = if (params.replayInst) Some(Bool()) else None 721 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 722 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 723 Some(new SqPtr()) else None 724 val trigger = if (params.trigger) Some(TriggerAction()) else None 725 // uop info 726 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 727 // vldu used only 728 val vls = OptionWrapper(params.hasVLoadFu, new Bundle { 729 val vpu = new VPUCtrlSignals 730 val oldVdPsrc = UInt(PhyRegIdxWidth.W) 731 val vdIdx = UInt(3.W) 732 val vdIdxInField = UInt(3.W) 733 val isIndexed = Bool() 734 val isMasked = Bool() 735 val isStrided = Bool() 736 val isWhole = Bool() 737 val isVecLoad = Bool() 738 val isVlm = Bool() 739 }) 740 val debug = new DebugBundle 741 val debugInfo = new PerfDebugInfo 742 } 743 744 // ExuOutput + DynInst --> WriteBackBundle 745 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 746 val rfWen = Bool() 747 val fpWen = Bool() 748 val vecWen = Bool() 749 val v0Wen = Bool() 750 val vlWen = Bool() 751 val pdest = UInt(params.pregIdxWidth(backendParams).W) 752 val data = UInt(params.dataWidth.W) 753 val robIdx = new RobPtr()(p) 754 val flushPipe = Bool() 755 val replayInst = Bool() 756 val redirect = ValidIO(new Redirect) 757 val fflags = UInt(5.W) 758 val vxsat = Bool() 759 val exceptionVec = ExceptionVec() 760 val debug = new DebugBundle 761 val debugInfo = new PerfDebugInfo 762 763 this.wakeupSource = s"WB(${params.toString})" 764 765 def fromExuOutput(source: ExuOutput, wbType: String) = { 766 val typeMap = Map("int" -> 0, "fp" -> 1, "vf" -> 2, "v0" -> 3, "vl" -> 4) 767 this.rfWen := source.intWen.getOrElse(false.B) 768 this.fpWen := source.fpWen.getOrElse(false.B) 769 this.vecWen := source.vecWen.getOrElse(false.B) 770 this.v0Wen := source.v0Wen.getOrElse(false.B) 771 this.vlWen := source.vlWen.getOrElse(false.B) 772 this.pdest := source.pdest 773 this.data := source.data(source.params.wbIndex(typeMap(wbType))) 774 this.robIdx := source.robIdx 775 this.flushPipe := source.flushPipe.getOrElse(false.B) 776 this.replayInst := source.replay.getOrElse(false.B) 777 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 778 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 779 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 780 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 781 this.debug := source.debug 782 this.debugInfo := source.debugInfo 783 } 784 785 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 786 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 787 rfWrite.wen := this.rfWen && fire 788 rfWrite.addr := this.pdest 789 rfWrite.data := this.data 790 rfWrite.intWen := this.rfWen 791 rfWrite.fpWen := false.B 792 rfWrite.vecWen := false.B 793 rfWrite.v0Wen := false.B 794 rfWrite.vlWen := false.B 795 rfWrite 796 } 797 798 def asFpRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 799 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(FpData()).addrWidth))) 800 rfWrite.wen := this.fpWen && fire 801 rfWrite.addr := this.pdest 802 rfWrite.data := this.data 803 rfWrite.intWen := false.B 804 rfWrite.fpWen := this.fpWen 805 rfWrite.vecWen := false.B 806 rfWrite.v0Wen := false.B 807 rfWrite.vlWen := false.B 808 rfWrite 809 } 810 811 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 812 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 813 rfWrite.wen := this.vecWen && fire 814 rfWrite.addr := this.pdest 815 rfWrite.data := this.data 816 rfWrite.intWen := false.B 817 rfWrite.fpWen := false.B 818 rfWrite.vecWen := this.vecWen 819 rfWrite.v0Wen := false.B 820 rfWrite.vlWen := false.B 821 rfWrite 822 } 823 824 def asV0RfWriteBundle(fire: Bool): RfWritePortWithConfig = { 825 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(V0Data()).addrWidth))) 826 rfWrite.wen := this.v0Wen && fire 827 rfWrite.addr := this.pdest 828 rfWrite.data := this.data 829 rfWrite.intWen := false.B 830 rfWrite.fpWen := false.B 831 rfWrite.vecWen := false.B 832 rfWrite.v0Wen := this.v0Wen 833 rfWrite.vlWen := false.B 834 rfWrite 835 } 836 837 def asVlRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 838 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VlData()).addrWidth))) 839 rfWrite.wen := this.vlWen && fire 840 rfWrite.addr := this.pdest 841 rfWrite.data := this.data 842 rfWrite.intWen := false.B 843 rfWrite.fpWen := false.B 844 rfWrite.vecWen := false.B 845 rfWrite.v0Wen := false.B 846 rfWrite.vlWen := this.vlWen 847 rfWrite 848 } 849 } 850 851 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 852 // / 853 // [IssueQueue]--> ExuInput -- 854 class ExuBypassBundle( 855 val params: ExeUnitParams, 856 )(implicit p: Parameters) extends XSBundle { 857 val intWen = Bool() 858 val data = UInt(params.destDataBitsMax.W) 859 val pdest = UInt(params.wbPregIdxWidth.W) 860 } 861 862 class ExceptionInfo(implicit p: Parameters) extends XSBundle { 863 val pc = UInt(VAddrData().dataWidth.W) 864 val instr = UInt(32.W) 865 val commitType = CommitType() 866 val exceptionVec = ExceptionVec() 867 val isPcBkpt = Bool() 868 val isFetchMalAddr = Bool() 869 val gpaddr = UInt(XLEN.W) 870 val singleStep = Bool() 871 val crossPageIPFFix = Bool() 872 val isInterrupt = Bool() 873 val isHls = Bool() 874 val vls = Bool() 875 val trigger = TriggerAction() 876 val isForVSnonLeafPTE = Bool() 877 } 878 879 object UopIdx { 880 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 881 } 882 883 object FuLatency { 884 def apply(): UInt = UInt(width.W) 885 886 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 887 } 888 889 object ExuOH { 890 def apply(exuNum: Int): UInt = UInt(exuNum.W) 891 892 def apply()(implicit p: Parameters): UInt = UInt(width.W) 893 894 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 895 } 896 897 object ExuVec { 898 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 899 900 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 901 902 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 903 } 904 905 class CancelSignal(implicit p: Parameters) extends XSBundle { 906 val rfWen = Bool() 907 val fpWen = Bool() 908 val vecWen = Bool() 909 val v0Wen = Bool() 910 val vlWen = Bool() 911 val pdest = UInt(PhyRegIdxWidth.W) 912 } 913 914 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 915 val uop = new DynInst 916 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 917 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 918 val isFirstIssue = Bool() 919 val flowNum = OptionWrapper(isVector, NumLsElem()) 920 921 def src_rs1 = src(0) 922 def src_rs2 = src(1) 923 def src_stride = src(1) 924 def src_vs3 = src(2) 925 def src_mask = if (isVector) src(3) else 0.U 926 def src_vl = if (isVector) src(4) else 0.U 927 } 928 929 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 930 val uop = new DynInst 931 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 932 val mask = if (isVector) Some(UInt(VLEN.W)) else None 933 val vdIdx = if (isVector) Some(UInt(3.W)) else None // TODO: parameterize width 934 val vdIdxInField = if (isVector) Some(UInt(3.W)) else None 935 val isFromLoadUnit = Bool() 936 val debug = new DebugBundle 937 938 def isVls = FuType.isVls(uop.fuType) 939 } 940 941 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 942 val uop = new DynInst 943 val flag = UInt(1.W) 944 } 945 946 object LoadShouldCancel { 947 def apply(loadDependency: Option[Seq[UInt]], ldCancel: Seq[LoadCancelIO]): Bool = { 948 val ld1Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld1Cancel)).map { case (dep, cancel) => cancel && dep(0)}.reduce(_ || _)) 949 val ld2Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld2Cancel)).map { case (dep, cancel) => cancel && dep(1)}.reduce(_ || _)) 950 ld1Cancel.map(_ || ld2Cancel.get).getOrElse(false.B) 951 } 952 } 953} 954