1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import org.chipsalliance.cde.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 30import system._ 31import utility._ 32import utils._ 33import huancun._ 34import openLLC.{OpenLLCParam} 35import freechips.rocketchip.diplomacy._ 36import xiangshan._ 37import xiangshan.backend.dispatch.DispatchParameters 38import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 39import xiangshan.cache.DCacheParameters 40import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 41import device.{EnableJtag, XSDebugModuleParams} 42import huancun._ 43import coupledL2._ 44import coupledL2.prefetch._ 45import xiangshan.frontend.icache.ICacheParameters 46 47class BaseConfig(n: Int) extends Config((site, here, up) => { 48 case XLen => 64 49 case DebugOptionsKey => DebugOptions() 50 case SoCParamsKey => SoCParameters() 51 case PMParameKey => PMParameters() 52 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 53 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 54 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 55 case JtagDTMKey => JtagDTMKey 56 case MaxHartIdBits => log2Up(n) max 6 57 case EnableJtag => true.B 58}) 59 60// Synthesizable minimal XiangShan 61// * It is still an out-of-order, super-scalaer arch 62// * L1 cache included 63// * L2 cache NOT included 64// * L3 cache included 65class MinimalConfig(n: Int = 1) extends Config( 66 new BaseConfig(n).alter((site, here, up) => { 67 case XSTileKey => up(XSTileKey).map( 68 p => p.copy( 69 DecodeWidth = 6, 70 RenameWidth = 6, 71 RobCommitWidth = 8, 72 FetchWidth = 4, 73 VirtualLoadQueueSize = 24, 74 LoadQueueRARSize = 24, 75 LoadQueueRAWSize = 12, 76 LoadQueueReplaySize = 24, 77 LoadUncacheBufferSize = 8, 78 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 79 RollbackGroupSize = 8, 80 StoreQueueSize = 20, 81 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 82 StoreQueueForwardWithMask = true, 83 // ============ VLSU ============ 84 VlMergeBufferSize = 16, 85 VsMergeBufferSize = 8, 86 UopWritebackWidth = 2, 87 // ============================== 88 RobSize = 48, 89 RabSize = 96, 90 FtqSize = 8, 91 IBufSize = 24, 92 IBufNBank = 6, 93 StoreBufferSize = 4, 94 StoreBufferThreshold = 3, 95 IssueQueueSize = 10, 96 IssueQueueCompEntrySize = 4, 97 dpParams = DispatchParameters( 98 IntDqSize = 12, 99 FpDqSize = 12, 100 LsDqSize = 12, 101 IntDqDeqWidth = 8, 102 FpDqDeqWidth = 6, 103 VecDqDeqWidth = 6, 104 LsDqDeqWidth = 6 105 ), 106 intPreg = IntPregParams( 107 numEntries = 64, 108 numRead = None, 109 numWrite = None, 110 ), 111 vfPreg = VfPregParams( 112 numEntries = 160, 113 numRead = None, 114 numWrite = None, 115 ), 116 icacheParameters = ICacheParameters( 117 nSets = 64, // 16KB ICache 118 tagECC = Some("parity"), 119 dataECC = Some("parity"), 120 replacer = Some("setplru"), 121 ), 122 dcacheParametersOpt = Some(DCacheParameters( 123 nSets = 64, // 32KB DCache 124 nWays = 8, 125 tagECC = Some("secded"), 126 dataECC = Some("secded"), 127 replacer = Some("setplru"), 128 nMissEntries = 4, 129 nProbeEntries = 4, 130 nReleaseEntries = 8, 131 nMaxPrefetchEntry = 2, 132 enableTagEcc = true, 133 enableDataEcc = true, 134 cacheCtrlAddressOpt = Some(AddressSet(0x38022000, 0x7f)) 135 )), 136 // ============ BPU =============== 137 EnableLoop = false, 138 EnableGHistDiff = false, 139 FtbSize = 256, 140 FtbWays = 2, 141 RasSize = 8, 142 RasSpecSize = 16, 143 TageTableInfos = 144 Seq((512, 4, 6), 145 (512, 9, 6), 146 (1024, 19, 6)), 147 SCNRows = 128, 148 SCNTables = 2, 149 SCHistLens = Seq(0, 5), 150 ITTageTableInfos = 151 Seq((256, 4, 7), 152 (256, 8, 7), 153 (512, 16, 7)), 154 // ================================ 155 itlbParameters = TLBParameters( 156 name = "itlb", 157 fetchi = true, 158 useDmode = false, 159 NWays = 4, 160 ), 161 ldtlbParameters = TLBParameters( 162 name = "ldtlb", 163 NWays = 4, 164 partialStaticPMP = true, 165 outsideRecvFlush = true, 166 outReplace = false, 167 lgMaxSize = 4 168 ), 169 sttlbParameters = TLBParameters( 170 name = "sttlb", 171 NWays = 4, 172 partialStaticPMP = true, 173 outsideRecvFlush = true, 174 outReplace = false, 175 lgMaxSize = 4 176 ), 177 hytlbParameters = TLBParameters( 178 name = "hytlb", 179 NWays = 4, 180 partialStaticPMP = true, 181 outsideRecvFlush = true, 182 outReplace = false, 183 lgMaxSize = 4 184 ), 185 pftlbParameters = TLBParameters( 186 name = "pftlb", 187 NWays = 4, 188 partialStaticPMP = true, 189 outsideRecvFlush = true, 190 outReplace = false, 191 lgMaxSize = 4 192 ), 193 btlbParameters = TLBParameters( 194 name = "btlb", 195 NWays = 4, 196 ), 197 l2tlbParameters = L2TLBParameters( 198 l3Size = 4, 199 l2Size = 4, 200 l1nSets = 4, 201 l1nWays = 4, 202 l1ReservedBits = 1, 203 l0nSets = 4, 204 l0nWays = 8, 205 l0ReservedBits = 0, 206 spSize = 4, 207 ), 208 L2CacheParamsOpt = Some(L2Param( 209 name = "L2", 210 ways = 8, 211 sets = 128, 212 echoField = Seq(huancun.DirtyField()), 213 prefetch = Nil, 214 clientCaches = Seq(L1Param( 215 "dcache", 216 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 217 )), 218 )), 219 L2NBanks = 2, 220 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 221 ) 222 ) 223 case SoCParamsKey => 224 val tiles = site(XSTileKey) 225 up(SoCParamsKey).copy( 226 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 227 sets = 1024, 228 inclusive = false, 229 clientCaches = tiles.map{ core => 230 val clientDirBytes = tiles.map{ t => 231 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 232 }.sum 233 val l2params = core.L2CacheParamsOpt.get.toCacheParams 234 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 235 }, 236 simulation = !site(DebugOptionsKey).FPGAPlatform, 237 prefetch = None 238 )), 239 L3NBanks = 1 240 ) 241 }) 242) 243 244// Non-synthesizable MinimalConfig, for fast simulation only 245class MinimalSimConfig(n: Int = 1) extends Config( 246 new MinimalConfig(n).alter((site, here, up) => { 247 case XSTileKey => up(XSTileKey).map(_.copy( 248 dcacheParametersOpt = None, 249 softPTW = true 250 )) 251 case SoCParamsKey => up(SoCParamsKey).copy( 252 L3CacheParamsOpt = None 253 ) 254 }) 255) 256 257class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 258 case XSTileKey => 259 val sets = n * 1024 / ways / 64 260 up(XSTileKey).map(_.copy( 261 dcacheParametersOpt = Some(DCacheParameters( 262 nSets = sets, 263 nWays = ways, 264 tagECC = Some("secded"), 265 dataECC = Some("secded"), 266 replacer = Some("setplru"), 267 nMissEntries = 16, 268 nProbeEntries = 8, 269 nReleaseEntries = 18, 270 nMaxPrefetchEntry = 6, 271 enableTagEcc = true, 272 enableDataEcc = true, 273 cacheCtrlAddressOpt = Some(AddressSet(0x38022000, 0x7f)) 274 )) 275 )) 276}) 277 278class WithNKBL2 279( 280 n: Int, 281 ways: Int = 8, 282 inclusive: Boolean = true, 283 banks: Int = 1, 284 tp: Boolean = true 285) extends Config((site, here, up) => { 286 case XSTileKey => 287 require(inclusive, "L2 must be inclusive") 288 val upParams = up(XSTileKey) 289 val l2sets = n * 1024 / banks / ways / 64 290 upParams.map(p => p.copy( 291 L2CacheParamsOpt = Some(L2Param( 292 name = "L2", 293 ways = ways, 294 sets = l2sets, 295 clientCaches = Seq(L1Param( 296 "dcache", 297 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 298 ways = p.dcacheParametersOpt.get.nWays + 2, 299 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 300 vaddrBitsOpt = Some(p.GPAddrBitsSv48x4 - log2Up(p.dcacheParametersOpt.get.blockBytes)), 301 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 302 )), 303 reqField = Seq(utility.ReqSourceField()), 304 echoField = Seq(huancun.DirtyField()), 305 tagECC = Some("secded"), 306 dataECC = Some("secded"), 307 enableTagECC = true, 308 enableDataECC = true, 309 dataCheck = Some("oddparity"), 310 prefetch = Seq(BOPParameters()) ++ 311 (if (tp) Seq(TPParameters()) else Nil) ++ 312 (if (p.prefetcher.nonEmpty) Seq(PrefetchReceiverParams()) else Nil), 313 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 314 enableRollingDB = site(DebugOptionsKey).EnableRollingDB, 315 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB, 316 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 317 )), 318 L2NBanks = banks 319 )) 320}) 321 322class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 323 case SoCParamsKey => 324 val sets = n * 1024 / banks / ways / 64 325 val tiles = site(XSTileKey) 326 val clientDirBytes = tiles.map{ t => 327 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 328 }.sum 329 up(SoCParamsKey).copy( 330 L3NBanks = banks, 331 L3CacheParamsOpt = Some(HCCacheParameters( 332 name = "L3", 333 level = 3, 334 ways = ways, 335 sets = sets, 336 inclusive = inclusive, 337 clientCaches = tiles.map{ core => 338 val l2params = core.L2CacheParamsOpt.get.toCacheParams 339 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 340 }, 341 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 342 ctrl = Some(CacheCtrl( 343 address = 0x39000000, 344 numCores = tiles.size 345 )), 346 reqField = Seq(utility.ReqSourceField()), 347 sramClkDivBy2 = true, 348 sramDepthDiv = 4, 349 tagECC = Some("secded"), 350 dataECC = Some("secded"), 351 simulation = !site(DebugOptionsKey).FPGAPlatform, 352 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 353 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 354 )), 355 OpenLLCParamsOpt = Some(OpenLLCParam( 356 name = "LLC", 357 ways = ways, 358 sets = sets, 359 banks = banks, 360 fullAddressBits = 48, 361 clientCaches = tiles.map { core => 362 val l2params = core.L2CacheParamsOpt.get 363 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 364 } 365 )) 366 ) 367}) 368 369class WithL3DebugConfig extends Config( 370 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 371) 372 373class MinimalL3DebugConfig(n: Int = 1) extends Config( 374 new WithL3DebugConfig ++ new MinimalConfig(n) 375) 376 377class DefaultL3DebugConfig(n: Int = 1) extends Config( 378 new WithL3DebugConfig ++ new BaseConfig(n) 379) 380 381class WithFuzzer extends Config((site, here, up) => { 382 case DebugOptionsKey => up(DebugOptionsKey).copy( 383 EnablePerfDebug = false, 384 ) 385 case SoCParamsKey => up(SoCParamsKey).copy( 386 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 387 enablePerf = false, 388 )), 389 ) 390 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 391 p.copy( 392 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 393 enablePerf = false, 394 )), 395 ) 396 } 397}) 398 399class MinimalAliasDebugConfig(n: Int = 1) extends Config( 400 new WithNKBL3(512, inclusive = false) ++ 401 new WithNKBL2(256, inclusive = true) ++ 402 new WithNKBL1D(128) ++ 403 new MinimalConfig(n) 404) 405 406class MediumConfig(n: Int = 1) extends Config( 407 new WithNKBL3(4096, inclusive = false, banks = 4) 408 ++ new WithNKBL2(512, inclusive = true) 409 ++ new WithNKBL1D(128) 410 ++ new BaseConfig(n) 411) 412 413class FuzzConfig(dummy: Int = 0) extends Config( 414 new WithFuzzer 415 ++ new DefaultConfig(1) 416) 417 418class DefaultConfig(n: Int = 1) extends Config( 419 new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16) 420 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 421 ++ new WithNKBL1D(64, ways = 4) 422 ++ new BaseConfig(n) 423) 424 425class WithCHI extends Config((_, _, _) => { 426 case EnableCHI => true 427}) 428 429class KunminghuV2Config(n: Int = 1) extends Config( 430 new WithCHI 431 ++ new Config((site, here, up) => { 432 case SoCParamsKey => up(SoCParamsKey).copy(L3CacheParamsOpt = None) // There will be no L3 433 }) 434 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4, tp = false) 435 ++ new WithNKBL1D(64, ways = 4) 436 ++ new DefaultConfig(n) 437) 438 439class KunminghuV2MinimalConfig(n: Int = 1) extends Config( 440 new WithCHI 441 ++ new Config((site, here, up) => { 442 case SoCParamsKey => up(SoCParamsKey).copy(L3CacheParamsOpt = None) // There will be no L3 443 }) 444 ++ new WithNKBL2(128, inclusive = true, banks = 1, tp = false) 445 ++ new WithNKBL1D(32, ways = 4) 446 ++ new MinimalConfig(n) 447) 448 449class XSNoCTopConfig(n: Int = 1) extends Config( 450 (new KunminghuV2Config(n)).alter((site, here, up) => { 451 case SoCParamsKey => up(SoCParamsKey).copy(UseXSNoCTop = true) 452 }) 453) 454 455class XSNoCTopMinimalConfig(n: Int = 1) extends Config( 456 (new KunminghuV2MinimalConfig(n)).alter((site, here, up) => { 457 case SoCParamsKey => up(SoCParamsKey).copy(UseXSNoCTop = true) 458 }) 459) 460 461class FpgaDefaultConfig(n: Int = 1) extends Config( 462 (new WithNKBL3(3 * 1024, inclusive = false, banks = 1, ways = 6) 463 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 464 ++ new WithNKBL1D(64, ways = 4) 465 ++ new BaseConfig(n)).alter((site, here, up) => { 466 case DebugOptionsKey => up(DebugOptionsKey).copy( 467 AlwaysBasicDiff = false, 468 AlwaysBasicDB = false 469 ) 470 case SoCParamsKey => up(SoCParamsKey).copy( 471 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 472 sramClkDivBy2 = false, 473 )), 474 ) 475 }) 476) 477 478class FpgaDiffDefaultConfig(n: Int = 1) extends Config( 479 (new WithNKBL3(3 * 1024, inclusive = false, banks = 1, ways = 6) 480 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 481 ++ new WithNKBL1D(64, ways = 8) 482 ++ new BaseConfig(n)).alter((site, here, up) => { 483 case DebugOptionsKey => up(DebugOptionsKey).copy( 484 AlwaysBasicDiff = true, 485 AlwaysBasicDB = false 486 ) 487 case SoCParamsKey => up(SoCParamsKey).copy( 488 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 489 sramClkDivBy2 = false, 490 )), 491 ) 492 }) 493) 494