xref: /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala (revision c41f725a91c55e75c95c55b4bb0d2649f43e4c83) 
1/***************************************************************************************
2  * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3  * Copyright (c) 2020-2021 Peng Cheng Laboratory
4  *
5  * XiangShan is licensed under Mulan PSL v2.
6  * You can use this software according to the terms and conditions of the Mulan PSL v2.
7  * You may obtain a copy of Mulan PSL v2 at:
8  *          http://license.coscl.org.cn/MulanPSL2
9  *
10  * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11  * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12  * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13  *
14  * See the Mulan PSL v2 for more details.
15  ***************************************************************************************/
16
17package xiangshan.mem.prefetch
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
22import utility.MemReqSource
23import xiangshan._
24import xiangshan.backend._
25import xiangshan.backend.fu.PMPRespBundle
26import xiangshan.mem.L1PrefetchReq
27import xiangshan.mem.Bundles.{LdPrefetchTrainBundle, StPrefetchTrainBundle}
28import xiangshan.cache.mmu.TlbRequestIO
29import coupledL2.PrefetchCtrlFromCore
30
31class PrefetchCtrl(implicit p: Parameters) extends XSBundle {
32  val l1I_pf_enable = Bool()
33  val l2_pf_enable = Bool()
34  val l1D_pf_enable = Bool()
35  val l1D_pf_train_on_hit = Bool()
36  val l1D_pf_enable_agt = Bool()
37  val l1D_pf_enable_pht = Bool()
38  val l1D_pf_active_threshold = UInt(4.W)
39  val l1D_pf_active_stride = UInt(6.W)
40  val l1D_pf_enable_stride = Bool()
41  val l2_pf_store_only = Bool()
42  val l2_pf_recv_enable = Bool()
43  val l2_pf_pbop_enable = Bool()
44  val l2_pf_vbop_enable = Bool()
45  val l2_pf_tp_enable = Bool()
46
47  def toL2PrefetchCtrl(): PrefetchCtrlFromCore = {
48    val res = Wire(new PrefetchCtrlFromCore)
49    res.l2_pf_master_en := l2_pf_enable
50    res.l2_pf_recv_en := l2_pf_recv_enable
51    res.l2_pbop_en := l2_pf_pbop_enable
52    res.l2_vbop_en := l2_pf_vbop_enable
53    res.l2_tp_en := l2_pf_tp_enable
54    res
55  }
56}
57
58class L2PrefetchReq(implicit p: Parameters) extends XSBundle {
59  val addr = UInt(PAddrBits.W)
60  val source = UInt(MemReqSource.reqSourceBits.W)
61}
62
63class PrefetcherIO()(implicit p: Parameters) extends XSBundle {
64  val ld_in = Flipped(Vec(backendParams.LdExuCnt, ValidIO(new LdPrefetchTrainBundle())))
65  val st_in = Flipped(Vec(backendParams.StaExuCnt, ValidIO(new StPrefetchTrainBundle())))
66  val tlb_req = new TlbRequestIO(nRespDups = 2)
67  val pmp_resp = Flipped(new PMPRespBundle())
68  val l1_req = DecoupledIO(new L1PrefetchReq())
69  val l2_req = ValidIO(new L2PrefetchReq())
70  val l3_req = ValidIO(UInt(PAddrBits.W)) // TODO: l3 pf source
71  val enable = Input(Bool())
72}
73
74class PrefetchReqBundle()(implicit p: Parameters) extends XSBundle {
75  val vaddr       = UInt(VAddrBits.W)
76  val paddr       = UInt(PAddrBits.W)
77  val pc          = UInt(VAddrBits.W)
78  val miss        = Bool()
79  val pfHitStream = Bool()
80}
81
82trait PrefetcherParams
83
84abstract class BasePrefecher()(implicit p: Parameters) extends XSModule {
85  val io = IO(new PrefetcherIO())
86
87  io.l3_req.valid := false.B
88  io.l3_req.bits  := DontCare
89}
90